JP2014020977A - Secondary battery cell monitoring circuit and secondary battery module using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the time required for measurement of cell voltages from varying due to the number of vertically stacked secondary battery cells in a battery module constituted of series connection of a plurality of vertically stacked secondary battery cells.SOLUTION: When respective voltage values of vertically stacked secondary battery cells are detected, each secondary battery cell is provided with a comparator COMP for comparing a reference voltage and a cell voltage (partial voltage) and a voltage-current conversion circuit 100 for transmitting the output result of the comparator. The reference voltage of each cell is generated by a current digital-analog conversion circuit (current DAC) 10, and a current value generated by the current DAC corresponds to its control bit Bin. A control bit at the time of inversion of the comparator is detected as a cell voltage by scanning control bits of the current DAC. The control bit of the current DAC at the time of inversion of the comparator is taken in to detect the output voltage value of each cell by one scan independently of the number of cells.

Description

  The present invention relates to a battery cell monitoring circuit for measuring and monitoring a voltage value of each cell of a battery in which a plurality of secondary battery cells are connected in series in a vertical stack, and a secondary battery module using the same.

  Since a battery mounted on a hybrid electric vehicle (HEV) or an electric vehicle (EV) requires a high voltage of about several hundred volts, it is configured by connecting a large number of secondary battery cells in series. Here, secondary batteries, particularly lithium ion batteries, are vulnerable to overcharge and overdischarge, and it is necessary to control the voltage of each secondary battery cell within the upper limit voltage and lower limit voltage ranges. In addition, it is necessary to accurately measure and monitor the charging voltage value of each secondary battery cell.

  In Patent Document 1, each cell is provided with a reference voltage and a comparator (comparison circuit) to detect overcharge voltage and overdischarge voltage.

  In Patent Document 2, a plurality of threshold voltages are provided, and an overcharge voltage and an overdischarge voltage are detected by a comparator.

  In Patent Document 3, switching is performed by a multiplexer, the voltage of each cell is measured by an instrumentation amplifier, an analog-digital conversion circuit is used, and the measured value (digital data) is sent to the outside for monitoring.

JP 2008-136336 A JP 2011-78163 A JP 2011-237266 A

  Prior to the present application, the inventors examined a charging voltage value control technique for each battery cell. The overcharge / overdischarge detection circuit in the battery cell charge voltage value control technique is shown in FIG. 1 of Patent Document 1 and FIG. 1 of Patent Document 2. However, Patent Document 1 and Patent Document 2 can simultaneously detect the overcharge voltage and overdischarge voltage of each battery cell, but cannot measure and monitor the voltage value of the battery cell.

  On the other hand, Patent Document 3 discloses a measurement monitoring circuit for each battery cell voltage value. However, in Patent Document 3, the voltage value of each battery cell can be measured and monitored. However, since switching time by a multiplexer is required, the measurement time increases as the number of cells increases. In order to measure the voltage of all cells without degrading the accuracy within a certain time, it is necessary to increase the multiplexer switching time and the conversion time of the analog-digital conversion circuit. It will increase. Alternatively, instead of increasing the number of control cells of one measurement monitoring circuit, it is possible to configure a system by connecting a number of measurement monitoring circuits in cascade, but the number of measurement monitoring circuits used increases.

  Thus, it is necessary to shorten the time for measuring the secondary battery cell voltage, which becomes noticeable when the number of secondary battery cells is increased.

  An example of a representative one of the present invention is as follows. When each voltage value of the vertically stacked secondary battery cells is detected, a comparator that compares the reference voltage and the cell voltage (divided voltage) to each secondary battery cell and a voltage-current conversion circuit that transmits the output result are provided. The reference voltage of each cell is generated by a current digital-to-analog conversion circuit, and the current value generated by the current digital-to-analog conversion circuit (current DAC) corresponds to the control bit. The control bit of the current DAC is scanned, and the voltage is detected using the control bit when the comparator is inverted as the cell voltage.

  By capturing the control bit of the current DAC at the time when the comparator is inverted, the output voltage value of each cell is detected by one scan regardless of the number of cells. Thereby, the secondary battery cell monitoring circuit which can measure the voltage value of each of the vertically stacked secondary battery cells by one scan and a secondary battery module using the secondary battery cell are realized.

It is a 1st Example of a battery module. It is a time chart of a 1st Example and a 2nd Example. It is a 2nd Example of a battery module. 4 (a) is a circuit example of the output circuit Os _n, FIG. 4 (b) (c) is a timing chart of the output circuit Os _n. It is a 3rd Example of a battery module. It is a time chart of a 3rd Example. It is a detailed time chart of control bit capture. It is another Example of a voltage-current conversion circuit. It is a flowchart of an offset voltage cancellation measurement.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting the battery cell monitoring circuit described below are not particularly limited, but are formed on a semiconductor substrate by a known integrated circuit technology such as bipolar or CMOS (complementary MOS transistor).

  FIG. 1 shows a first embodiment of a battery module to which the battery cell monitoring circuit of the present invention is applied. FIG. 2 shows the time chart.

The secondary battery module is provided with one battery cell monitoring circuit with n secondary battery cells 200 connected in series in a vertical stack as one unit. For example, when each secondary battery cell 200 generates a voltage of 3.7 V, the secondary battery module generates a voltage of (3.7 × n) V (that is, a voltage of the node V _n ). In addition, when a higher voltage is required, desired power is obtained by connecting battery modules in series in series. In this case, an upper control circuit for controlling the plurality of battery modules is required, and a secondary battery system is constructed by the plurality of battery modules and the upper control circuit for controlling them.

As shown in FIG. 1, the battery cell monitoring circuit includes a voltage / current conversion circuit 100 provided corresponding to each secondary battery cell 200 and a common circuit provided in common to the plurality of voltage / current conversion circuits 100. Have. The voltage / current conversion circuit 100 will be described by taking the voltage / current conversion circuit 100 (n) corresponding to the battery cell 200 (n) stacked vertically from the reference potential (GND) as an example. Voltage-current conversion circuit 100 (n) has an output transistor M1 _n for transmitting the comparator COMP _n and the output Vo _n. The comparator COMP _n receives a reference voltage Vi + generated by a current DAC (digital-to-analog converter circuit) and a resistor R1 _n and a cell divided voltage Vi− divided by the resistors R2 _n and R3 _n . The current DAC (Note, are denoted as a constant current source for generating a current I _n in the voltage-current conversion circuit 100 (n)), a current corresponding to the control bit output from the DAC control unit 20 described later Is a circuit that generates Control bits Bin of k bits from the DAC control unit 20 is input in common to the current DAC10 of each voltage-current conversion circuit 100, a current I ₁ ~I _n for generating the respective current DAC is the same current I _out. As described above, in the example of FIG. 1, the current DAC 10 is provided for each secondary battery cell, but a configuration in which a common current DAC is provided for a plurality of secondary battery cells is also possible. However, when a common current DAC is provided, the influence of current variations due to device variations in each voltage-current conversion circuit 100 may affect the monitoring accuracy. With respect to this problem, an embodiment (third embodiment) for improving the monitoring accuracy will be described later.

  Moreover, it has the k bit register | resistor 30 provided corresponding to each of the DAC control part 20 and a secondary battery cell as a common circuit. The bit control unit 20 is realized by a counter that increments the control bits bit by bit, for example. The role of the register 30 will be described later.

The operation of the voltage / current conversion circuit 100 (n) will be described with reference to FIG. The divided voltage of the generated voltage (V _n −V _n−1 ) of the secondary battery cell 200 (n) is input to the negative input Vi− of the comparator COMP _n . On the other hand, to the positive input Vi + of the comparator COMP _n reference voltage generated by resistors R1 _n and the current I _n of the current DAC10 is input. By going to change the control bits Bin of DAC controller 20, to the voltage detection control bit Bin when the output of the comparator COMP _n changes the magnitude relationship between Vi + and Vi- is reversed as the cell voltage.
That is,
Vi + = V _n − (R1 _n × Iout) (1)
Vi− = V _n − (V _n −V _n−1 ) / 2 (where R2 _n resistance value = R3 _n resistance value) (2)
When (R1 _n × Iout) <(V _n −V _n−1 ) / 2, Vi +> Vi− and the output Vo _n [1] of the comparator COMP _n becomes Vo _n = high level, and the PMOS transistor M1 _n Turn off. Therefore, the current It _n [1] does not flow, and the voltage level of the node Vt _n [1] is low.

As the generation current I _n (= Iout) of the current DAC increases corresponding to the control bit Bin, the amount of voltage drop due to the resistor R1 _n increases. As a result, when (R1 _n × Iout)> (V _n −V _n−1 ) / 2, Vi + <Vi−, and the output Vo _n [1] of the comparator COMP _n becomes Vo _n = low level. The PMOS transistor M1 _n is turned on. When the current It _n [1] flows, the voltage level of the node Vt _n [1] becomes a high level. The register 30 (n) takes in k-bit data that is the control bit Bin of the current DAC 10 at the timing when the voltage level of the node Vt _n [1] transits from low to high.

  The voltage-current conversion circuit 100 corresponding to the other secondary battery cells also performs the same operation, so that the generated current of the current DAC 10 is scanned once from the small current to the large current, and thus all the N stages stacked vertically The voltage values of the secondary battery cells 200 (1) to 200 (n) can be taken. For this reason, even if the number n of secondary battery cells to be measured increases, the measurement time can be determined by a single scan time of the current DAC 10, and the speed of voltage detection can be increased.

Since the PMOS transistor M1 _n is applied with a voltage n times as large as the generation voltage of the secondary battery cell between its source and drain, a transistor having a withstand voltage is used. As the other transistors, low breakdown voltage transistors (for example, about 5 V) corresponding to the generation voltage of the secondary battery cell can be used.

FIG. 3 shows a second embodiment of the battery module to which the battery cell monitoring circuit of the present invention is applied. FIG. 2 shows the time chart. In contrast to the configuration example 1, as shown in FIG. 3, by adding the output circuit Os _n in the voltage-current conversion circuit 101 (n) between the comparator output Vo _n transistor M1 _n, pulsed whiskers Noise removal and current consumption suppression are planned.
Figure 4 (a) shows a circuit example 40 of the output circuit Os _n. Output circuit Os _n has a noise removing unit and a one-shot pulse circuit portion. The noise removing unit includes a first filter 41 having a time constant τ1, and a first Schmitt trigger-equipped inverter 42 to which the output of the first filter 41 is input. The one-shot pulse circuit section receives the output of the inverter 42, the second filter 43 having the time constant τ2, the second Schmitt trigger inverter 43 to which the output of the second filter 43 is input, and the inverter 42 and the inverter 43. The NAND circuit 45 is input.

4B and 4C show time charts of the output circuit Os _n . Each waveform indicates an output voltage at nodes A to F shown in FIG. FIG. 4B shows a normal input state, and FIG. 4C shows a beard noise input. When noise is superimposed on the input of the comparator COMP _n or the like, whisker-like noise is generated at the output. In order to avoid such erroneous measurement of the secondary battery cell voltage due to the beard noise, a filter 41 having a time constant τ1 larger than the beard noise is provided on the input side of the one-shot pulse circuit. As a result, noise having a pulse width smaller than the time constant τ1 is removed and is not input to the one-shot pulse circuit.

On the other hand, when a signal having a pulse width longer than the time constant τ1 is input, the output C of the first Schmitt trigger-equipped inverter 42 becomes a high level. In the case of the first embodiment shown in FIG. 1, as shown in the time chart shown in FIG. 2, in the period Tsel where Vi + <Vi−, the PMOS transistor M1 _n remains on and the current It _n is It will continue to flow (see waveform Vt _n (It _n ) [1]). To suppress the power consumption by the current It _n, in the second embodiment, it receives the output C of the first Schmitt trigger with the inverter 42 to the one-shot pulse circuit portion. FIG. 4A shows an example of a one-shot pulse generation circuit configured by a second filter 43 having a time constant τ2, a second Schmitt trigger inverter 44, and a NAND circuit 45. As a result, as shown in the time chart of FIG. 4B, a pulse having a time constant τ 2 can be generated, and the Tsel period in which the current It _n flows can be shortened. FIG. 2 shows the output waveform Vo _n [2] of the comparator COMP _n , the output Vg _n [2] of the output circuit Os _n , and the output waveform Vt _n (It _n ) [2] of the PMOS transistor M1 _n .

Incidentally, what with Schmitt trigger with the inverter as an inverter for the output circuit Os _n as shown in FIG. 4 (a), in order to prevent chattering noise near the threshold voltage of the inverter. Although the invention is not particularly limited, in the example of FIG. 4, the time constant of the filter is easily set by setting the threshold voltage of the Schmitt-triggered inverter to 37% and 63% of the total amplitude.

  In a filter circuit having an input amplitude Vo and a time constant τ composed of a capacitor C and a resistor R, the filter output V has the following relationship.

V = Vo (1-exp (−t / τ)) (3)
When t = τ, V = Vo × 0.63. That is, when the threshold voltage is set to 63% of the input amplitude, the inversion timing t coincides with τ (= CR).

  FIG. 5 shows a third embodiment of the battery module to which the battery cell monitoring circuit of the present invention is applied. 6 and 7 show time charts of the circuit of FIG.

In the third embodiment, one current DAC 10 is provided in common for the secondary battery cell. The voltage / current conversion circuit 102 will be described by taking the voltage / current conversion circuit 102 (n) corresponding to the battery cell 200 (n) vertically stacked from the reference potential (GND) as an example. Compared with the voltage-current conversion circuit 101 (n) in FIG. 3, the common-gate transistor M3 _n , the current bypass transistor M2 _n when the secondary battery cell is not used, the cell voltage holding capacity C1 _n , and the connection point switching Switches sw2 _n , sw3 _n , sw4 _n , a consumption current reduction switch SW1 _n , a dummy switch sw0 _n, and a forced-off switch sw5 _{n of the} output transistor (M1 _n ) are added.

The transistor M3 _n is provided in order to share the current that flows from the common current DAC 10 to the resistor R1 of each voltage-current conversion circuit 102, and serves as a common gate transistor. That is, Iout at the reference voltage Vi + = V _n − (R1 _n × Iout) is all common to the voltage-current conversion circuit 102. On the other hand, the gate-source voltage V _gs of the _common- gate transistor M3 differs among the voltage-current conversion circuits 102 due to process variations and the like. In order to eliminate the influence of the variation in the gate-source voltage V _gs and improve the voltage detection accuracy, the reference voltage and the cell divided voltage are compared from a common potential. This is based on the source point (Vcom) of the common-gate transistor M3. Therefore, to hold the divided voltage value Vi- of the cell voltage to the capacitor C1 _n, performs connection switching the switch _{SW2 n, SW3 n, SW4 n} , it compares the reference voltage Vi + and the comparator COMP _n.

The switch SW1 _n is provided for the purpose of eliminating the current path except when measuring the voltage of the secondary battery cell, and the dummy switch SW0 _n is a normally-on dummy switch. In response to the provision of the switch SW1 _n on the low potential side, the voltage dividing accuracy is improved by providing the dummy switch SW0 _n in series on the high potential side. The forced-off switch SW5 _n is a switch that forcibly turns off the output transistor (M1 _n ) except when measuring the cell voltage.

The circuit operation of the voltage-current conversion circuit 102 (n) in FIG. 5 will be described below using the time charts in FIGS. The switch SW1 _n is off except during the cell voltage measurement, and is turned on during the measurement. When the switches SW1 _n , SW2 _n , and SW3 _n are turned on, a divided value (voltage between the node n1 and the node n2) is stored in the capacitor C1 _n . After Tcharge elapses, the switch SW2 _n and then the switch SW3 _n are turned off, and then the switch SW4 _n is turned on, whereby the capacitor C1 _n is connected between the source point Vcom of the transistor M3 _n and the node n3. As a result, the divided voltage value based on the source point Vcom of the transistor M3 _n is applied to the negative side input Vi− of the comparator COMP _n .
At this time, _if the gate-source voltage Vgs of the transistor M3 _n is Va,
Vi− = V _n − (V _n −V _n−1 ) / 2−Va (where R2 _n resistance value = R3 _n resistance value) (4)
It can be expressed as

On the other hand, the reference voltage Vi + is
_{Vi + = V n -Va- (R1} n × Iout) ... (5)
It can be expressed as In this way, in each voltage-current conversion circuit 102, the reference voltage Vi + and the cell voltage division Vi- are compared with the source point Vcom of the transistor M3 as a reference, and thereby the influence of the variation in the gate-source voltage Vgs of the transistor M3. Can be eliminated.

The voltage of the secondary battery cell can be detected by turning off the switch SW5 _n after setting the reference voltage Vi + and the cell voltage division Vi- based on the source point Vcom of the transistor M3 to the input of the comparator COMP _n. It becomes a state.

Gradually increasing the set current of the current DAC 10, the reference voltage Vi + is a comparator COMP _n output Vo _n when Tckn becomes lower than the cell partial pressure Vi- is inverted from a high level to a low level. As a result, a one-shot pulse is generated by the output circuit Os _n of the voltage-current conversion circuit 102 (n), so that the current It _n flows and the voltage of the node Vt _n becomes high level. 30 (n).

FIG. 7 shows a detailed time chart of control bit fetching. This operation is not limited to the present embodiment, and the same applies to other embodiments. When the control bit Bin of k bits is incremented, the reference voltage Vi + is changed, and the control bit Bin when the reference voltage Vi + coincides with the cell partial pressure Vi− is taken into the corresponding register 30. Thereafter, the switch SW5 _n is turned on, each switch is returned to the initial state, and the series of operations for measuring the secondary battery cell voltage is completed.

The transistor M2 _n is a current bypass transistor when the cell is not used. When the corresponding cell is not used (in FIG. 5, the secondary battery cell 200 (n-1)), the other secondary battery cell can be operated normally by short-circuiting the secondary battery cell.

On the other hand, in the voltage-current conversion circuit 102, the voltage of the negative terminal of the corresponding secondary battery cell is input to the gate of the transistor M2 _n , so that when the cell is used (for example, the cell 200 (n)), the transistor M2 _Since the gate voltage of _n is lower than the source voltage, the transistor is turned off, and no current flows through the source / drain path of the transistor M2 _n . The current Iout of the current DAC10 flows through the transistor M3 _{n as} it is. When the cell is not used (for example, the cell 200 (n−1)), the source voltage of the transistor M2 _n−1 is lower than the gate voltage and the transistor M2 _n−1 is turned on. As a result, the current flowing through the transistor M3 _n-1 is reduced, but the total drain current value of the transistors M2 _n-1 and M3 _n-1 matches the current Iout of the current DAC10. Also in the voltage-current conversion circuit of the cell, the current DAC flows and voltage measurement is possible.

FIG. 8 shows another embodiment of the voltage-current conversion circuit in the battery module to which the battery cell monitoring circuit of the present invention is applied. The voltage-current conversion circuit 103 (n) of the present embodiment cancels the offset voltage Voff of the comparator COMP _n and performs re-measurement at the time of abnormality measurement. Circuit portions other than the voltage-current conversion circuit 103 are, for example, This is the same as the circuit of FIG. FIG. 9 shows an offset voltage cancel measurement flowchart.

In _order to cancel the offset voltage Voff of the comparator COMP _n , it is conceivable to provide an offset cancel circuit as another solution. However, this means increases the circuit scale of the comparator. In this embodiment, in consideration of the relatively low frequency of the voltage measurement of the battery cell, by performing a voltage measurement interchanged signal input of the comparator COMP _n, to cancel the offset voltage Voff of the comparator COMP _n . In addition, by performing voltage measurement multiple times, if the measured value shows a variation greater than the measurement variation due to the offset voltage Voff, the voltage measurement accuracy is determined by determining that the variation is due to noise. Can be increased.

The voltage / current conversion circuit 103 (n) has the following main differences from the voltage / current conversion circuit 102 (n) shown in FIG. In order to switch the input to the comparator COMP _{n of the} reference voltage and the cell voltage division, switching switches SW5 _n , SW6 _n , SW7 _n , SW8 _n are provided on the input side of the comparator COMP _n . Further, in order to invert the output of the comparator COMP _n according to the switching of the comparator COMP _n input, an inverter INV _n and switching switches SW9 _n , SW10 _n , SW11 _n are provided on the output side of the comparator COMP _n .

  The circuit operation will be described with reference to the flowchart of FIG. In step (i), the switches SW5, SW6, and SW9 of the voltage-current conversion circuit 103 are turned on, and the switches SW7, SW8, SW10, and SW11 are turned off, and the voltage detection operation of each secondary battery cell described in the third embodiment is performed. .

  Secondary battery cell 200 (1) voltage Vcell1 '= Vc1 (1), secondary battery cell 200 (2) voltage Vcell2' = Vc2 (1), detected in step (i) Assume that the voltage Vcelln ′ = Vcn (1) of the battery cell 200 (n).

  Next, in step (ii), the input to the comparator COMP is switched. That is, the switches SW5, SW6, and SW9 of the voltage-current conversion circuit 103 are turned off, and the switches SW7, SW8, SW10, and SW11 are turned on, and the voltage detection operation of each secondary battery cell described in the third embodiment is performed.

  The voltage Vcell1 ″ = Vc1 (2) of the secondary battery cell 200 (1), the voltage Vcell2 ″ = Vc2 (2) of the secondary battery cell 200 (2) detected in step (ii), and the secondary Assume that the voltage Vcelln ″ = Vcn (2) of the battery cell 200 (n).

  Thereafter, in step (iii) -1, a difference Vck between the first measurement value Vc (1) and the second measurement value Vc (2) of each secondary battery cell is obtained. That is, the voltage difference Vck1 = Vc1 (1) −Vc1 (2) of the secondary battery cell 200 (1), the voltage difference Vck2 = Vc2 (1) −Vc2 (2) of the secondary battery cell 200 (2),. The voltage difference of the secondary battery cell 200 (n) is Vckn = Vcn (1) −Vcn (2).

  In step (iii) -2, it is identified whether the voltage difference detected by the two measurements in each secondary battery cell 200 is due to the input offset voltage of the comparator COMP or due to noise. For example, it is determined whether or not the absolute value of Vck is smaller than or greater than a predetermined threshold, which is the input offset voltage Voff × 2 + α (arbitrary value) of the comparator COMP in this embodiment.

  That is, if | Vck | <2 × Voff + α (α is an arbitrary value), the voltage of the secondary battery cell is obtained in step (iv), and | Vck |> 2 × Voff + α (α is an arbitrary value) If there is, the process returns to step (i), and the voltage of the secondary battery cell is detected again. In the case of remeasurement, it is also possible to perform control so that voltage detection is performed only for the secondary battery cell determined to be due to noise.

  Finally, in step (iv), the voltage of the secondary battery cell is determined from the two measured values. As an example, an average value of two measured values (Vcell ′, Vcell ″) is used. That is, the voltage Vcell1 = (Vc1 (1) + Vc1 (2)) / 2 of the secondary battery cell 200 (1), two Voltage Vcell2 of secondary battery cell 200 (2) = (Vc2 (1) + Vc2 (2)) / 2,... Voltage Vcelln = (Vcn (1) + Vcn (2) of secondary battery cell 200 (n) ) / 2.

As an example, when the input offset voltage Voff of the comparator COMP _n of the voltage-current conversion circuit 103 (n) is 10 mV and the voltage of the secondary battery cell 200 (n) is 3.6V, the cell voltage value (Vcelln) at this time is measured. The flow of is shown.

In step (i), the inputs Vi + and Vi- of comparator COMP _n are
Vi + = Vcom−Vref−Voff (6)
Vi- = Vcom-Vcelln / 2 (7)
Here, Vcom is a source voltage of the transistor M3 _n , and Vref is a voltage drop due to the resistor R1n. In the formula (7), the resistance value of the resistor R2 _n = the resistance of the resistor R3 _n, has a potential difference generated by the capacitor C1n and Vcelln / 2.

Comparator COMP _n is inverted when Vi + = Vi-.
Vcom−Vref−Voff = Vcom−Vcell / 2 (8)
Thus, the setting value Iout (Iout = Vref / R1 _n ) of the current DAC that satisfies Vref = Vcell / 2−Voff is read.

In this case, since the input offset voltage Voff of the comparator COMP _n exists,
Vref = Vcelln / 2−Voff = 3.6 / 2−0.01 = 1.79 (V)
Therefore, the voltage Vcelln ′ = Vcn (1) = Vref × 2 = 3.58 (V) of the secondary battery 200 (n) in the first measurement.

Next, in step (ii), the inputs Vi + and Vi- of the comparator COMP _n are
Vi + = Vcom−Vcelln / 2−Voff (9)
Vi- = Vcom-Vref (10)
It becomes. Note that in step (ii), the output side of the comparator COMP _n is a path through the inverter INV _n , so that the transistor M1 _n operates in the same manner as in step (i).

Comparator COMP _n is inverted when Vi + = Vi-.
Vcom−Vcelln / 2−Voff = Vcom−Vref (11)
Thus, the setting value Iout (Iout = Vref / R1 _n ) of the current DAC that satisfies Vref = Vcell / 2 + Voff is read.

In this case, since the input offset voltage Voff of the comparator COMP _n exists,
Vref = Vcelln / 2−Voff = 3.6 / 2 + 0.01 = 1.81 (V)
Therefore, the voltage Vcelln ″ = Vcn (2) = Vref × 2 = 3.62 (V) of the secondary battery 200 (n) in the second measurement.

In steps (iii) -1 and 2, the magnitude relation between | Vckn | = | Vcn (1) −Vcn (2) | and (2 × Voff + α) is compared.
| Vckn | = | Vcn (1) −Vcn (2) | = | 3.58−3.62 | = 0.04 (V)
On the other hand, when 2 × Voff + α = 100 mV,
| Vckn | = 0.04 <0.1, so go to step (iv). as a result,
Vcelln = (Vcn (1) + Vcn (2)) / 2 = (3.58 + 3.62) /2=2.60 (V) (12)
Thus, the cell voltage Vcelln (= 3.60 V) from which the offset voltage Voff has been removed is obtained.
If there is an abnormality during the second measurement and Vcelln '= Vcn (2) = 3.9V versus Vcelln' = Vcn (1) = 3.6V, then step (iii)
In step iii), | Vckn | = | Vcn (1) −Vcn (2) | = | 3.6−3.9 | = 0.3 (V). In this case, the value exceeds 2 × Voff + α = 100 mV. Return to) and repeat the measurement. With the above flow, the offset voltage of the comparator COMP can be removed, and a remeasurement routine for abnormal measurement can be performed. Needless to say, the flow of offset voltage cancellation measurement shown in FIG. 9 is a measurement method applicable to the circuits of the first to fourth embodiments.

DESCRIPTION OF SYMBOLS 100 ... Voltage current conversion circuit, 200 ... Secondary battery cell, 10 ... Current DAC, 20 ... DAC control part, 300 ... Register.

Claims (10)

A secondary battery cell monitoring circuit for monitoring output voltages of a plurality of secondary battery cells connected in series,
A plurality of voltage-current conversion circuits;
A current digital-to-analog converter circuit;
A DAC control unit that generates a control bit for controlling a current amount of the current digital-to-analog converter circuit;
The voltage-current conversion circuit includes a comparator and an output transistor that compare a reference voltage corresponding to a current generated by the current digital-to-analog conversion circuit and a corresponding partial voltage of the secondary battery cell,
The DAC control unit scans the control bit, and detects the output voltage of each of the plurality of secondary battery cells from the value of the control bit when the output current starts to flow through the output transistor according to the output inversion of the comparator. Secondary battery cell monitoring circuit. In claim 1,
The current digital-to-analog conversion circuit is provided in common for the plurality of voltage-current conversion circuits,
The current generated by the current digital-to-analog converter circuit is supplied to the voltage-current converter circuit through a grounded gate transistor that inputs the output voltage of the corresponding secondary battery cell to the gate,
The comparator compares a reference voltage corresponding to a current generated by the current digital-to-analog converter circuit with a divided voltage of the corresponding secondary battery cell with reference to a source point of the common-gate transistor. circuit. In claim 2,
The voltage-current conversion circuit has a capacity,
After maintaining the partial pressure of the secondary battery cell corresponding to the capacity, the secondary battery with reference to the source point of the grounded gate transistor is switched by switching one end of the capacity to the source point of the grounded gate transistor. A secondary battery cell monitoring circuit for obtaining a partial pressure of the cell. In claim 2,
The voltage-current conversion circuit has a bypass transistor,
The drain of the bypass transistor is connected to the drain of the grounded gate transistor, the source of the bypass transistor is connected to a potential point for supplying the reference voltage to the comparator, and the gate of the bypass transistor is connected to the corresponding secondary battery cell. A secondary battery cell monitoring circuit to which a negative terminal voltage is input. In any one of Claims 1 thru | or 4,
In the voltage-current conversion circuit, an output circuit is provided between the comparator and the output transistor,
The output circuit has a filter with a predetermined time constant,
A secondary battery cell monitoring circuit in which the output of the comparator is input to the filter. In claim 5,
The output circuit further includes a one-shot pulse circuit, and generates a pulse signal in response to the output inversion of the comparator. In any one of Claims 1 thru | or 4,
The reference voltage is input to the positive side input of the comparator, the partial voltage of the secondary battery cell corresponding to the negative side input of the comparator is input, and the first output voltage of the corresponding secondary battery cell is detected. And
The reference voltage is input to the negative input of the comparator, the partial voltage of the secondary battery cell corresponding to the positive input of the comparator is input, and the second output voltage of the corresponding secondary battery cell is detected. And
A secondary battery cell monitoring circuit that determines an output voltage of a corresponding secondary battery cell based on the first output voltage and the second output voltage. In claim 7,
A secondary battery cell monitoring circuit that detects the output voltage of the secondary battery cell again when the difference between the first output voltage and the second output voltage is greater than a predetermined threshold value. A secondary battery module having a plurality of secondary battery cells connected in series and a secondary battery cell monitoring circuit for monitoring the output voltage of each of the plurality of secondary battery cells,
The secondary battery cell monitoring circuit includes a plurality of voltage-current conversion circuits,
A current digital-to-analog conversion circuit; and a DAC control unit that generates a control bit for controlling a current amount of the current digital-to-analog conversion circuit,
The voltage-current conversion circuit includes a comparator and an output transistor that compare a reference voltage corresponding to a current generated by the current digital-to-analog conversion circuit and a corresponding partial voltage of the secondary battery cell,
The DAC control unit scans the control bit, and detects the output voltage of each of the plurality of secondary battery cells from the value of the control bit when the output current starts to flow through the output transistor according to the output inversion of the comparator. Battery module. In claim 9,
The current digital-to-analog conversion circuit is provided in common for the plurality of voltage-current conversion circuits,
The current generated by the current digital-to-analog converter circuit is supplied to the voltage-current converter circuit through a grounded gate transistor that inputs the output voltage of the corresponding secondary battery cell to the gate,
The said comparator is a secondary battery module which compares the reference voltage according to the electric current which the said current digital analog conversion circuit produces | generates with the reference | standard of the source point of the said gate common transistor, and the partial pressure of the said secondary battery cell.

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