JP2014016749A - Switch device and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switch device and a system in which an address space on a transmission host side is associated with an address in a usable area of a memory in a transmission destination host.SOLUTION: A switch device includes a first port, a second port, an address conversion information storage part, and a setting part, wherein the first port includes: a first storage part in which first address information for specifying a first space used for data transmission processing out of address spaces of a first device side is registered; and a third storage part in which second address information for specifying an area usable by a second storage part owned by the first device is registered. The second port has: a fourth storage part in which third address information for specifying a second space used for data transmission processing out of address spaces on a second device side is registered; and a sixth storage part in which fourth address information for specifying an area usable by a fifth storage part owned by the second device is registered. The setting part sets address conversion information in association with the third address information registered in the address conversion information storage part.

Description

  The present invention relates to a switch device and a system.

  2. Description of the Related Art Conventionally, a technique for transferring data between hosts using, for example, PCI-Express is known.

  For example, Patent Document 1 discloses an image processing apparatus in which hosts are connected by PCI-Express for the purpose of transferring data between hosts. More specifically, two hosts are connected via a PCI-Express switch having a non-transparent port, and the PCI space of the transfer source host is mapped to the memory space of the transfer destination host in the switch. A configuration is disclosed in which mutual memory areas can be referred to each other.

  However, in the technique disclosed in Patent Document 1, in order to set the address indicating the usable area of the memory of one host as a translation address for the other PCI space, each host is set to the partner host at the time of initial setting. It is necessary to know in advance the usable area of the memory.

  For this reason, it is necessary for each host to define the usable area of each other's memory space in advance in the interface specification, or to notify the other host of the usable area via another interface.

  The present invention has been made in view of the above, and the transfer source host side that performs data transfer via the switch device does not need to know the address of the usable area of the memory of the transfer destination host. It is an object of the present invention to provide a switch device and system capable of associating the address space with the address of the usable area of the memory in the transfer destination host.

  In order to solve the above-described problems and achieve the object, the present invention provides a first port to which a first device is connected, a second port to which a second device is connected, and an address space on the first device side. And an address conversion information storage unit that stores address conversion information indicating a correspondence relationship between the address space on the second device side and a setting unit that sets the address conversion information, and the first port includes the first port A first storage unit in which first address information for designating a first space used for data transfer processing among address spaces on the first device side is registered at the time of initial setting of one port, and initial setting of the first port And a third storage unit in which second address information designating a usable area of the second storage unit of the first device is registered, and the second port is an initial setting of the second port Sometimes the second device side A fourth storage unit in which third address information designating a second space used for data transfer processing in the address space is registered; and a fifth storage unit of the second device at the time of initial setting of the second port. A sixth storage unit in which fourth address information for designating a usable area is registered, and the setting unit registers the third address registered in the fourth storage unit at the time of initial setting of the second port. Address information is registered in the address conversion information storage unit, and the second address information registered in the third storage unit is registered in the address conversion information storage unit at the time of initial setting of the first port. 3 is a switch device that sets the address conversion information in association with address information.

  The present invention is a system comprising a first device, a second device, and a switch device that connects the first device and the second device, wherein the switch device is connected to the first device. Address conversion for storing address conversion information indicating a correspondence relationship between the first port, the second port to which the second device is connected, and the address space on the first device side and the address space on the second device side An information storage unit; and a setting unit configured to set the address conversion information. The first port is used for data transfer processing in the address space on the first device side when the first port is initially set. A first storage unit in which first address information for specifying the first space is registered, and a second address for specifying a usable area of the second storage unit of the first device at the time of initial setting of the first port. Information is registered A third address for designating a second space used for data transfer processing in the address space on the second device side when the second port is initially set. A fourth storage unit in which information is registered, and a sixth storage unit in which fourth address information for designating a usable area of the fifth storage unit included in the second device at the time of initial setting of the second port is registered The first device includes: a first control unit that performs control to register the first address information in the first storage unit at the time of initial setting of the first port; and initial setting of the first port A second control unit that performs control to register the second address information in the third storage unit, and the second device stores the third address information in the initial setting of the second port. Third control unit for performing control registered in the fourth storage unit A fourth control unit that performs control to register the fourth address information in the sixth storage unit at the time of initial setting of the second port, and the setting unit at the time of initial setting of the second port, The third address information registered in the fourth storage unit is registered in the address conversion information storage unit, and the second address information registered in the third storage unit at the time of initial setting of the first port, In the system, the address conversion information is set in association with the third address information registered in the address conversion information storage unit.

  According to the present invention, even if the transfer source host that performs data transfer via the switch device does not know the address of the usable area of the memory in the transfer destination host, the address space on the transfer source host side is transferred to the transfer destination host. It can be associated with the address of the usable area of the internal memory.

FIG. 1 is a block diagram illustrating a schematic configuration example of a system according to the embodiment. FIG. 2 is a diagram for explaining address conversion when data is written to the memory space of the counterpart host via PCI-Express. FIG. 3 is a block diagram illustrating a detailed configuration example of the system according to the embodiment. FIG. 4 is a diagram illustrating an example of the data structure of the address conversion table. FIG. 5 is a flowchart showing an example of processing for setting the base address and size of the PCI memory space in the address conversion table in the initial setting of the first port and the second port. FIG. 6 is a flowchart showing an example of processing for setting address translation information in the address translation table in the initial setting of the first port and the second port. FIG. 7 is a flowchart illustrating an example of data transfer processing between the first host system and the second host system.

  Hereinafter, embodiments of a switch device and a system according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating a schematic configuration example of a system 1 according to the present embodiment. As shown in FIG. 1, the system 1 includes a first host system 100 and a second host system 200.

  In the example of FIG. 1, the first host system 100 includes a first host device 10 and a switch device 20, and the second host system 200 includes a second host device 30. The first host device 10 includes a CPU 11 and a storage device 12. The CPU 11 and the storage device 12 are connected to each other via the chipset 13. The chipset 13 is a root complex that is an element constituting a PCI-Express system.

  The second host device 30 has the same configuration as the first host device 10 and includes a CPU 31 and a storage device 32. The CPU 31 and the storage device 32 are connected to each other via a chip set 33. The chip set 33 is a root complex that is an element constituting a PCI-Express system.

  The switch device 20 is a switch chip composed of a semiconductor integrated circuit. Here, the switch device 20 is a PCI-Express switch, but is not limited to this. The switch device 20 includes a first port 40 to which the first host device 10 is connected and a second port 50 to which the second host device 30 is connected. The chip set 13 has a plurality of PCI-Express ports for connecting to the first port 40. In this example, the first port 40 is configured as an Upstream port. The chip set 33 has a plurality of PCI-Express ports for connecting to the second port 50. In this example, the second port 50 is configured as a non-transparent port. In short, in the present embodiment, the standard of the bus connecting the first port 40 and the host device 10 and the standard of the bus connecting the second port 50 and the second host device 30 are PCI-Express.

  In this example, the first host device 10 corresponds to the “first device” in the claims, and the second host device 30 corresponds to the “second device” in the claims.

  In the present embodiment, when the first host system 100 is started, the first port 40 is initialized. At this time, the address for specifying the usable area in the storage device 12 is set to the address on the second host device 30 side. Associate with space. In addition, when the second host system 200 is started, the second port 50 is initialized. At this time, an address that designates an available area in the storage device 32 is associated with an address space on the first host device 10 side. . Detailed contents will be described later.

  FIG. 2 is a diagram for explaining address conversion when data is written to the memory space of the counterpart host via PCI-Express. An address conversion operation during memory access between hosts will be described with reference to FIGS. When data is transferred from the first host device 10 to the second host device 30 (in other words, when data is transferred from the first host system 100 to the second host system 200), first, the first host device 10 When the CPU 11 performs write access to the PCI memory space in its own address space, a packet having the address in the PCI memory space as the write address is transmitted from the chip set 13 to the switch device 20 (PCI-Express switch). The switch device 20 that has received the packet converts the address in the packet into a translation address (an area in the storage device 32) corresponding to an address in the packet (an address in the PCI memory space) set in an address translation table to be described later. Is transmitted to the host device 30. Thereafter, the chip set 33 that has received the packet writes data in the usable area of the storage device 32 indicated by the address in the packet, and the data transfer is completed.

  When data is transferred from the second host device 30 to the first host device 10 (in other words, when data is transferred from the second host system 200 to the first host system 100), first, the second host device 30 When the CPU 31 performs write access to the PCI memory space in its own address space, a packet having the address in the PCI memory space as the write address is transmitted from the chip set 33 to the switch device 20. The switch device 20 that has received the packet converts the address in the packet to the conversion address (the area in the storage device 12) corresponding to the address in the packet (the address of the PCI memory space) set in the address conversion table described later. The address is rewritten to the designated address) and transmitted to the first host device 10. Thereafter, the chip set 13 that has received the packet writes data in the area of the storage device 12 indicated by the address in the packet, and the data transfer is completed.

  FIG. 3 is a diagram illustrating a detailed configuration example of the system 1 of the present embodiment. First, a configuration example of the switch device 20 will be described. In addition, about the part which overlaps with description of FIG. 1, description is abbreviate | omitted suitably. As illustrated in FIG. 3, the switch device 20 includes an address conversion table 60, a setting unit 70, and an address conversion unit 80 in addition to the first port 40 and the second port 50.

  The first port 40 includes a reception buffer 41, a transmission buffer 42, a base address / size register 43, an available area register 44, and a request size register 45. Similarly, the second port 50 includes a reception buffer 51, a transmission buffer 52, a base address / size register 53, an available area register 54, and a request size register 55. This will be specifically described below.

  The reception buffer 41 functions as a buffer memory that temporarily holds packets transmitted from the chipset 13 when performing data transfer from the first host device 10 to the second host device 30. The transmission buffer 42 functions as a buffer memory that temporarily holds a packet transmitted from the second port 50 side when transferring data from the second host device 30 to the first host device 10.

  The base address / size register 43 corresponds to the “first storage unit” in the claims. When the first port 40 is initially set, the base address / size register 43 includes data transfer processing (“access processing”) in the address space on the first host device 10 side. First address information for designating a PCI memory space (corresponding to “first space” in the claims) used for the first address information is registered. More specifically, when the first port 40 is initialized, the base address / size register 43 registers the base address and size of the PCI memory space of the first host device 10 as first address information.

  At the time of initial setting of the first port 40, the first size information indicating the size of the PCI memory space (first space) included in the first address information registered in the base address / size register 43 is the second size information. It is also registered in the request size register 55 on the port 50 side. The request size register 55 corresponds to the “eight storage unit” in the claims, and first size information indicating the size of the PCI memory space of the first host device 10 is registered when the first port 40 is initialized.

  The usable area register 44 corresponds to the “third storage unit” in the claims, and when the first port 40 is initially set, the first host device 10 has the storage device 12 (in the “second storage unit” in the claims). 2nd address information specifying the usable area is registered. More specifically, at the time of initial setting of the first port 40, the usable area register 44 registers the start address of the usable area in the storage device 12 of the first host device 10 as the second address information. Is done.

  The reception buffer 51 functions as a buffer memory that temporarily holds packets transmitted from the chip set 33 when data transfer is performed from the second host device 30 to the first host device 10. The transmission buffer 52 functions as a buffer memory that temporarily holds packets transmitted from the first port 40 side when performing data transfer from the first host device 10 to the second host device 30.

  The base address / size register 53 corresponds to the “fourth storage unit” in the claims, and the PCI memory space used for data transfer processing in the address space on the second host device 30 side when the second port 50 is initially set. Third address information designating (corresponding to “second space” in the claims) is registered. More specifically, when the second port 50 is initially set, the base address / size register 53 registers the base address and size of the PCI memory space of the second host device 30 as third address information.

  The second size information indicating the size of the PCI memory space (second space) included in the third address information registered in the base address / size register 53 when the second port 50 is initialized is the first port. It is also registered in the request size register 45 on the 40 side. The request size register 45 corresponds to the “seventh storage unit” in the claims, and second size information indicating the size of the PCI memory space of the second host device 30 is registered when the second port 50 is initialized.

  The usable area register 54 corresponds to the “sixth storage unit” in the claims, and when the second port 50 is initially set, the second host device 30 has the storage device 32 (in the “fifth storage unit” in the claims). 4th address information designating the usable area is registered. More specifically, at the initial setting of the second port 50, the available area register 54 registers the start address of the usable area in the storage device 32 of the second host device 30 as the fourth address information. Is done. The above is the configuration of the first port 40 and the second port 50 in the present embodiment.

  The address translation table 60 corresponds to the “address translation information storage unit” in the claims, and stores address translation information indicating the correspondence between the address space on the first host device 10 side and the address space on the second host device 30 side. To do. In the present embodiment, the address translation table 60 designates first address information that designates the PCI memory space of the first host device 10 and a usable area in the storage device 32 that the second host device 30 has. Address conversion information (corresponding to the first address conversion information in FIG. 3 for convenience of explanation) indicating the correspondence with the address information is stored in a table format. The address conversion table 60 also includes third address information that designates the PCI memory space of the second host device 30, and second address information that designates an available area in the storage device 12 of the first host device 10. Address conversion information (for convenience of description, expressed as second address conversion information in FIG. 3) is stored in a table format.

  FIG. 4 is a diagram illustrating an example of the data structure of the address conversion table 60. As shown in FIG. 4, the address conversion table 60 includes a data transfer direction, a base address of the PCI memory space, a size of the PCI memory space, a conversion address, and a conversion address setting flag indicating whether the conversion address is valid. Are stored in association with each other. In the example of FIG. 4, when the data transfer direction is “0”, the base address and size of the PCI memory space of the first host device 10 and the translation address corresponding thereto are stored in the storage device 32 included in the second host device 30. Is stored in association with the first address of the usable area (that is, the first address conversion information described above is stored). On the other hand, when the data transfer direction is “1”, the base address and size of the PCI memory space of the second host device 30 and the translation address corresponding thereto can be used in the storage device 12 of the first host device 10. The first address of the area is stored in association with it (that is, the second address conversion information described above is stored). The translation address setting flag is set to “1 (valid)” when the base address and size of the corresponding PCI memory space and the translation address are set.

  Returning to FIG. 3 again, the description will be continued. The setting unit 70 sets address conversion information. More specifically, the setting unit 70 stores the second address stored in the base address / size register 53 (corresponding to “fourth storage unit” in the claims) at the time of initial setting of the second port 50. The 3-address information (the base address and size of the PCI memory space of the second host device 30) is registered in the address conversion table 60. Then, when the first port 40 is initially set, the setting unit 70 stores the second address information (the second address information) registered in the usable area register 44 (corresponding to the “third storage unit” in the claims) on the first port 40 side. The address conversion information (the above-mentioned second address conversion information) is associated with the third address information registered in the address conversion table 60 in correspondence with the third address information registered in the address conversion table 60). Set.

  The setting unit 70 also stores first address information (corresponding to “first storage unit” in the claims) stored in the base address / size register 43 on the first port 40 side when the first port 40 is initially set. The base address and size of the PCI memory space of the first host device 10 are registered in the address conversion table 60. Then, when the second port 50 is initially set, the setting unit 70 stores the fourth address information (second address) registered in the second port side usable area register 54 (corresponding to the “sixth storage unit” in the claims). The address conversion information (the above-mentioned first address conversion information) is set by associating the first address information registered in the address conversion table 60 with the first address information registered in the address conversion table 60. To do.

  The address translation unit 80 performs address translation using the address translation table 60 in data transfer between the first host system 100 and the second host system 200. Detailed contents will be described later.

  Next, a configuration example of the first host device 10 will be described. In addition, about the part which overlaps with description of FIG. 1, description is abbreviate | omitted suitably. As shown in FIG. 3, the CPU 11 in the first host device 10 includes a first control unit 14 and a second control unit 15. When the first port 40 is initially set, the first control unit 14 sends first address information indicating the base address and size of the PCI memory space of the first host device 10 to the base address / size register 43 on the first port 40 side. Control to register to.

  When the first port 40 is initially set, the second control unit 15 uses the second address information indicating the start address of the usable area in the storage device 12 of the first host device 10 on the first port 40 side. Control to register in the possible area register 44 is performed. More specifically, the second control unit 15 performs control to read the request size register 45 (corresponding to the “seventh storage unit” in the claims) at the time of initial setting of the first port 40. If the second size information indicating the size of the PCI memory space of the second host device 30 is registered in the request size register 45, an area for the size indicated by the registered second size information is stored in the storage device 12. Control to ensure Then, the second control unit 15 performs control to register the start address of the secured area in the usable area register 44 as second address information. The functions of the first control unit 14 and the second control unit 15 described above are realized by the CPU 11 executing a program stored in a ROM or the like.

  Next, a configuration example of the second host device 30 will be described. In addition, about the part which overlaps with description of FIG. 1, description is abbreviate | omitted suitably. As shown in FIG. 3, the CPU 31 in the second host device 30 includes a third control unit 34 and a fourth control unit 35. When the second port 50 is initially set, the third control unit 14 sends third address information indicating the base address and size of the PCI memory space of the second host device 30 to the base address / size register 53 on the second port 50 side. Control to register to.

  When the second port 50 is initially set, the fourth control unit 35 uses the fourth address information indicating the start address of the usable area in the storage device 32 of the second host device 30 on the second port 50 side. Control to register in the possible area register 54 is performed. More specifically, the fourth control unit 35 performs control to read the request size register 55 (corresponding to the “eighth storage unit” in the claims) at the time of initial setting of the second port 50. If the first size information indicating the size of the PCI memory space of the first host device 10 is registered in the request size register 55, an area for the size indicated by the registered first size information is stored in the storage device 32. Control to ensure Then, the fourth control unit 35 performs control to register the start address of the secured area in the usable area register 54 as fourth address information. The functions of the third control unit 34 and the fourth control unit 35 described above are realized by the CPU 31 executing a program stored in a ROM or the like.

  Next, when the first host system 100 and the second host system 200 are started up (at startup), the base address and size of the PCI memory space are set to the address conversion table 60 in the initial setting of the first port 40 and the second port 50. An example of the processing to be set will be described according to the flowchart of FIG.

  First, processing for setting the base address and size of the PCI memory space of the first host device 10 in the address conversion table 60 will be described. When the initial setting of the first port 40 is started when the first host system 100 is started up, the first control unit 14 uses the base address and size of the PCI memory space of the first host device 10 as the first address information. Control to register in the address / size register 43 is performed (S501). The setting unit 70 sets the base address and size registered in the base address / size register 43 in the address conversion table 60. The size registered in the base address / size register 43 is also registered in the request size register 55 on the second port 50 side (S502). If the setting for all the base address spaces is completed (result of S503: YES), the process ends. On the other hand, if there is an unset base address space (result of S503: NO), whether or not to end the setting is selected (step S504), and the next base address space is not ended without completing the setting. When setting is performed (result of step S504: NO), the above process is repeated. On the other hand, when the setting is to be ended (result of step S504: YES), the processing is ended as it is.

  Next, processing for setting the base address and size of the PCI memory space of the second host device 30 in the address conversion table 60 will be described. When the second host system 200 is started up and the initial setting of the second port 50 is started, the third control unit 34 uses the base address and size of the PCI memory space of the second host device 30 as the third address information. Control to register in the address / size register 53 is performed (S501). The setting unit 70 sets the base address and size registered in the base address / size register 53 in the address conversion table 60. The size registered in the base address / size register 53 is also registered in the request size register 45 on the first port side 40 (S502). If the setting for all the base address spaces is completed (result of S503: YES), the process ends. On the other hand, if there is an unset base address space (result of S503: NO), whether or not to end the setting is selected (step S504), and the next base address space is not ended without completing the setting. When setting is performed (result of step S504: NO), the above process is repeated. On the other hand, when the setting is to be ended (result of step S504: YES), the processing is ended as it is.

  Next, when the first host system 100 and the second host system 200 are started up (started up), the address conversion information is stored in the address conversion table 60 in the switch device 20 at the initial setting of the first port 40 and the second port 50. An example of the process of setting is described with reference to the flowchart of FIG.

  First, the process for setting the second address translation information described above in the initial setting of the first port 40 will be described. When the first host system 100 is started up, when the initial setting of the first port 40 is started, the second control unit 15 reads the request size register 45 on the first port 40 side, and the value is stored in the request size register 45. Control is performed to confirm whether or not it is present (S601). If the read value is other than “0” (result of step S601: YES), the third address information (base address and size of the PCI memory space of the second host device 30) is set in the address conversion table 60. Control for securing the usable area for the requested size in the storage device 12 (S602), and registering the start address of the secured area in the usable area register 44 on the first port 40 side (S603). On the other hand, if “0” is set in the request size register (the result of step S601: NO), it is determined that the third address information is not set in the address conversion table 60, and the processing is ended as it is.

  The setting unit 70 sets the address registered in the usable area register 44 as a conversion address for the corresponding PCI space base address of the address conversion table 60 (base address of the PCI memory space of the second host device 30). “1” is set in the address setting flag (S604). Here, if the conversion address has been set for all the base addresses (result of step S605: YES), the process ends. On the other hand, if there is a base address for which no conversion address is set (result of step S605: NO), it is selected whether or not to end the setting (S606), and the next base is set without ending the setting. When the conversion address is set for the address (result of step S606: NO), the above process is repeated. On the other hand, when the setting is to be ended (result of step S606: YES), the process is ended as it is.

  Next, processing for setting the first address translation information described above in the initial setting of the second port 50 will be described. When starting the initial setting of the second port 50 when the second host system 200 is started, the fourth control unit 35 reads the request size register 55 on the second port 50 side, and the value is stored in the request size register 55. Control is performed to confirm whether or not it is present (S601). If the read value is other than “0” (result of step S601: YES), the first address information (base address and size of the PCI memory space of the first host device 10) is set in the address conversion table 60. Control to secure an available area for the requested size in the storage device 32 (S602), and register the start address of the secured area in the available area register 54 on the second port 50 side (S603). On the other hand, if “0” is set in the request size register (the result of step S601: NO), it is determined that the first address information is not set in the address conversion table 60, and the processing is ended as it is.

  The setting unit 70 sets the address registered in the usable area register 54 as a conversion address for the corresponding PCI space base address (the base address of the PCI memory space of the first host device 10) in the address conversion table 60, and converts the address. “1” is set in the address setting flag (S604). Here, if the conversion address has been set for all the base addresses (result of step S605: YES), the process ends. On the other hand, if there is a base address for which no conversion address is set (result of step S605: NO), it is selected whether or not to end the setting (S606), and the next base is set without ending the setting. When the conversion address is set for the address (result of step S606: NO), the above process is repeated. On the other hand, when the setting is to be ended (result of step S606: YES), the process is ended as it is.

  Next, an example of data transfer processing between the first host system 100 and the second host system 200 will be described with reference to the flowchart of FIG. First, a process of writing data from the first host system 100 to the storage device 32 of the second host system 200 will be described. In this example, the first host system 100 is a transfer source host, and the second host system 200 is a transfer destination host. When the CPU 11 performs write access to the PCI memory space of the first host device 10, a packet is transmitted from the chip set (Root Complex) 13 to the switch device 20 that is a PCI-Express switch. When the packet is received by the first port 40 (result of step S700: YES), the address translation unit 80 retrieves the write address set in the packet and searches the address translation table 60 (step S701). If there is a space (base address and size) including the write address among the base addresses and sizes of the PCI memory space set in the address conversion table 60 (result of step S702: YES), the conversion address setting flag Is confirmed (step S703). If the translation address setting flag is set to “1” (result of step S703: YES), the address translation unit 80 rewrites the write address in the packet with the translation address (step S704), and the second host system. The packet is transmitted to 200 chip sets (Root Complex) 33 (step S705).

  On the other hand, if there is no space including the write address in step S702 (result of step S702: NO), or the write address of the base address and size of the PCI memory space set in the address conversion table 60 is If the conversion address setting flag is “0 (invalid)” even if the included space exists (the result of step S703: NO), it is determined that there is no corresponding address, and the transfer source chip set (Root Complex) 13 In response to this, an error packet is transmitted (step S706).

  Next, a process for writing data from the second host system 200 to the storage device 12 of the first host system 100 will be described. In this example, the second host system 200 is a transfer source host, and the first host system 100 is a transfer destination host. When the CPU 31 performs write access to the PCI memory space of the second host device 30, a packet is transmitted from the chip set (Root Complex) 33 to the switch device 20 that is a PCI-Express switch. When the packet is received by the second port 50 (result of step S700: YES), the address translation unit 80 retrieves the write address set in the packet and searches the address translation table 60 (step S701). If there is a space including the write address among the base address and size of the PCI memory space set in the address conversion table 60 (result of step S702: YES), the conversion address setting flag is checked (step S703). ). If the translation address setting flag is set to “1” (result of step S703: YES), the address translation unit 80 rewrites the write address in the packet with the translation address (step S704), and the first host system The packet is transmitted to 100 chip sets (Root Complex) 13 (step S705).

  On the other hand, if there is no space including the write address in step S702 (result of step S702: NO), or the write address of the base address and size of the PCI memory space set in the address conversion table 60 is If the conversion address setting flag is “0 (invalid)” even if the included space exists (result of step S703: NO), it is determined that there is no corresponding address, and the transfer source chip set (Root Complex) 33 In response to this, an error packet is transmitted (step S706).

  As described above, the setting unit 70 is stored in the base address / size register 53 (corresponding to the “fourth storage unit” in the claims) at the time of initial setting of the second port 50. The third address information (the base address and size of the PCI memory space of the second host device 30) is registered in the address conversion table 60. Then, when the first port 40 is initially set, the setting unit 70 stores the second address information (the second address information) registered in the usable area register 44 (corresponding to the “third storage unit” in the claims) on the first port 40 side. The address conversion information (second address conversion information) is set in association with the third address information registered in the address conversion table 60 with the first address of the usable area in the storage device 12 included in one host device 10. Therefore, it is not necessary for the second host device 30 to know in advance the usable area of the storage device 12 in the first host device 10.

  The setting unit 70 also stores first address information (corresponding to “first storage unit” in the claims) stored in the base address / size register 43 on the first port 40 side when the first port 40 is initially set. The base address and size of the PCI memory space of the first host device 10 are registered in the address conversion table 60. Then, when the second port 50 is initially set, the setting unit 70 stores the fourth address information (second address) registered in the second port side usable area register 54 (corresponding to the “sixth storage unit” in the claims). Since the address conversion information (first address conversion information) is set by associating the first address information registered in the address conversion table 60 with the first address of the usable area in the storage device 32 of the host device 30. The first host device 10 does not need to know in advance the usable area of the storage device 32 in the second host device 30. In other words, according to the present embodiment, the transfer source host that performs data transfer via the switch device 20 does not know the address of the usable area of the memory in the transfer destination host, and does not use the PCI memory space of the transfer source host. Can be associated with the address of an available area in the memory of the transfer destination host.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

1 system 10 first host device 12 storage device 13 chipset 14 first control unit 15 second control unit 20 switch device 30 second host device 32 storage device 33 chipset 34 third control unit 35 fourth control unit 40 first Port 41 Reception buffer 42 Transmission buffer 43 Base address / size register 44 Available area register 45 Request size register 50 Second port 51 Reception buffer 52 Transmission buffer 53 Base address / size register 54 Available area register 55 Request size register 60 Address conversion Table 70 Setting unit 80 Address conversion unit 100 Host system 200 Host system

JP 2008-067242 A

Claims (10)

A first port to which the first device is connected;
A second port to which the second device is connected;
An address translation information storage unit for storing address translation information indicating a correspondence relationship between the address space on the first device side and the address space on the second device side;
A setting unit for setting the address conversion information,
The first port is
A first storage unit in which first address information for designating a first space used for data transfer processing among the address spaces on the first device side is registered at the time of initial setting of the first port;
A third storage unit in which second address information specifying an available area of the second storage unit of the first device is registered at the time of initial setting of the first port;
The second port is
A fourth storage unit in which third address information for designating a second space used for data transfer processing among the address spaces on the second device side is registered at the time of initial setting of the second port;
A sixth storage unit in which fourth address information specifying an available area of the fifth storage unit of the second device is registered at the time of initial setting of the second port;
The setting unit
When the second port is initially set, the third address information registered in the fourth storage unit is registered in the address conversion information storage unit,
At the time of initial setting of the first port, the address conversion information is set by associating the second address information registered in the third storage unit with the third address information registered in the address conversion information storage unit To
Switch device. The setting unit
At the time of initial setting of the first port, the first address information registered in the first storage unit is registered in the address conversion information storage unit,
The address conversion information is set by associating the fourth address information registered in the sixth storage unit with the first address information registered in the address conversion information storage unit at the time of initial setting of the second port. To
The switch device according to claim 1. The first port further includes a seventh storage unit in which second size information indicating a size of the second space, which is included in the third address information, is registered when the second port is initialized.
The second address information is information that can specify an area for the size indicated by the second size information registered in the seventh storage unit among the available regions of the second storage unit.
The switch device according to claim 1. The second port further includes an eighth storage unit in which first size information indicating a size of the first space, which is included in the first address information, is registered when the first port is initialized.
The third address information is information that can specify an area for the size indicated by the first size information registered in the eighth storage unit among the usable regions of the fifth storage unit.
The switch device according to claim 1. The standard of the bus that connects the first port and the first device and the standard of the bus that connects the second port and the second device are PCI-Express,
The second port is a non-transparent port;
The switch device according to claim 1. The first space and the second space are PCI memory spaces.
The switch device according to claim 1. A system comprising a first device, a second device, and a switch device connecting the first device and the second device,
The switch device is
A first port to which the first device is connected;
A second port to which the second device is connected;
An address translation information storage unit for storing address translation information indicating a correspondence relationship between the address space on the first device side and the address space on the second device side;
A setting unit for setting the address conversion information,
The first port is
A first storage unit in which first address information for designating a first space used for data transfer processing among the address spaces on the first device side is registered at the time of initial setting of the first port;
A third storage unit in which second address information specifying an available area of the second storage unit of the first device is registered at the time of initial setting of the first port;
The second port is
A fourth storage unit in which third address information for designating a second space used for data transfer processing among the address spaces on the second device side is registered at the time of initial setting of the second port;
A sixth storage unit in which fourth address information specifying an available area of the fifth storage unit of the second device is registered at the time of initial setting of the second port;
The first device includes:
A first control unit that performs control to register the first address information in the first storage unit at the time of initial setting of the first port;
A second control unit that performs control to register the second address information in the third storage unit at the time of initial setting of the first port;
The second device includes:
A third control unit for performing control to register the third address information in the fourth storage unit at the time of initial setting of the second port;
A fourth control unit that performs control to register the fourth address information in the sixth storage unit at the time of initial setting of the second port;
The setting unit
When the second port is initially set, the third address information registered in the fourth storage unit is registered in the address conversion information storage unit,
At the time of initial setting of the first port, the address conversion information is set by associating the second address information registered in the third storage unit with the third address information registered in the address conversion information storage unit To
system. The setting unit
At the time of initial setting of the first port, the first address information registered in the first storage unit is registered in the address conversion information storage unit,
The address conversion information is set by associating the fourth address information registered in the sixth storage unit with the first address information registered in the address conversion information storage unit at the time of initial setting of the second port. To
The system of claim 7. The first port further includes a seventh storage unit in which second size information indicating a size of the second space, which is included in the third address information, is registered when the second port is initialized.
When the second size information is registered in the seventh storage unit at the time of initial setting of the first port, the second control unit indicates the second size information registered in the seventh storage unit An area for the size is secured in the second storage unit, and information for identifying the secured area is registered in the third storage unit as the second address information.
The system of claim 7. The second port further includes an eighth storage unit in which first size information indicating a size of the first space, which is included in the first address information, is registered when the first port is initialized.
When the first size information is registered in the eighth storage unit at the time of initial setting of the second port, the fourth control unit indicates the first size information registered in the eighth storage unit. An area for the size is secured in the fifth storage unit, and information for identifying the secured area is registered in the sixth storage unit as the fourth address information.
The system of claim 8.

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