JP2014014054A - A/d conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D conversion device that improves A/D conversion accuracy.SOLUTION: At every control timing, a correction value VDh is added to a digital value VDs to produce a corrected digital value VDt. If a comparator 2 determines that a voltage Vref is higher than a voltage Vc at the control timing, a constant value is consecutively added to a digital value VD_0 until the determination that the voltage Vref is higher than the voltage Vc is denied, and the digital value VDs is subtracted from the result of addition to produce the correction value VDh. If the comparator 2 does not determine that the voltage Vref is higher than the voltage Vc at the control timing, a constant value is consecutively subtracted from the digital value VD_0 until the determination that the voltage Vref is higher than the voltage Vc is asserted, and the digital value VDs is subtracted from the result of subtraction to produce the correction value VDh.

Description

  The present invention relates to an A / D converter that converts an analog value into a digital value.

  In general, the output value of the A / D converter includes errors caused by the characteristics of the A / D converter, such as absolute error, differential nonlinearity error, and integral nonlinearity error.

  Thus, for example, it is conceivable to improve the A / D conversion accuracy by correcting the output value using a correction value stored in advance in the A / D converter.

  However, if the correction value stored in advance in the A / D conversion device is fixed, an error caused by the influence of environmental changes (for example, changes in ambient temperature) cannot be suppressed. There is a risk of hindering improvement.

  Therefore, for example, an A / D converter that converts the first analog value into a digital value, an adder that adds the digital value and the correction value, and a D / A that converts the digital value into a second analog value. In the A / D conversion device including the conversion unit, the first analog value is changed until the first and second analog values coincide with each other, that is, until the difference between the first and second analog values becomes zero. It is conceivable to increase the correction value when it is larger than the second analog value and decrease the correction value when the second analog value is larger than the first analog value (for example, see Patent Document 1). In this way, by changing the correction value so that the difference between the first and second analog values becomes zero, errors caused by the influence of environmental changes can be suppressed.

Japanese Utility Model Publication No. 1-171133

  However, as described above, when the correction value is varied so that the difference between the first and second analog values becomes zero, in order to determine whether or not the difference has become zero, It is necessary to add an A / D converter for converting the difference into a digital value. For this reason, an error generated in the added A / D conversion unit is included in the output value, which may hinder improvement in A / D conversion accuracy.

  Therefore, an object of the present invention is to provide an A / D conversion device capable of improving A / D conversion accuracy.

  An A / D conversion device according to the present invention includes an A / D conversion unit, a D / A conversion unit, a latch unit, a comparator, and a control unit.

  The A / D converter converts the input first analog value into a digital value.

  The D / A conversion unit converts the digital value into a second analog value.

  The latch unit latches the first analog value at each control timing.

  The comparator determines whether the first analog value latched by the latch unit is greater than the second analog value.

  The control unit adds a correction value to the digital value at each control timing to obtain a corrected digital value.

  In addition, when the control unit determines that the first analog value latched by the latch unit by the comparator at the control timing is larger than the second analog value, the comparator causes the latch unit to A constant value is continuously added to the digital value until it is determined that the latched first analog value is not larger than the second analog value, and the result obtained by subtracting the digital value from the addition result is corrected. Value.

  In addition, when it is not determined that the first analog value latched by the latch unit by the comparator is larger than the second analog value, the control unit latches the first analog value latched by the comparator by the latch unit. The constant value is continuously subtracted from the digital value until it is determined that the analog value of 1 is larger than the second analog value, and the result obtained by subtracting the digital value from the subtraction result is used as the correction value.

  As a result, the correction value can be varied in accordance with the variation in the output value of the A / D conversion unit, so that an error caused by an environmental change can be suppressed. Further, since the correction value is changed using the first and second analog value magnitude determination results of the first and second analog values as they are, it is not necessary to convert the magnitude relation judgment result into a digital value, and the A / D converter Therefore, an error generated in the AD conversion unit is not included in the output value of the A / D conversion unit. Therefore, A / D conversion accuracy can be improved.

  Further, when the control unit determines that the correction value is equal to or greater than a threshold value, the control unit may determine that the A / D conversion unit is faulty.

  Thereby, it can be determined whether or not the A / D converter is out of order.

  According to the present invention, the A / D conversion accuracy of the A / D conversion device can be improved.

It is a figure which shows the A / D converter of embodiment of this invention. It is a flowchart which shows an example of operation | movement of a control part. 5 is a timing chart illustrating an example of an analog value VA, a control signal SR, a control signal SDC, a voltage Vref, a square wave SDA, a signal Comp, and a voltage Vc. It is a flowchart which shows an example of an initial process. It is a figure which shows an example of a correction value table.

  FIG. 1 is a diagram illustrating an A / D conversion apparatus according to an embodiment of the present invention.

  The A / D conversion device 1 shown in FIG. 1 includes a comparator 2, npn bipolar transistors 3 to 5, capacitors 6 and 7, resistors 8 and 9, a diode 10, and a control circuit 11. The npn bipolar transistors 3 to 5 may be configured by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a mechanical relay, or the like.

  The positive input terminal of the comparator 2 is connected to one end of the capacitor 6 and the cathode terminal of the diode 10. The anode terminal of the diode 10 is connected to the emitter terminal of the npn bipolar transistor 3, and the collector terminal of the npn bipolar transistor 3 is connected to the output terminal of the sensor 12 (for example, a current sensor, a voltage sensor, or a temperature sensor). Yes. The collector terminal of npn bipolar transistor 4 is connected to one end of capacitor 6, and the emitter terminal of npn bipolar transistor 4 is connected to one end of resistor 8. The other end of the resistor 8 is connected to the other end of the capacitor 6 and the ground. The negative input terminal of the comparator 2 is connected to one end of the resistor 9, one end of the capacitor 7, and the emitter terminal of the npn bipolar transistor 5. The collector terminal of the npn bipolar transistor 5 is connected to the power supply Vdd, and the other end of the resistor 9 and the other end of the capacitor 7 are connected to the ground.

  The control circuit 11 includes an A / D conversion unit 13, a storage unit 14, a square wave output unit 15, and a control unit 16.

  The control unit 16 is configured by, for example, a CPU (Central Processing Unit) or a programmable device (FPGA (Field Programmable Gate Array) or PLD (Programmable Logic Device)), and the program stored in the storage unit 14 is stored. By executing this, the output value of the A / D converter 13 is corrected and the correction value is stored or updated. The storage unit 14 includes a RAM (Random Access Memory), a ROM (Read Only Memory), and the like. Further, the A / D conversion unit 13 and the square wave output unit 15 may be configured integrally with the control unit 16 as, for example, a partial function of the CPU. Further, the latch portion described in the claims may be configured by, for example, an npn bipolar transistor 3, a capacitor 6, a diode 10, and the like. The D / A converter described in the claims may be configured by, for example, an npn bipolar transistor 5, a capacitor 7, a resistor 9, a square wave output unit 15, and the like.

  At the control timing, the A / D conversion unit 13 converts an analog voltage value (hereinafter, analog value VA) (first analog value) (first analog value) output from the sensor 12 into a digital value VDt by operation control by the control unit 16. The digital value VDt is converted and stored in the storage unit 14 as the digital value VDs and the digital value VD_0.

  At the control timing, the square wave output unit 15 outputs a square wave SDA having a duty corresponding to the digital value VD_0 stored in the storage unit 14 through operation control by the control unit 16. For example, the square wave output unit 15 is a CPU capable of processing a digital value of 10 [bit] (0 to 1024 [LSB]), and when the digital value VD_0 is 512 [LSB], the square wave output unit 15 outputs a square wave SDA having a duty of 50 [%]. Further, when the square wave SDA changes from the low level to the high level and the npn bipolar transistor 5 is turned on, the capacitor 7 is charged by the current flowing from the power source Vdd to the capacitor 7 via the npn bipolar transistor 5, and the square wave SDA is changed from the high level. When the level becomes low and the npn bipolar transistor 5 is turned off, the capacitor 7 is discharged by the resistor 9. Thereby, the voltage of the capacitor 7 becomes the voltage Vc corresponding to the duty of the square wave SDA. That is, the digital value VD_0 is converted into an analog value (second analog value) and input to the negative input terminal of the comparator 2.

  The control unit 16 controls the operation of the A / D conversion unit 13 and the square wave output unit 15 and controls the on / off of the npn bipolar transistors 3 and 4.

  For example, the control unit 16 turns on the npn bipolar transistor 3 by changing the control signal SR input to the base terminal of the npn bipolar transistor 3 from the low level to the high level, and changes the control signal SR from the high level to the low level. As a result, the npn bipolar transistor 3 is turned off. When npn bipolar transistor 3 is turned on, capacitor 6 is charged by the current flowing from sensor 12 to capacitor 6 through npn bipolar transistor 3 and diode 10. As a result, the voltage Vref of the capacitor 6 after charging is input to the plus input terminal of the comparator 2 as a voltage (first analog value) equal to or substantially equal to the analog value VA.

  For example, the control unit 16 turns on the npn bipolar transistor 4 by changing the control signal SDC input to the base terminal of the npn bipolar transistor 4 from low level to high level, and changes the control signal SDC from high level to low level. Thus, the npn bipolar transistor 4 is turned off. When the npn bipolar transistor 4 is turned on, a current flows from the capacitor 6 to the ground via the npn bipolar transistor 4 and the resistor 8, and the capacitor 6 is discharged.

  FIG. 2 is a flowchart illustrating an example of the operation of the control unit 16. FIG. 3 is a timing chart showing an example of the analog value VA, the control signal SR, the control signal SDC, the voltage Vref, the square wave SDA, the signal Comp, and the voltage Vc.

  First, the control unit 16 performs initial processing at the control timing (S21).

  FIG. 4 is a flowchart illustrating an example of the initial process.

  First, the control unit 16 starts an AD conversion operation by the A / D conversion unit 13 and changes the control signal SR from a low level to a high level (S41). For example, as shown in FIG. 3, when the control timing t1 or control timing t2 is reached, the control unit 16 starts the AD conversion operation in the A / D conversion unit 13 and sets the control signal SR to a high level for a certain period. . At this time, the control unit 16 stores the digital value VDt output from the A / D conversion unit 13 in the storage unit 14 as the digital value VDs and the digital value VD_0. Further, the voltage Vref is input to the plus input terminal of the comparator 2.

  Next, the control unit 16 starts the output operation of the square wave SDA by the square wave output unit 15 (S42). At this time, the voltage Vc is input to the negative input terminal of the comparator 2.

  Then, the control unit 16 determines whether the voltage Comp output from the comparator 2 is high level or low level, stores the magnitude relation determination result in the storage unit 14 as an initial value (S43), and ends the initial processing. To do. For example, at the control timing t1 shown in FIG. 3, since the voltage Vref input to the positive input terminal of the comparator 2 is larger than the voltage Vc input to the negative input terminal of the comparator 2, the signal Comp output from the comparator 2 is The high level is set, and “high level” is stored in the storage unit 14 as the initial value magnitude relation determination result. Further, at the control timing t2 shown in FIG. 3, the voltage Vref input to the positive input terminal of the comparator 2 is smaller than the voltage Vc input to the negative input terminal of the comparator 2, so that the signal Comp output from the comparator 2 is The low level is set, and “low level” is stored in the storage unit 14 as the initial value magnitude determination result.

  Next, as illustrated in FIG. 2, when the control unit 16 determines that the correction value VDh corresponding to the digital value VDs is already stored in the storage unit 14 after the initial process is completed (Yes in S22), The correction value VDh is added to the digital value VDs to obtain a corrected digital value VDt (S23). For example, as illustrated in FIG. 5, when a correction value table in which the correction value VDh is stored in association with the digital value VDs is stored in the storage unit 14, the control unit 16 sets the digital value VDs as “512 [ When “LSB]” is input, “+1” is extracted from the correction value table as the correction value VDh, and after correction by calculating “512 [LSB]” + “+ 1 [LSB]” = “513 [LSB]” "513 [LSB]" is obtained as the digital value VDt.

  Next, the control unit 16 determines whether or not the magnitude relation determination result of the initial value stored in the storage unit 14 is “high level” (S24).

  If the control unit 16 determines that the magnitude relationship determination result of the initial value is “high level” (S24 is Yes), the control unit 16 determines that the level of the signal Comp (size relationship determination result) is not “high level” ( After S25 is No), after adding a certain value (for example, 1 [LSB] which is the minimum digital value) to the digital value VD_0 stored in the storage unit 14 (S26), the digital value VD ′ which is the addition result is added. The digital value VD_0 stored in the storage unit 14 as the digital value VD_0 is overwritten, and a square wave SDA having a duty corresponding to the overwritten digital value VD_0 is output from the square wave output unit 15 (S27). For example, in the correction value VDh update cycle after the control timing t1 shown in FIG. 3, the magnitude relationship determination result of the initial value is “high level”, and when 1 [LSB] is added once to the digital value VD_0, The relationship judgment result becomes “low level”. Thereby, an error (absolute error, differential nonlinearity error, integral nonlinearity error, etc.) generated in the A / D conversion unit 13 at this time can be recognized as +1 [LSB]. When the magnitude relation determination result changes from “high level” to “low level”, the digital value VD ′ as the previous addition result is overwritten on the digital value VD_0 stored in the storage unit 14 as the digital value VD_0. May be. In S26, the constant value added to the digital value VD_0 is not limited to 1 [LSB].

  On the other hand, when the control unit 16 determines that the magnitude relation determination result as the initial value is “low level” (No in S24), it is determined that the level of the signal Comp (magnitude relation determination result) is not “low level”. (S28 is No), a certain value (for example, 1 [LSB] which is the minimum digital value VD) is subtracted from the digital value VD_0 stored in the storage unit 14 (S29), and then the subtraction result is digital. The value VD ′ is overwritten on the digital value VD_0 stored in the storage unit 14 as the digital value VD_0, and a square wave SDA having a duty corresponding to the overwritten digital value VD_0 is output from the square wave output unit 15 (S30). . For example, in the correction value VDh update cycle after the control timing t2 shown in FIG. 3, when the initial value magnitude relation determination result is “low level” and 1 [LSB] is subtracted twice from the digital value VD_0, The relationship judgment result becomes “high level”. Thereby, an error (absolute error, differential nonlinearity error, integral nonlinearity error, etc.) generated in the A / D conversion unit 13 at this time can be recognized as -2 [LSB]. When the magnitude relation determination result changes from “low level” to “high level”, the digital value VD ′ as the previous subtraction result is overwritten on the digital value VD_0 stored in the storage unit 14 as the digital value VD_0. May be. In S29, the constant value subtracted from the digital value VD_0 is not limited to 1 [LSB].

  Next, the control unit 16 obtains a correction value VDh by subtracting the digital value VDs stored in the storage unit 14 from the digital value VD_0 stored in the storage unit 14, and calculates the correction value VDh as the digital value VDs. Are stored in the storage unit 14 in association with each other or overwritten on the correction value VDh already stored in the storage unit 14 (S31). That is, if the comparator 2 determines that the voltage Vref is greater than the voltage Vc at the control timing, the control unit 16 sets the digital value VD_0 to a constant value until the comparator 2 does not determine that the voltage Vref is greater than the voltage Vc. The result of subtracting the digital value VDs from the addition result is used as the correction value VDh. If the comparator 2 does not determine that the voltage Vref is greater than the voltage Vc at the control timing, the control unit 16 subtracts a constant value from the digital value VD_0 until the comparator 2 determines that the voltage Vref is greater than the voltage Vc. Subsequently, a result obtained by subtracting the digital value VDs from the subtraction result is set as a correction value VDh.

  Next, when the control unit 16 determines that the correction value VDh obtained in S31 is greater than or equal to the threshold value VDth (S32 is Yes), it determines that the A / D conversion unit 13 is out of order (S33). Thereby, it is possible to determine whether or not the A / D converter 13 is out of order.

  Next, the control unit 16 changes the control signal SDC from the low level to the high level (S34), adds the correction value VDh to the digital value VDs to obtain the corrected digital value VDt (S35), and sets the control signal SDC to high. From the level to the low level (S36), the correction process of the digital value VDt output from the A / D conversion unit 3 and the update process of the correction value VDh are terminated.

  Then, the control unit 16 starts the initial process (S21) at the next control timing. It is assumed that the high level period of the control signal SDC is equal to or substantially equal to the time required until the capacitor 6 is sufficiently discharged.

  As described above, according to the A / D conversion device 1 of the present embodiment, the error generated in the A / D conversion unit 13 is obtained using the minimum relationship determination result of the comparator 2, and the error is calculated as the A / D conversion unit 13. Since the correction value is obtained so that it is not included in the output value of +1 [LSB] or -1 [LSB], the error included in the output value of the A / D converter 13 is averaged ± 0.5 [LSB] can be suppressed.

  Further, according to the A / D conversion device 1 of the present embodiment, the correction value VDh can be changed in accordance with the change in the output value of the A / D conversion unit 13, so that an environmental change (for example, a change in ambient temperature) ) Can be suppressed.

  Further, according to the A / D conversion device 1 of the present embodiment, the correction value VDh is changed using the magnitude relationship determination result between the voltage Vref and the voltage Vc by the comparator 2 as it is. Since it is not necessary to convert the value into a value and it is not necessary to add an A / D converter, an error generated in the A / D converter 13 is not included in the output value of the A / D converter 13.

  Therefore, according to the A / D conversion device 1 of the present embodiment, the A / D conversion accuracy can be improved.

DESCRIPTION OF SYMBOLS 1 A / D converter 2 Comparator 3-5 npn bipolar transistor 6, 7 Capacitor 8, 9 Resistor 10 Diode 11 Control circuit 12 Sensor 13 A / D converter 14 Memory | storage part 15 Square wave output part 16 Control part

Claims (2)

An A / D converter that converts the input first analog value into a digital value;
A D / A converter for converting the digital value into a second analog value;
A latch unit that latches the first analog value at each control timing;
A comparator for determining whether a first analog value latched by the latch unit is larger than the second analog value;
A correction value is added to the digital value at each control timing to obtain a corrected digital value, and the first analog value latched by the latch unit by the comparator at the control timing is the second analog value. If it is determined that the value is greater than the value, a constant value is added to the digital value until it is determined that the first analog value latched by the latch unit by the comparator is not greater than the second analog value. Subsequently, a result obtained by subtracting the digital value from the addition result is used as the correction value, and the first analog value latched by the latch unit by the comparator at the control timing is larger than the second analog value. If it is not determined, the first latch latched in the latch unit by the comparator. A control unit that continuously subtracts the constant value from the digital value until it is determined that a log value is greater than the second analog value, and uses the result of subtracting the digital value from the subtraction result as the correction value; ,
An A / D conversion device. The A / D converter according to claim 1,
When the control unit determines that the correction value is equal to or greater than a threshold value, the control unit determines that the A / D conversion unit is faulty.

Images