JP2014011615A - Adaptive equalizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of taps and improve reception performance by suppressing an increase in circuit scale and an increase in operating clock frequency.SOLUTION: A first block-generating section 102 divides an input signal in the time domain into blocks. A second block-generating section 128 divides an error signal into blocks. A third clock-generating section 131 divides a decision feedback signal into blocks. A first FFT section 104 fast-Fourier-transforms the input signal for each block. A fourth FFT section 130 fast-Fourier-transforms the error signal for each block. A fifth FFT section 133 fast-Fourier-transforms the decision feedback signal for each block. A block control section 101 controls so that the block size when the feedback signal is divided into blocks is shorter than the block size when the input signal is divided into blocks, and the block size when the feedback signal is divided into blocks becomes a length according to the number of taps in adaptive equalization processing.

Description

  The present invention relates to an adaptive equalizer that performs adaptive equalization processing on a time domain signal in the frequency domain.

  In the radio propagation path, a multipath wave is generated in addition to the main wave due to a reflector or the like. For this reason, the wireless signal receiving apparatus needs to remove this influence. For example, in North America, South Korea, etc., the Advanced Television Systems Committee (ATSC) system is used as a digital television broadcasting system. The ATSC system employs single carrier modulation. For this reason, unlike other broadcast standards such as an OFDM (Orthogonal Frequency Division Multiplexing) system employing multi-carrier modulation, an ATSC receiver is premised on the application of an adaptive equalizer.

  In single carrier modulation, it is common to perform adaptive equalization processing in the time domain. However, the adaptive equalization process in the time domain requires a convolution operation for the filter process and the coefficient update process, and the circuit scale increases as the number of taps increases.

  Therefore, there is a technique for performing adaptive equalization processing on a signal in the time domain not in the time domain but in the frequency domain (see, for example, Patent Document 1, Patent Document 2, and Non-Patent Document 1). The techniques described in Patent Document 1, Patent Document 2, and Non-Patent Document 1 (hereinafter referred to as “prior art”) perform adaptive equalization processing after converting a time domain signal into a frequency domain signal by fast Fourier transform. Do. Further, in the conventional technique, the frequency domain signal after the adaptive equalization processing is converted into a time domain signal by inverse fast Fourier transform. In such a single-carrier modulation signal receiving apparatus using the conventional technique, it is possible to improve reception performance while suppressing an increase in circuit scale.

Special table 2004-503180 gazette JP-T-2004-530365

John J. Shynk, "Frequency-Domain and Multirate Adaptive Filtering", IEEE SP MAGAZINE, January 1992, p. 14-37

  However, the conventional technique has a problem that the operation clock frequency required for the adaptive equalizer increases when the number of taps required is large or when it is necessary to perform reception processing at high speed. In the prior art, the power consumption of the adaptive equalizer increases due to the increase of the operating clock frequency, and there arises a problem that it becomes troublesome when mounted on an FPGA (Field Programmable Gate Array) or the like. Therefore, it is desirable that an adaptive equalizer that performs adaptive equalization processing for a signal in the time domain in the frequency domain can suppress an increase in circuit scale and an increase in operating clock frequency as much as possible.

  It is an object of the present invention to increase the number of taps and improve reception performance in an adaptive equalizer that performs adaptive equalization processing for a signal in the time domain in the frequency domain while suppressing an increase in circuit scale and an increase in operating clock frequency. It is to provide an adaptive equalizer that can be implemented.

  The adaptive equalizer according to the present invention is configured to block the first input signal in the time domain and the first feedback signal in the time domain, and the first input signal that has been blocked at high speed for each block. First, a Fourier transform is performed to generate a second input signal in the frequency domain, and a first feedback signal in the frequency domain is generated by performing a fast Fourier transform on the block-by-block first feedback signal for each block. A signal conversion unit; an equalization unit that adaptively equalizes the second input signal using the second feedback signal; and the second input signal that is adaptive equalization processed by the equalization unit is inverted at high speed. A second signal conversion unit that generates a time domain output signal by Fourier transform and outputs the output signal as the first feedback signal; and the first feedback signal. A control unit for controlling a block size of the signal in the blocking to be shorter than a block size of the first input signal in the blocking and a length corresponding to the number of taps in the adaptive equalization processing; Are provided.

  ADVANTAGE OF THE INVENTION According to this invention, in the adaptive equalizer which performs an adaptive equalization process with respect to the signal of a time domain in a frequency domain, while suppressing the increase in a circuit scale and the increase in an operation clock frequency, it increases a tap number, and improves receiving performance Can be made.

The block diagram which shows the structure of the adaptive equalizer which concerns on embodiment of this invention The figure which shows the method of blocking in embodiment of this invention The schematic diagram which shows the restriction | limiting in the fast Fourier-transform process in embodiment of this invention Comparison diagram of the number of taps of feedback signal in the embodiment of the present invention with the conventional one

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment)
<Configuration of adaptive equalizer>
The configuration of adaptive equalizer 100 according to the embodiment of the present invention will be described with reference to FIG. The adaptive equalizer 100 includes a block control unit 101, a first block generation unit 102, a block release unit 124, a second block generation unit 128, and a third block, which are related to the block processing described later. And a generation unit 131.

  Furthermore, the adaptive equalizer 100 includes a first zero insertion unit 103, a first fast Fourier transform unit (hereinafter referred to as “FFT unit”) 104, and a third multiplication, which are related to the processing of the input signal. And 113, a third adder 122, a third IFFT unit 123, a deblocking unit 124, a fourth adder 125, and a time domain filter 134.

  Further, the adaptive equalizer 100 includes a complex conjugate unit 105, a first multiplier 106, a first inverse fast Fourier transform unit (hereinafter referred to as “IFFT unit”) 107, which are related to the feedforward processing. , Second multiplier 108, first adder 109, first delay unit 110, second zero insertion unit 111, and second FFT unit 112.

  Further, the adaptive equalizer 100 includes a fourth multiplier 114, a second IFFT unit 115, a fifth multiplier 116, a second adder 117, a second delay, and the like, which are related to feedback processing. Unit 118, third zero insertion unit 119, third FFT unit 120, sixth multiplier 121, determination unit 126, error extraction unit 127, second block generation unit 128, 4 zero insertion unit 129, fourth FFT unit 130, third block generation unit 131, fifth zero insertion unit 132, and fifth FFT unit 133.

  The first block generation unit 102, the second block generation unit 128, and the third block generation unit 131 constitute a blocking unit.

  The first FFT unit 104, the fourth FFT unit 130, and the fifth FFT unit 133 constitute a first signal conversion unit. Further, the third IFFT unit 123 constitutes a second signal conversion unit.

  The third multiplier 113 and the third adder 122 constitute an equalization unit that performs adaptive equalization processing.

  The block control unit 101 controls the operations of the first block generation unit 102, the second block generation unit 128, the third block generation unit 131, and the block release unit 124. The block control unit 101 is configured so that the block size in the block formation in the second block generation unit 128 and the third block generation unit 131 is shorter than the block size in the block formation in the first block generation unit 102. ,Control. In addition, the block control unit 101 controls the block size in the block formation in the second block generation unit 128 and the third block generation unit 131 so as to have a length corresponding to the number of taps in the adaptive equalization processing. . The block control unit 101 performs control so that the block size in the block formation in the second block generation unit 128 and the third block generation unit 131 becomes shorter as the number of taps in the adaptive equalization process increases.

  Specifically, the block control unit 101 counts the number of symbols in the input signal. The block control unit 101 clears the count value every time the count value reaches the threshold value. Then, the block control unit 101 instructs the first block generation unit 102, the second block generation unit 128, and the third block generation unit 131 to block with the counted number of symbols. Here, the threshold value to be compared with the count value is set as a variable value or a fixed value according to the number of taps necessary in the adaptive equalization process. The blocking method will be described later.

  The first block generation unit 102 accumulates the input signal, converts the input signal into a block having a predetermined block size under the control of the block control unit 101, and outputs the block to the first zero insertion unit 103.

  The first zero insertion unit 103 zeros a portion other than the desired signal among the signals input from the first block generation unit 102, and outputs the obtained signal to the first FFT unit 104.

  The first FFT unit 104 performs FFT for each block on the signal input from the first zero insertion unit 103 and outputs the obtained signal to the complex conjugate unit 105 and the third multiplier 113. .

  The complex conjugate unit 105 outputs the complex conjugate of the signal input from the first FFT unit 104.

  The first multiplier 106 multiplies the complex conjugate input from the complex conjugate unit 105 by an error signal input from a fourth FFT unit 130 described later, and the obtained signal is sent to the first IFFT unit 107. Output.

  The first IFFT unit 107 performs IFFT on the signal input from the first multiplier 106 and outputs the obtained signal to the second multiplier 108.

  The second multiplier 108 multiplies the signal input from the first IFFT unit 107 by a predetermined coefficient μ and outputs the obtained signal to the first adder 109.

  The first adder 109 adds the signal input from the second multiplier 108 and the signal input from the first delay unit 110 described later, and the obtained signal is the first delay unit 110. Output to.

  The first delay unit 110 delays the signal input from the first adder 109. The first delay unit 110 outputs the delayed signal to the first adder 109 and the second zero insertion unit 111 as a time domain adaptive equalizer coefficient. That is, the first adder 109 and the first delay unit 110 function as an accumulating unit that accumulates the output of the second multiplier 108.

  The second zero insertion unit 111 zeroes a portion other than the desired tap coefficient in the signal input from the first delay unit 110 and outputs the obtained signal to the second FFT unit 112.

  The second FFT unit 112 performs FFT on the signal input from the second zero insertion unit 111, and outputs the obtained signal to the third multiplier 113.

  The third multiplier 113 multiplies the signal input from the first FFT unit 104 by the signal input from the second FFT unit 112 and outputs the obtained signal to the third adder 122. To do.

  The fourth multiplier 114 multiplies the decision feedback signal input from the fifth FFT unit 133 (to be described later) and the error signal input from the fourth FFT unit 130 (to be described later). Is output to the IFFT unit 115.

  Second IFFT unit 115 performs IFFT on the signal input from fourth multiplier 114 and outputs the obtained signal to fifth multiplier 116.

  The fifth multiplier 116 multiplies the signal input from the second IFFT unit 115 by a predetermined coefficient μ and outputs the obtained signal to the second adder 117.

  The second adder 117 adds the signal input from the fifth multiplier 116 and the signal input from the second delay unit 118 described later, and the obtained signal is added to the second delay unit 118. Output to.

  The second delay unit 118 delays the signal input from the second adder 117, and uses the second adder 117 as a time domain adaptive equalizer coefficient (filter coefficient for decision feedback signal). , And output to the third zero insertion unit 119 and the time domain filter 134. That is, the second adder 117 and the second delay unit 118 function as an accumulating unit that accumulates the output of the fifth multiplier 116.

  The third zero insertion unit 119 sets a portion other than the desired tap coefficient among the signals input from the second delay unit 118 to zero, and outputs the obtained signal to the third FFT unit 120.

  The third FFT unit 120 performs FFT on the signal input from the third zero insertion unit 119 and outputs the obtained signal to the sixth multiplier 121.

  The sixth multiplier 121 multiplies the decision feedback signal input from the fifth FFT unit 133 (to be described later) by the signal input from the third FFT unit 120, and performs a third addition on the obtained signal. Output to the device 122.

  The third adder 122 adds the signal input from the third multiplier 113 and the signal input from the sixth multiplier 121, and outputs the obtained signal to the third IFFT unit 123. To do.

  The third IFFT unit 123 performs an IFFT unit on the signal input from the third adder 122 and outputs the obtained signal to the block release unit 124.

  The deblocking unit 124 extracts the latest signal sequence from the signal input from the third IFFT unit 123 by the block size when the first block generation unit 102 blocks the signal sequence, and sends it to the fourth adder 125. Output.

  The fourth adder 125 adds the signal input from the deblocking unit 124 and the post-interpolation signal input from the time domain filter 134 described later, and sends the obtained signal to the determination unit 126 and the outside. Output. The signal output to the outside corresponds to the output signal of the adaptive equalizer 100. Further, the signal output to the determination unit 126 corresponds to a feedback signal.

  The determination unit 126 outputs a determination feedback signal, which is a determination result for the feedback signal input from the fourth adder 125, to the error extraction unit 127, the third block generation unit 131, and the time domain filter 134. .

  Based on the determination feedback signal input from the determination unit 126, the error extraction unit 127 and the signal point of the signal input from the fourth adder 125 (that is, the output of the adaptive equalizer 100) and the ideal signal point The estimation error is calculated. The error extraction unit 127 outputs an error signal of the obtained estimation error to the second block generation unit 128.

  The second block generation unit 128 converts the error signal input from the error extraction unit 127 into a block having a predetermined block size and outputs the block to the fourth zero insertion unit 129 according to the control of the block control unit 101.

  The fourth zero insertion unit 129 zeroes a portion other than a desired tap coefficient in the block of error signal series input from the second block generation unit 128 and outputs the obtained error signal to the fourth error signal. Is output to the FFT unit 130.

  The fourth FFT unit 130 performs FFT on the error signal input from the fourth zero insertion unit 129 for each block, and uses the obtained error signal for the first multiplier 106 and the fourth multiplier 114. Output to.

  The third block generation unit 131 converts the determination feedback signal input from the determination unit 126 into a block having a predetermined block size and outputs the block to the fifth zero insertion unit 132 according to the control of the block control unit 101.

  The fifth zero insertion unit 132 sets a portion other than the desired data out of the blocked decision feedback signal input from the third block generation unit 131 to zero, and sets the obtained decision feedback signal to the fifth The data is output to the FFT unit 133.

  The fifth FFT unit 133 performs FFT on the decision feedback signal input from the fifth zero insertion unit 132 for each block, and uses the obtained decision feedback signal for the fourth multiplier 114 and the sixth multiplier. To the device 121.

  The time domain filter 134 uses the time domain adaptive equalizer coefficient input from the second delay unit 118 and the determination feedback signal input from the determination unit 126 to make batch processing in units of blocks difficult. Interpolation of filter output in symbol time units is performed. Then, the time domain filter 134 outputs the obtained signal after the interpolation calculation to the fourth adder 125.

  In adaptive equalizer 100 in the present embodiment, first IFFT section 107, second zero insertion section 111, and second FFT section 112 are arranged at the subsequent stage of first multiplier 106. In addition, the adaptive equalizer 100 includes the second IFFT unit 115, the third zero insertion unit 119, and the third FFT unit 120 arranged at the subsequent stage of the fourth multiplier 114. Thereby, adaptive equalizer 100 in the present embodiment can remove the influence caused by performing FFT and IFFT on a discontinuous signal. In other words, these parts have a function to return the multiplication result of the error sequence and the input signal in the frequency domain to the time domain, and to convert the invalid part as a tap coefficient to zero, and then convert it to the frequency domain again. doing. Thereby, adaptive equalizer 100 in the present embodiment can obtain the same calculation result as that of block update in the time domain, and can maintain high reception performance.

  Further, the complex conjugate unit 105 and the part from the determination unit 126 to the first delay unit 110 function as a first coefficient update unit in the present embodiment.

  Furthermore, the parts from the third block generation unit 131 to the fifth FFT unit 133 and the determination unit 126 to the second delay unit 118 function as the second coefficient update unit in the present embodiment.

  By configuring the adaptive equalizer 100 as shown in FIG. 1, it is possible to perform adaptive equalization processing on a time domain signal not in the time domain but in the frequency domain.

<Blocking method>
Blocking of the input signal and the feedback signal in the embodiment of the present invention will be described with reference to FIG.

  The block control unit 101 is configured so that the block size in the block formation in the second block generation unit 128 and the third block generation unit 131 is shorter than the block size in the block formation in the first block generation unit 102. Control. And the block control part 101 is controlling so that it becomes the length according to the tap number in an adaptive equalization process.

  For example, the block control unit 101 performs control so that the ratio between the block size of the input signal and the block size of each of the determination feedback signal that is a feedback signal and the error signal is 2: 1. That is, as shown in FIG. 2, the first block generation unit 102 blocks the input signal into blocks having a block size L under the control of the block control unit 101. In addition, the second block generation unit 128 blocks the error signal, which is a part of the feedback signal, into blocks having a block size L / 2 under the control of the block control unit 101. In addition, the third block generation unit 131 blocks the determination feedback signal, which is a part of the feedback signal, into blocks having a block size L / 2 under the control of the block control unit 101.

  In the present embodiment, the feedback signal is divided into blocks with the above block size, and FFT is performed for each block. Thereby, in this Embodiment, the number of taps can be increased compared with the past, without increasing the number of points in FFT.

  The block control unit 101 is not limited to the block size described above. If the ratio between the block size of each of the decision feedback signal and the error signal as a feedback signal and the block size of the input signal is an integer, the block size can be arbitrarily set. Can be changed. Here, the block size ratio being an integer means that when the block size ratio is p: q, p and q are integers.

  In FIG. 2, only blocking in the Nth block is shown, but blocking is performed in other blocks than the Nth block in the same manner as in the Nth block.

<Reason why the number of taps can be increased>
The reason why the number of taps can be increased in the adaptive equalizer 100 according to the embodiment of the present invention as compared with the prior art will be described with reference to FIGS. In FIG. 4, (a) shows the number of taps of the conventional feedback signal, and (b) shows the number of taps of the feedback signal of the present embodiment.

  When the received signal is a television broadcast signal, the received signal must be processed within real time in order to continuously view the broadcast without interruption. That is, all the operations executed by the adaptive equalizer 100 need to be completed within the block size time.

  Also, for broadcasters, it is usually desirable to widen the broadcast area as much as possible and transmit signals with high output from a small number of broadcast points in order to reduce infrastructure costs. As a result, the delayed wave due to the distant reflector arrives with a delay of several hundred symbols or more, so the number of taps that must be handled by the adaptive equalizer 100 is also several hundred taps or more. In other words, the assumed application system must support a long delay multipath of 40 μsec or more, and requires a tap number of at least 500 taps or more.

  As shown in FIG. 3, the conventional adaptive equalizer performs arithmetic processing for 416 samples in a region # 301 indicated by a parallelogram. At this time, in the conventional adaptive equalizer, an unnecessary calculation result obtained by the calculation in the region # 302 and the region # 303 is generated due to the periodicity of the FFT. In the present embodiment, the third zero insertion unit 119, the fourth zero insertion unit 129, and the fifth zero insertion unit 132 indicate the calculation results obtained by the calculation processing in the region # 302 and the region # 303. The corresponding part is set to zero. Thereby, only the calculation result in the region # 301 can be obtained.

  In general, in an adaptive equalizer using FFT and IFFT, the block size, the number of taps, and the number of FFT points must satisfy the condition “block size + number of taps−1 <number of FFT points”. There is a restriction that it must not be.

  For example, conventionally, when application to ATSC is considered, if the number of FFT points is 1024, arithmetic processing is performed in a state where the block size 416 and the number of taps 609 are limited as shown in FIG. . That is, conventionally, assuming that the number of FFT points is 1024, the block size is set to 416 symbols, which is 1/2 of one segment, in order to correspond to the number of taps 609.

  From the above, in the conventional feedback signal calculation processing, the maximum number of taps that can be handled can be calculated as 1024−416 + 1 = 609 taps as shown in FIG. This corresponds to a delay amount of 55 μsec. Therefore, conventionally, the feedback signal of the block size 416 is processed with the maximum number of taps 609. Specifically, in region # 401, 416 samples of the feedback signal of block size 416 are collectively calculated using FFT. Then, in region # 402, 208 samples of batch auxiliary calculations are performed, and in region # 403 and region # 404, convolution calculations are performed.

  If a tap number of 610 taps or more is required, it is necessary to increase the number of FFT points or reduce the block size. However, when the number of FFT points is increased, the number of arithmetic circuits and memory circuits is increased, which increases the circuit scale. In addition, when the block size is reduced, the permissible time per calculation of each block is reduced, which causes an increase in the relative calculation amount.

  Therefore, in the present embodiment, the calculation cycle is left as it is, the block size of the feedback signal is reduced as compared with the conventional one, and the feedback signal is calculated in a plurality of times each time the input signal is calculated once. At this time, in the calculation of the feedback signal, the ratio of the operation time of the time domain filter 134 is large, and there is a time in which resources necessary for the calculation of the FFT are excessive. For this reason, in the calculation of the feedback signal, even if only the feedback signal is calculated in a plurality of times, the circuit scale is not increased.

  For example, when the number of FFT points is 1024 and the block size of the input signal is 416, the adaptive equalizer 100 sets the block size of each feedback signal to 208, which is half of the input signal. Further, the adaptive equalizer 100 calculates the feedback signal in two steps each time the input signal is calculated once. As a result, the adaptive equalizer 100 can handle up to 1024−416 / 2 + 1 = 817 taps. This corresponds to a delay amount of about 75 μsec.

  As shown in FIG. 4B, the adaptive equalizer 100 performs an arithmetic process on the feedback signal of the block size 208 with the maximum number of taps 817. Specifically, in region # 411, adaptive equalizer 100 collectively calculates 208 samples of the feedback signal of block size 208 corresponding to the first half of block size 416 of the input signal using FFT. Further, in region # 412, adaptive equalizer 100 collectively calculates 208 samples of the feedback signal of block size 208 corresponding to the second half of block size 416 of the input signal using FFT. The calculation in the area # 412 includes a conventional batch auxiliary calculation for 208 samples. The adaptive equalizer 100 performs a convolution operation in the region # 413 and the region # 414. That is, the adaptive equalizer 100 reduces the block size of the feedback signal to half of the conventional size, and performs the calculation using the FFT of the feedback signal that has been performed only once in the conventional region # 401. It is divided into 4 times with 412.

  From the above, in this embodiment, even if the number of FFT points is 1024, the maximum tap number is increased to 817 by halving the feedback signal block size and doubling the number of operations. Can do.

<Effects of the present embodiment>
This embodiment is an adaptive equalizer that performs adaptive equalization processing on a signal in the time domain in the frequency domain, and can increase the number of taps while suppressing an increase in circuit scale and an increase in operating clock frequency, and reception. Performance can be improved.

  Further, in this embodiment, it is possible to cope with an increase in the number of taps by shortening the block size of the feedback signal.

  INDUSTRIAL APPLICABILITY The present invention is useful as an adaptive equalizer that can suppress an increase in circuit scale in an adaptive equalizer that performs adaptive equalization processing on a signal in the time domain in the frequency domain. In particular, the present invention is suitable for an adaptive equalizer of a receiving apparatus that supports multilevel VSB (Vestigial Sideband) modulation, which is employed in ATSC and the like. Further, the present invention is suitable for various digital adaptive equalizers such as a speech echo canceller and a noise canceller that require a large number of taps in addition to an adaptive equalizer for wireless transmission.

DESCRIPTION OF SYMBOLS 100 Adaptive equalizer 101 Block control part 102 1st block production | generation part 103 1st zero insertion part 104 1st FFT part 105 Complex conjugate part 106 1st multiplier 107 1st IFFT part 108 2nd multiplication Unit 109 first adder 110 first delay unit 111 second zero insertion unit 112 second FFT unit 113 third multiplier 114 fourth multiplier 115 second IFFT unit 116 fifth multiplier 117 Second adder 118 Second delay unit 119 Third zero insertion unit 120 Third FFT unit 121 Sixth multiplier 122 Third adder 123 Third IFFT unit 124 Block release unit 125 4th Adder 126 Determination unit 127 Error extraction unit 128 Second block generation unit 129 Fourth zero insertion unit 130 Fourth FFT unit 131 Third block raw Part 132 Fifth zero insertion section 133 fifth FFT unit 134 time domain filter of

Claims (4)

A blocking unit that blocks the first input signal in the time domain and the first feedback signal in the time domain;
The block-formed first input signal is subjected to fast Fourier transform for each block to generate a second input signal in the frequency domain, and the block-formed first feedback signal is subjected to fast Fourier transform for each block. A first signal converter for generating a second feedback signal in the frequency domain;
An equalizer for adaptively equalizing the second input signal using the second feedback signal;
A second signal for generating an output signal in the time domain by performing inverse fast Fourier transform on the second input signal subjected to adaptive equalization processing by the equalization unit, and outputting the output signal as the first feedback signal A conversion unit;
The block size in the blocking of the first feedback signal is shorter than the block size in the blocking of the first input signal and has a length corresponding to the number of taps in the adaptive equalization processing. A control unit to control;
An adaptive equalizer comprising: The controller is
The block size of the first feedback signal is shortened as the number of taps in the adaptive equalization process increases.
The adaptive equalizer according to claim 1. The controller is
A numerical value representing a ratio between the block size of the first feedback signal and the block size of the first input signal is an integer.
The adaptive equalizer according to claim 1. The controller is
The ratio of the block size of the first input signal to the block size of the first feedback signal is 2: 1;
The adaptive equalizer according to claim 1.

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