JP2014011217A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit peeling and scattering of small pieces of a substrate from a dicing sheet.SOLUTION: A semiconductor device manufacturing method comprises: hydrophobizing a rear face of a substrate (step S100); subsequently, applying a dicing sheet to the rear face of the substrate (step S200); and subsequently dicing the substrate by pouring water on the substrate and singulating the substrate into semiconductor chips (step S210). By doing this, water can be inhibited from entering into a boundary between the substrate and the dicing tape in dicing. Accordingly, scattering of small pieces of the substrate can be inhibited in dicing.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and in particular, is a technique applicable to a method for manufacturing a semiconductor device having a dicing process.

  When manufacturing semiconductor chips, processing is performed on a wafer basis. Then, the wafer is divided into a plurality of semiconductor chips by dicing. At this time, small pieces of the substrate that are not commercialized are generated from the peripheral portion of the wafer. When the wafer is diced, a dicing sheet is attached to the back surface of the wafer, but a small piece of the substrate may be peeled off from the dicing sheet and scattered during dicing. The technique described in Patent Document 1 devises the composition of the adhesive layer of the dicing sheet in order to suppress this scattering.

JP 2011-233718A

  Regardless of the type of adhesive layer, there is a demand for a technique that suppresses the small pieces of the substrate from peeling off and scattering from the dicing sheet. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a manufacturing method of a semiconductor device includes a hydrophobizing step of hydrophobizing the back surface of a semiconductor substrate, a pasting step of pasting a dicing sheet on the back surface of the semiconductor substrate, and dicing while applying water to the semiconductor substrate. A dicing process.

  According to the said one embodiment, it can suppress that the small piece of a board | substrate peels off from a dicing sheet.

3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. It is sectional drawing of the processing apparatus used when hydrolyzing the back surface of a board | substrate. It is a top view for demonstrating the process of dicing a board | substrate. It is sectional drawing of a board | substrate and a dicing sheet. It is a figure for demonstrating the reason which can hydrophobize with a dilute hydrofluoric acid solution. It is sectional drawing of the semiconductor chip which concerns on 2nd Embodiment. It is a flowchart which shows an example of the manufacturing method of the semiconductor chip shown in FIG. It is sectional drawing which shows the structure of the semiconductor chip which concerns on 3rd Embodiment. It is a flowchart which shows an example of the manufacturing method of the semiconductor chip shown in FIG. It is a figure which shows the dicing result of an Example. It is sectional drawing which shows the structure of the modification of FIG.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. The manufacturing method of the semiconductor device shown in this figure includes the following steps. First, the back surface of the substrate is hydrophobized (step S100). Next, a dicing sheet is pasted on the back surface of the substrate (step S200). Next, the substrate is diced while applying water to the substrate, and separated into semiconductor chips (step S210). Thereafter, the separated semiconductor chip is picked up from the dicing tape (step S220).

  When the back surface of the substrate is hydrophilized, when the substrate is diced, water may enter the portion of the interface between the substrate and the dicing tape located at the edge of the substrate along the back surface of the substrate. When the substrate is diced, a part of the portion located at the edge of the substrate becomes a small piece. When water enters the interface between the small piece and the dicing tape, the small piece is easily peeled off from the dicing tape. In this case, there is a possibility that small pieces are scattered during dicing.

  In contrast, in the present embodiment, the back surface of the substrate is hydrophobized before the dicing tape is applied to the back surface of the substrate. For this reason, it can suppress that water permeates into the interface of a board | substrate and a dicing tape at the time of dicing. Therefore, it is possible to suppress scattering of small pieces of the substrate during dicing. In order to obtain this effect, it is preferable that processing is not performed on the back surface of the substrate after the back surface of the substrate is hydrophobized and before the dicing tape is applied to the back surface of the substrate. In addition, it is preferable that the period from when the back surface of the substrate is hydrophobized to when the dicing tape is applied to the back surface of the substrate is within 90 days. Details will be described below.

  FIG. 2 is a cross-sectional view of the processing apparatus used when the back surface BSF of the substrate SUB is hydrophobized (step S100 in FIG. 1). This processing apparatus includes a stage STG, a holding unit HLD, a cover CV, a nozzle NZL1, and a nozzle NZL2. The holding unit HLD holds the substrate SUB while being separated from the surface of the stage STG. Specifically, one end of the holding part HLD is attached to the peripheral part of the surface of the stage STG. The other end of the holding unit HLD extends in a direction away from the stage STG, and then bends toward the center side of the stage STG to hold the edge of the substrate SUB. The substrate SUB is a semiconductor wafer such as a silicon wafer.

  A nozzle NZL1 is provided on the surface of the stage STG. The nozzle NZL1 injects a chemical for hydrophobizing the back surface BSF onto the back surface BSF of the substrate SUB. When the substrate SUB is a silicon substrate, this chemical solution is, for example, a diluted hydrofluoric acid solution. The nozzle NZL2 injects pure water onto the surface of the substrate SUB. Thereby, it can suppress that the chemical | medical solution injected to the back surface BSF of the board | substrate SUB influences the surface of the board | substrate SUB.

  Note that the stage STG rotates together with the holding unit HLD and the substrate SUB while the chemical liquid or pure water is sprayed onto the substrate SUB. Thereby, the chemical | medical solution sprayed on the back surface BSF of the board | substrate SUB spreads on the whole surface of the back surface BSF. The pure water sprayed on the surface of the substrate SUB spreads over the entire surface of the substrate SUB. Note that the periphery of the stage STG, the holding unit HLD, and the substrate SUB is surrounded by a cover CV. For this reason, the chemical | medical solution and pure water which were injected by the board | substrate SUB are not scattered around.

  FIG. 3 is a plan view for explaining the step of dicing the substrate SUB (step S210 in FIG. 1). In this step, a dicing sheet DSH is attached to the back surface BSF of the substrate SUB. The planar shape of the dicing sheet DSH is larger than that of the substrate SUB. The edge of the dicing sheet DSH is held by the wafer ring WFR.

  The substrate SUB is diced by the dicing blade DBL along the dicing line DIL. Thereby, the substrate SUB is divided into a plurality of semiconductor chips. A part of the peripheral portion of the substrate SUB is a small piece SCP. During dicing, pure water is supplied from the nozzle NZL3 to the surface of the substrate SUB.

  FIG. 4 is a cross-sectional view of the substrate SUB and the dicing sheet DSH. As described above, the dicing sheet DSH is attached to the back surface BSF of the substrate SUB. The back surface BSF of the substrate SUB is easily oxidized to form a silicon oxide film. In this case, the back surface BSF of the substrate SUB becomes hydrophilic, and the necessity for the above-described hydrophobizing treatment is increased.

  In the present embodiment, the back surface of the substrate SUB is not ground. For this reason, the manufacturing cost of a semiconductor chip becomes low. On the other hand, since the back surface of the substrate SUB remains flat, the adhesion of the dicing sheet DSH to the substrate SUB is poor as compared with the case where the back surface of the substrate SUB is ground. For this reason, the small piece SCP is easily scattered during dicing. In contrast, in the present embodiment, as described above, the back surface of the substrate is hydrophobized before the dicing tape is applied to the back surface of the substrate. For this reason, it can suppress that water permeates into the interface of a board | substrate and a dicing tape at the time of dicing. Therefore, it is possible to suppress scattering of small pieces of the substrate during dicing.

  FIG. 5 is a diagram for explaining the reason why the hydrophobization treatment can be performed with a diluted hydrofluoric acid solution. As shown in FIG. 5A, when the substrate SUB is a silicon substrate, a silicon oxide film is formed on the surface layer of the back surface BSF of the substrate SUB by natural oxidation or thermal oxidation during the manufacturing process. Has dangling bonds on the surface. The presence of dangling bonds attracts water molecules with electrical polarity, so that the back surface BSF becomes hydrophilic.

  On the other hand, as shown in FIG. 5B, when the back surface BSF of the substrate SUB is treated with dilute hydrofluoric acid, the silicon oxide film is removed and the dangling bonds are terminated with hydrogen. For this reason, the electrical polarity of the back surface BSF surface of the substrate SUB is lost, and water molecules are not attracted and become hydrophobic.

  As described above, according to the present embodiment, the back surface of the substrate is hydrophobized before the dicing tape is applied to the back surface of the substrate. For this reason, it can suppress that water permeates into the interface of a board | substrate and a dicing tape at the time of dicing. Therefore, it is possible to suppress scattering of small pieces of the substrate during dicing. This effect is particularly prominent when the time between the hydrophobization of the back surface of the substrate and the application of the dicing tape to the back surface of the substrate is within 90 days. In addition, this effect is particularly remarkable when the back surface of the substrate is not treated after the back surface of the substrate is hydrophobized and before the dicing tape is applied to the back surface of the substrate.

(Second Embodiment)
FIG. 6 is a cross-sectional view of a semiconductor chip according to the second embodiment. In the present embodiment, the transistor TR is formed on the substrate SUB. A multilayer wiring layer MIL is formed on the substrate SUB and the transistor TR. Specifically, the contact CON is embedded in the first-layer interlayer insulating film IL1. The contact CON is formed using, for example, tungsten. An interlayer insulating film IL2 is formed on the interlayer insulating film IL1. A wiring INC is embedded in the interlayer insulating film IL2. The wiring INC is, for example, a copper wiring and is formed using a damascene method. On the interlayer insulating film IL2, a plurality of wiring layers (in the example shown in the drawing, the interlayer insulating film IL3, the interlayer insulating film IL4, and the interlayer insulating film IL5) are formed. In both the interlayer insulating film IL3 and the interlayer insulating film IL4, wirings and vias are embedded using a damascene method (single damascene method or dual damascene method). An electrode pad PD is formed in the uppermost wiring layer (interlayer insulating film IL5 in the example shown in the figure). The electrode pad PD is formed using, for example, aluminum or an aluminum alloy.

  A passivation film PL is formed on the electrode pad PD and the interlayer insulating film IL5. The passivation film PL has, for example, at least one of a silicon oxide film and a silicon nitride film. A polyimide layer PI is formed on the passivation film PL. Both the passivation film PL and the polyimide layer PI have openings on the electrode pads PD. An under bump metal UBM and a nickel layer NL are formed in this order on the electrode pad PD located in the opening and the polyimide layer PI located around the opening. The under bump metal UBM is, for example, Ti, TiW, or Cu, and may be a laminated film thereof. A solder layer SD is formed on the nickel layer NL. The solder layer SD may be both eutectic solder and lead-free solder. The eutectic solder is composed of Sn and Pb. Lead-free solder contains Sn and Cu as main components, and contains both Cu and Ag or one of them. A bump BMP is formed by the under bump metal UBM, the nickel layer NL, and the solder layer SD.

  FIG. 7 is a flowchart showing an example of a manufacturing method of the semiconductor chip shown in FIG. The flowchart shown in this figure shows the process until the wafer is separated into semiconductor chips.

  First, an element isolation film is formed on a wafer substrate SUB. Thereby, the element formation region is separated. The element isolation film is formed using, for example, the STI method, but may be formed using the LOCOS method. Next, a gate insulating film and a gate electrode are formed on the substrate SUB located in the element formation region. The gate insulating film may be a silicon oxide film or a high dielectric constant film (for example, a hafnium silicate film) having a higher dielectric constant than that of the silicon oxide film. When the gate insulating film is a silicon oxide film, the gate electrode is formed of a polysilicon film. When the gate insulating film is a high dielectric constant film, the gate electrode is formed of a laminated film of a metal film (for example, TiN) and a polysilicon film. When the gate electrode is formed of polysilicon, a polysilicon resistor may be formed on the element isolation film in the step of forming the gate electrode.

  Next, source and drain extension regions are formed in the substrate SUB located in the element formation region. Next, sidewalls are formed on the sidewalls of the gate electrode. Next, impurity regions serving as a source and a drain are formed in the substrate SUB located in the element formation region. In this way, the transistor TR is formed on the substrate SUB.

  Next, a multilayer wiring layer MIL is formed on the element isolation film and the transistor TR. An electrode pad PD is formed on the uppermost wiring layer (step S10). Next, a passivation film PL is formed on the multilayer wiring layer MIL. Next, an opening located on the electrode pad PD is formed in the passivation film PL (step S12).

  Next, a polyimide layer PI is formed on the passivation film PL and the electrode pad PD. Next, the polyimide layer PI is exposed and developed. Thereby, an opening located on the electrode pad PD is formed in the polyimide layer PI (step S14).

  Next, an under bump metal UBM is formed on the polyimide layer PI and in the opening of the polyimide layer PI (including on the electrode pad PD) by using, for example, a sputtering method (step S16).

  Next, a resist is patterned on the under bump metal UBM. This resist has an opening in a region where the solder layer SD is to be formed in the under bump metal UBM (step S18). Next, plating (for example, electroplating) for forming the nickel layer NL and plating (for example, electroplating) for forming the solder layer SD are performed in this order using the under bump metal UBM as a seed. Thereby, the nickel layer NL and the solder layer SD are formed on the under bump metal UBM in the resist opening (step S20).

  Thereafter, the resist is peeled off, and a portion of the under bump metal UBM that is not covered with the nickel layer NL and the solder layer SD is removed (step S22). Next, the bump BMP is reflowed (step S24). Then, for example, using plasma, the surface side of the substrate SUB (side on which the bump BMP is formed) is cleaned (step S26). Thereafter, a hydrophobic treatment is performed (step S100). The details of the hydrophobic treatment and the conditions required for the hydrophobic treatment are the same as in the first embodiment.

  Note that the back surface BSF of the substrate SUB is not ground at any timing between step S26 and step S100. Further, before step S100, a film such as a SiN film is not formed on the back surface BSF.

  Then, after the hydrophobic treatment is performed, the substrate in the wafer state is stored in a storage. This board | substrate is conveyed to another factory as needed. Thereafter, the processing shown in steps S200 to S220 in FIG. 1 is performed on the substrates in the storage at a necessary timing. Between step S100 and step S200, the back surface BSF of the substrate SUB is not processed.

  According to this embodiment, the same effect as that of the first embodiment can be obtained.

  In the present embodiment, the process of hydrophobizing the back surface BSF of the substrate SUB (step S100) need not be performed at the timing shown in FIG. For example, as long as processing is not performed on the back surface BSF of the substrate SUB after hydrophobization, it may be performed at any timing after step S10.

(Third embodiment)
FIG. 8 is a cross-sectional view showing a configuration of a semiconductor chip according to the third embodiment. This semiconductor chip has the same configuration as that of the semiconductor chip according to the second embodiment except that it has a pillar PIL instead of the bump BMP.

  Specifically, the pillar PIL is formed on the under bump metal UBM. The pillar PIL is formed of, for example, a copper layer CUL, a nickel layer NL, and a solder layer SD. However, as shown in FIG. 11, it may be formed of a copper layer CUL and a solder layer SD.

  FIG. 9 is a flowchart showing an example of the manufacturing method of the semiconductor chip shown in FIG. 8, and corresponds to FIG. 7 in the second embodiment. The semiconductor chip manufacturing method according to the present embodiment is the same as that shown in FIG. 7 until the step of forming a resist pattern (step S18).

  After forming the resist pattern, plating (for example, electrolytic plating) for forming copper is performed using the under bump metal UBM as a seed (step S19). Thereafter, plating (for example, electrolytic plating) for forming the nickel layer NL and plating (for example, electrolytic plating) for forming the solder layer SD are performed (step S21). When the pillar PIL is formed of the copper layer CUL and the solder layer SD, plating for forming the copper layer CUL is performed, and then plating for forming the solder layer SD is performed.

  The subsequent processing (steps S22 to S26) is the same as that in FIG.

  According to this embodiment, the same effect as that of the second embodiment can be obtained. Also in the present embodiment, the process of hydrophobizing the back surface BSF of the substrate SUB (step S100) does not need to be performed at the timing shown in FIG. For example, as long as processing is not performed on the back surface BSF of the substrate SUB after hydrophobization, it may be performed at any timing after step S10.

(Example)
The silicon wafer was diced using the method shown in FIG. A dilute hydrofluoric acid solution was used for hydrophobization. Further, as Comparative Example 1, a silicon wafer in which the back surface of the substrate was not hydrophobized was diced. Further, as Comparative Example 2, after performing the hydrophobization treatment, the silicon wafer whose back surface was treated with oxygen plasma was diced.

  FIG. 10 shows the result of dicing. In the silicon wafer according to the example, water did not enter the interface between the substrate and the dicing tape. Moreover, even if the silicon wafer according to the embodiment was diced, small pieces of the silicon wafer were not scattered.

  Moreover, the wettability with respect to the water of the back surface of the silicon wafer which concerns on an Example was evaluated. Specifically, a silicon wafer immersed in pure water was lifted horizontally. Thereafter, the silicon wafer was tilted, and the time until the water dropped was measured. In the example, the water fell from the silicon wafer in 1 second. This is presumably because the back surface of the silicon wafer was hydrophobized by the diluted hydrofluoric acid solution.

  On the other hand, in the silicon wafers according to Comparative Examples 1 and 2, water entered the interface between the substrate and the dicing tape. Further, when the silicon wafers according to Comparative Examples 1 and 2 were diced, a plurality of small pieces of the semiconductor wafer were scattered.

  Moreover, the wettability with respect to the water of the back surface of the silicon wafer which concerns on the comparative examples 1 and 2 was evaluated using the method similar to an Example. As a result, water did not fall from the silicon wafer. In Comparative Example 1, it is considered that the back surface of the silicon wafer is still hydrophilic, and in Comparative Example 2, it is considered that the back surface of the silicon wafer is hydrophilicized again by oxygen plasma.

  From the above, it has been shown that when the back surface of the silicon wafer is hydrophobized, small pieces of the silicon wafer are not scattered during dicing. In other words, in the examples, the silicon wafer was hydrophobized by treating with a dilute hydrofluoric acid solution. However, it is shown that the same effect can be obtained by hydrophobizing by another method. It was.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments and examples. However, the present invention is not limited to the above-described embodiments and examples, and does not depart from the spirit of the invention. It goes without saying that various changes can be made.

BMP Bump BSF Back surface CON Contact DBL Dicing blade DIL Dicing line DSH Dicing sheet HLD Holding portion IL1 Interlayer insulating film IL2 Interlayer insulating film IL3 Interlayer insulating film IL4 Interlayer insulating film IL5 Interlayer insulating film INC Wiring MIL Multilayer wiring layer NL Nickel layer NZL1 Nozzle NZL2 Nozzle NZL3 Nozzle PD Electrode pad PI Polyimide layer PIL Pillar PL Passivation film SD Solder layer STG Stage SUB Substrate TR Transistor UBM Under bump metal WFR Wafer ring SCP Small piece

Claims (7)

A hydrophobizing step for hydrophobizing the back surface of the substrate;
A pasting step of pasting a dicing sheet on the back surface of the substrate;
A dicing step of dicing while applying water to the substrate;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 1,
The substrate is a silicon substrate;
The method of manufacturing a semiconductor device, wherein the hydrophobizing step is a step of treating the back surface of the substrate with a diluted hydrofluoric acid solution. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein pure water is supplied to a surface of the substrate in the hydrophobic step. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the back surface of the substrate is not processed between the hydrophobizing step and the attaching step. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the back surface of the substrate is not ground before the attaching step. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, comprising: forming a bump on a surface of the substrate before the hydrophobizing step. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the interval between the hydrophobizing step and the dicing step is within 90 days.

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