JP2014007189A - Semiconductor power module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor power module having physical features such as a withstanding voltage, a low on-resistance, and a high-temperature operation.SOLUTION: A semiconductor power module comprises: a normally-on type high-side power transistor FET 1 connected to a first voltage terminal; a normally-on type low-side power transistor FET 4 connected in series to the high-side power transistor FET 1; and a normally-off type MOS transistor 10 for short circuit prevention provided between a second voltage terminal and the low-side power transistor FET 4. Further, the semiconductor module comprises: control integrated circuits IC1 and IC2 controlling switching of a power transistor; and a metal pattern 3 directly and electrically connecting between a source of the low-side power transistor FET 4 and a drain of the MOS transistor 10.

Description

  The present invention relates to a semiconductor power module, and more particularly to a semiconductor power module using a normally-on device.

  In recent years, in air conditioners, refrigerators, and the like, power consumption has been improved by controlling the number of rotations of a motor according to a control load by inverter control. In the inverter circuit, an intelligent power module (hereinafter referred to as IPM) is used as a drive element, which is a combination of a plurality of power semiconductor elements and a control IC (one or more) that drives the power semiconductor elements. It has come to be. In the conventional IPM, an IGBT (Insulated Gate Bipolar Transistor) is mainly used as a normally-off type power semiconductor element, and a control IC for controlling the IGBT is formed on a separate substrate.

  FIG. 3 is a plan view of a circuit board in a conventional IPM described in Patent Document 1 (Japanese Patent Laid-Open No. 2000-133768). FIG. 4 is a circuit diagram of the semiconductor power module described in Patent Document 1.

  3 and 4, IGBT1 to IGBT6 are provided as power semiconductor elements 103, and diode elements D1 to D6 are connected in antiparallel to these.

  A control lead 107 is drawn from one side of the control circuit unit 102, and a control IC 105 is mounted on the control circuit unit 102. A main circuit portion 101 is provided on the side opposite to the control lead 107 through a separation groove S. A power lead 106 is provided on the opposite side of the main circuit unit 101 from the control circuit unit 102.

  The high-side IGBT 1 to IGBT 3 are arranged in parallel with the diode elements D 1 to D 3 connected in antiparallel, and are placed on the main circuit unit 101 connected to the terminal P. The low-side IGBT4 to IGBT6 are paired with each of the diode elements D4 to D6 connected in antiparallel, and are placed on different main circuit boards.

JP 2000-133768 A

  However, the semiconductor power module described in Patent Document 1 is a Si (silicon) power device and has a problem that it does not have physical characteristics such as withstand voltage, low on-resistance, and high-temperature operation.

  Therefore, an object of the present invention is to provide a semiconductor power module having physical characteristics of withstand voltage, low on-resistance, and high-temperature operation.

In order to solve the above problems, a semiconductor power module of the present invention is connected to a first voltage terminal, a normally-on type high-side power semiconductor element, and a high-side power semiconductor element connected in series. A normally-on type low-side power semiconductor element, a normally-off type MOS transistor for preventing a short circuit provided between the second voltage terminal and the low-side power semiconductor element, and a high-side and low-side power semiconductor A control IC for controlling switching of the element, and a first metal pattern for directly electrically connecting the source of the low-side power semiconductor element and the drain of the MOS transistor are provided.
Preferably, the low side semiconductor element is a horizontal device, and the MOS transistor is a vertical device.

  Preferably, a high-side diode connected in reverse parallel to the high-side power semiconductor element and a low-side diode connected in reverse parallel to the low-side power semiconductor element are provided.

  Preferably, the first metal pattern on which the low-side power semiconductor element is placed and the fourth metal pattern on which the low-side diode is placed are separated, and the first metal pattern on which the high-side power semiconductor element is placed. The second metal pattern is separated from the third metal pattern on which the high-side diode is placed.

  Preferably, the control IC is mounted on a control board, and the control board is a flexible printed board.

  Preferably, the high-side and low-side power semiconductor elements are placed on a power substrate, and the power substrate is a DCB (Direct Copper Bonding) substrate.

Preferably, the power semiconductor element is a normally-on type GaN-based device.
The semiconductor power module of the present invention includes a normally-on type first to third high-side power semiconductor element connected to a first voltage terminal, first to third high-side power semiconductor elements, and Short circuit prevention provided between the normally-on type first to third low-side power semiconductor elements connected in series, the second voltage terminal, and the first to third low-side power semiconductor elements. Normally-off type MOS transistor, a high-side control integrated circuit for controlling the first to third high-side switching, and a low-side control integrated circuit for controlling the first to third low-side switching And a first metal pattern for directly electrically connecting the sources of the first to third low-side power semiconductor elements and the drain of the MOS transistor.

  The semiconductor power module of the present invention has physical characteristics of withstand voltage, low on-resistance, and high-temperature operation.

It is a top view of the circuit board in the semiconductor power module of the embodiment of the present invention. It is a circuit diagram in the semiconductor power module of the embodiment of the present invention. 10 is a plan view of a circuit board in a conventional IPM described in Patent Document 1. FIG. 2 is a circuit diagram of a semiconductor power module described in Patent Document 1. FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In recent years, wide band gap semiconductors that are expected to have performance exceeding that of power elements made of silicon semiconductors have attracted attention. Wide band gap semiconductors have physical characteristics such as high breakdown voltage, low on-resistance, and high temperature operation. Among such wide bandgap semiconductors, GaN-based FETs (Field Effect Transistors) are able to withstand high withstand voltage and high-temperature operation, and enable realization of low on-resistance by heterojunction.

  A GaN-based HFET (Hetero Field Effect Transistor) using a heterojunction of AlGaN / GaN (aluminum gallium nitride / gallium nitride) can easily generate a two-dimensional electron gas due to spontaneous polarization and piezo effect at the heterojunction interface. Coupled with mobility, a high-speed and high-current element power device can be obtained.

  In addition, in a HFET using a two-dimensional electron gas, a normally-on device can be manufactured relatively easily and at a low cost, whereas a normally-off device has a high cost and a threshold voltage of only about 2V. Absent. An object of the present application is to provide a low-cost and highly reliable module in a power module using a normally-on device.

  FIG. 1 is a plan view of a circuit board in a semiconductor power module according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the semiconductor power module according to the embodiment of the present invention.

  Referring to FIGS. 1 and 2, a semiconductor power module 100 includes a DCB substrate (Direct Copper Bonding: ceramic substrate) 1 and a control substrate 2.

  As a power substrate, the DCB substrate 1 has characteristics such as low thermal resistance, high withstand voltage, and excellent heat dissipation. Circuit patterns are formed on the surface of the DCB substrate 1 with metal patterns 3a to 3h having copper foil as a representative material. Here, the metal pattern 3d is the first metal pattern, the metal pattern 3a / 3b / 3c is the second metal pattern, the metal pattern 3e is the third metal pattern, and the metal pattern 3f / 3g / 3h is the fourth metal pattern. Also defined. On the metal pattern on the DCB substrate 1, power transistors FET1 to FET6, diodes D1 to D6, and a short-circuit preventing MOS transistor 10 are provided.

  The control substrate 2 is provided with a high-side control integrated circuit IC1 and a low-side control integrated circuit IC2. The control board 2 is a flexible printed board. When the current capacity of the semiconductor power module is lined up, it is necessary to change the gate drive current with the change of the power semiconductor device. Since the control board 2 is composed of a flexible printed board, the gate drive circuit and the circuit constants can be easily changed without changing the high-side control integrated circuit IC1 and the low-side control integrated circuit IC2.

  The control lead 4 and the power lead 5 are connected to the outside of the semiconductor power module.

  The power transistors FET1 to FET6 are GaN-based HFETs using heterojunctions and are laterally normally on devices in which current flows in the lateral direction.

  The diodes D1 to D6 are fast recovery diode elements connected in antiparallel to the power transistors FET1 to FET6. Here, the diodes D1 to D3 are described as high-side diodes, and the diodes D4 to D6 are described as low-side diodes. The power transistors FET1 to FET3 will be described as high-side power semiconductor elements, and the power transistors FET4 to FET6 will be described as low-side power semiconductor elements.

  The short-circuit prevention MOS transistor 10 is a normally-off type device for arm short-circuit prevention, and is a vertical MOS transistor in which current flows in the vertical direction (perpendicular to the substrate).

  A power transistor FET1, a power transistor FET4, and a MOS transistor 10 are connected in series between an input voltage terminal P and an input voltage terminal N (for example, a ground terminal). Between the input voltage terminal P and the input voltage terminal N, the power transistor FET2, the power transistor FET5, and the MOS transistor 10 are connected in series. Between the input voltage terminal P and the input voltage terminal N, the power transistor FET3, the power transistor FET6, and the MOS transistor 10 are connected in series.

  In order to connect the power transistor FET1 and the diode D1 in antiparallel, the drain of the power transistor FET1 and the cathode of the diode D1 are connected, and the source of the power transistor FET1 and the anode of the diode D1 are connected. The drain of the power transistor FET 1 is connected to the input voltage terminal P of the power lead 5. The source of the power transistor FET 1 is connected to the output terminal U of the power lead 5.

  In order to connect the power transistor FET2 and the diode D2 in antiparallel, the drain of the power transistor FET2 and the cathode of the diode D2 are connected, and the source of the power transistor FET2 and the anode of the diode D2 are connected. The drain of the power transistor FET 2 is connected to the input voltage terminal P of the power lead 5. The source of the power transistor FET 2 is connected to the output terminal V of the power lead 5.

  In order to connect the power transistor FET3 and the diode D3 in antiparallel, the drain of the power transistor FET3 and the cathode of the diode D3 are connected, and the source of the power transistor FET3 and the anode of the diode D3 are connected. The drain of the power transistor FET 3 is connected to the input voltage terminal P of the power lead 5. The source of the power transistor FET 3 is connected to the output terminal W of the power lead 5.

  In order to connect the power transistor FET4 and the diode D4 in antiparallel, the drain of the power transistor FET4 and the cathode of the diode D4 are connected, and the source of the power transistor FET4 and the anode of the diode D4 are connected. The source of the power transistor FET4 is directly connected to the drain of the short-circuit preventing MOS transistor 10. The drain of the power transistor FET 4 is connected to the output terminal U of the power lead 5.

  In order to connect the power transistor FET5 and the diode D5 in antiparallel, the drain of the power transistor FET5 and the cathode of the diode D5 are connected, and the source of the power transistor FET5 and the anode of the diode D5 are connected. The source of the power transistor FET5 is directly connected to the drain of the short-circuit preventing MOS transistor 10. The drain of the power transistor FET 5 is connected to the output terminal V of the power lead 5.

  In order to connect the power transistor FET6 and the diode D65 in antiparallel, the drain of the power transistor FET6 and the cathode of the diode D6 are connected, and the source of the power transistor FET6 and the anode of the diode D6 are connected. The source of the power transistor FET 6 is directly connected to the drain of the short-circuit preventing MOS transistor 10. The drain of the power transistor FET 6 is connected to the output terminal W of the power lead 5.

  As shown in FIG. 1, the power transistors FET1 to FET6 are arranged in a line, and the diodes D1 to D6 are also arranged in a line almost in parallel with the power transistors.

  The power transistor FET1 is placed on the metal pattern 3a whose representative material is copper foil, and the diode D1 is placed on the metal pattern 3e. The metal pattern 3a and the metal pattern 3e are connected via a bonding wire without being in direct contact. The power transistor FET2 is placed on the metal pattern 3b, and the diode D2 is placed on the metal pattern 3e. The metal pattern 3b and the metal pattern 3e are connected via a bonding wire without being in direct contact. The power transistor FET3 is placed on the metal pattern 3c, and the diode D3 is placed on the metal pattern 3e. The metal pattern 3c and the metal pattern 3e are connected via a bonding wire without being in direct contact. The power transistor FET4 is placed on the metal pattern 3d, and the diode D4 is placed on the metal pattern 3f. The metal pattern 3d and the metal pattern 3f are connected via a bonding wire without being in direct contact. The power transistor FET5 is placed on the metal pattern 3d, and the diode D5 is placed on the metal pattern 3g. The metal pattern 3d and the metal pattern 3g are connected via a bonding wire without being in direct contact. The power transistor FET6 is placed on the metal pattern 3d, and the diode D6 is placed on the metal pattern 3h. The metal pattern 3d and the metal pattern 3h are connected via a bonding wire without being in direct contact.

  By doing so, the metal pattern on which each of the power transistors FET1 to FET6 is placed can be used as the source potential of the power transistors FET1 to FET6, so that the collapse phenomenon in the power transistor FET can be suppressed.

  Since the diodes D1 to D6 are provided on an N-type Si semiconductor substrate whose cathode side can be a metal pattern, the resistance can be reduced. The high-side diodes D1 to D3 are placed on a common metal pattern 3e.

  Since the low-side power transistors FET4 to FET6 are horizontal devices, the substrate potential can be set as the source potential, so that they are placed on the common metal pattern 3d. On the common metal pattern 3d, the drain terminal of the short-circuit preventing MOS transistor 10 which is a vertical device is connected. As the Si-type vertical MOS, an element using an N-type Si substrate is generally used, and in this case, the drain side serves as a back electrode. The N-type substrate has a lower resistance than the P-type substrate, and is preferable because the loss is reduced for the semiconductor power module.

  The drain electrode of the short-circuit preventing MOS transistor 10 and the source terminals of the power transistors FET4 to FET6 are directly placed on the common metal pattern 3d (first metal pattern), thereby short-circuiting the sources of the power transistors FET4 to FET6. The parasitic inductance between the drain of the prevention MOS transistor 10 can be minimized. That is, the potential fluctuation due to the parasitic inductance during this period can be suppressed. As a result, it is possible to prevent malfunctions in the low-side power transistors FET4 to FET6.

  In particular, in the semiconductor power module according to the present embodiment, when the short-circuit preventing MOS transistor 10 is turned off, the source potentials of the power transistors FET4 to FET6 rise, and as a result, the gate potentials of the power transistors FET4 to FET6 become the source potential. Therefore, if the malfunction is caused by the parasitic inductance, the power transistors FET4 to FET6 or the MOS transistor 10 for short-circuit prevention may be broken. . Therefore, reducing the parasitic inductor here is very useful.

  The high-side control integrated circuit IC1 is connected to the gates and sources of the high-side power transistors FET1 to FET3.

  The high-side control integrated circuit IC 1 receives a control signal from the outside via the control lead 4. Specifically, a high-side U-phase control signal, a V-phase control signal, and a W-phase control signal are input to the high-side control integrated circuit IC1 through leads UP, VP, and WP.

  The high-side control integrated circuit IC1 is connected to the gates of the high-side power transistors FET1 to FET3 via the gate resistors R1 to R3, and controls the high-side power transistors FET1 to FET3.

  The high-side control integrated circuit IC1 is connected to the source of the power transistor FET1 so that the source potential of the power transistor FET1 can be sensed, and a U-phase high-side power supply boot capacitor C1 is connected to the connection line.

  The high-side control integrated circuit IC1 is connected to the source of the power transistor FET2 so that the source potential of the power transistor FET2 can be sensed, and a V-phase high-side power supply boot capacitor C2 is connected to the connection line.

  The high-side control integrated circuit IC1 is connected to the source of the power transistor FET3 so that the source potential of the power transistor FET3 can be sensed, and a W-phase high-side power supply boot capacitor C3 is connected to the connection line.

  The low-side control integrated circuit IC2 is connected to the gates and sources of the low-side power transistors FET4 to FET6 and the short-circuit prevention MOS transistor 10.

  The low-side control integrated circuit IC 2 receives a control signal from the outside via the control lead 4. Specifically, a low-side U-phase control signal, a V-phase control signal, and a W-phase control signal are input to the low-side control integrated circuit IC2 through leads UN, VN, and WN.

  The low-side control integrated circuit IC2 is connected to the gates of the low-side power transistors FET4 to FET6 via the gate resistors R4 to R6, and controls the low-side power transistors FET4 to FET6.

  The low-side control integrated circuit IC2 controls the short-circuit prevention MOS transistor 10 by being connected to the gate and the source of the short-circuit prevention MOS transistor 10.

  When a problem occurs in the low-side control integrated circuit IC2, and no voltage is applied from the low-side control integrated circuit IC2 to the gate terminals of the power transistors FET4 to FET6, the high-side power transistors FET1 to FET3 and the low-side power transistor Since FET4 to FET6 are normally-on devices, they are turned on and a large short-circuit current flows. In order to prevent this, a short-circuit prevention MOS transistor 10 is provided. That is, when the shortage of the operation voltage of the low-side control integrated circuit IC2 is detected and insufficient, the short-circuit prevention MOS transistor 10 which is a normally-off device is turned off, and an arm short circuit is avoided.

  Under the control of the control integrated circuits IC1 and IC2, the power transistors FET1 to FEE6 turn on / off the direct current input from the input voltage terminals P and N, and output from the output terminals U, V, and W to a three-phase motor (not shown). Supply AC output of any frequency.

  As described above, in the semiconductor power module of the present embodiment, a low-resistance and inexpensive diode or MOS can be used, and a low-loss module can be obtained.

  In the present embodiment, a configuration having a three-phase power module has been described. However, a configuration of a single-phase power module may be used.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  D1-D6 Diode, FET1-FET6 Power transistor, 10 MOS transistor, 1 DCB board, 2 Flexible printed board, 3a-3h Metal pattern, 4 Control lead, 5 Power lead, IC1, IC2 Control integrated circuit, P, N Input voltage terminal, 100 semiconductor power module.

Claims (8)

A normally-on high-side power semiconductor element connected to the first voltage terminal;
A normally-on low-side power semiconductor element connected in series with the high-side power semiconductor element;
A normally-off type MOS transistor for preventing a short circuit provided between a second voltage terminal and the low-side power semiconductor element;
A control integrated circuit for controlling the switching of the high-side and low-side power semiconductor elements;
A semiconductor power module comprising: a first metal pattern for directly electrically connecting a source of the low side power semiconductor element and a drain of the MOS transistor.   The semiconductor power module according to claim 1, wherein the low-side power semiconductor element is a lateral device, and the MOS transistor is a vertical device. A high-side diode connected in reverse parallel to the high-side power semiconductor element;
The semiconductor power module according to claim 1, further comprising a low-side diode connected in reverse parallel to the low-side power semiconductor element. The first metal pattern on which the low-side power semiconductor element is placed and the fourth metal pattern on which the low-side diode is placed are separated,
4. The semiconductor power module according to claim 3, wherein a second metal pattern on which the high-side power semiconductor element is placed and a third metal pattern on which the high-side diode is placed are separated. The control integrated circuit is placed on a control substrate,
The semiconductor power module according to claim 1, wherein the control board is a flexible printed board. The high-side and low-side power semiconductor elements are placed on a power substrate,
The semiconductor power module according to claim 1, wherein the power substrate is a DCB (Direct Copper Bonding) substrate.   The semiconductor power module according to claim 1, wherein the power semiconductor element is a normally-on GaN-based device. A normally-on type first to third high-side power semiconductor element connected to the first voltage terminal;
Normally-on type first to third low-side power semiconductor elements connected in series with the first to third high-side power semiconductor elements, respectively;
A normally-off type MOS transistor for preventing a short circuit provided between a second voltage terminal and the first to third low-side power semiconductor elements;
A high-side control integrated circuit that controls switching of the first to third high-sides;
A low-side control integrated circuit that controls switching of the first to third low-side sides;
A semiconductor power module comprising: a first metal pattern for directly electrically connecting a source of the first to third low-side power semiconductor elements and a drain of the MOS transistor.

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