JP2014003393A - Preamble generating method and preamble generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a preamble generating method capable of reducing the power consumed for preamble generation.SOLUTION: The preamble generating method using plural kinds of code sequences includes the steps of: selecting plural pieces of partial information of previously generated code sequences after rate conversion for each combination pattern of code sequences neighboring to each of the code sequences with respect to each code sequence before rate conversion; and generating a code sequence after rate conversion by using the selected plural pieces of partial information.

Description

  The present disclosure relates to a preamble generation method and a preamble generation apparatus that generate a preamble using a complementary sequence (for example, a Golay sequence) in a communication system that requires rate conversion.

  In recent years, the demand for high data rates for wireless communications has increased significantly. For example, the use of high data rates for wireless personal area networks (WPAN). Also, the use of wireless streaming for uncompressed high definition (HD) video and wireless synch-and-go with extremely high download rates has received much attention. In Patent Document 1, multi-gigabit wireless communication is proposed using a 60 GHz band (millimeter wave band).

  Here, the millimeter wave communication standard normally defines two modes of single carrier (SC) and multicarrier (for example, OFDM) in the physical layer (PHY). The OFDM mode, which is a multi-carrier mode, is used to achieve a higher data rate with higher reliability. In the millimeter wave communication standard, it is proposed to use the same preamble format for both SC and OFDM modes.

US Patent Application Publication No. 2010/0111229

  The present inventors studied a preamble generation method and a preamble generation apparatus that generate a preamble using a complementary sequence (for example, a Golay sequence). However, even if the conventional preamble generation method and preamble generation apparatus are used, it has been difficult to obtain a preamble that sufficiently corresponds to a system that requires rate conversion.

  Accordingly, the present disclosure provides a preamble generation method and a preamble generation apparatus that can obtain a preamble that sufficiently corresponds to a system that requires rate conversion in order to solve the above-described problem.

  The present disclosure is a method for generating a preamble using a plurality of types of code sequences, and is generated in advance for each code sequence before rate conversion for each combination pattern of code sequences adjacent to each code sequence. There is provided a preamble generation method including a step of selecting a plurality of pieces of partial information of a code sequence after rate conversion and a step of generating the code sequence after rate conversion using the selected pieces of partial information.

Further, the present disclosure is a preamble generation device that generates a preamble using a plurality of types of code sequences, and for each code sequence before rate conversion, for each combination pattern of code sequences adjacent to the code sequences. A memory for storing a plurality of pieces of partial information of a code sequence after rate conversion generated in advance, and a controller for controlling the timing of outputting the partial information from the memory according to each code sequence before the rate conversion;
A preamble generation device is provided.

  According to the preamble generation method and preamble generation apparatus according to the present disclosure, it is possible to reduce power consumed in preamble generation.

Schematic which shows an example of the frame structure of the preamble for each mode of SC and OFDM in the physical layer (PHY) of a millimeter wave communication system The block diagram which shows the internal structure of the preamble production | generation apparatus by 1st Embodiment. Schematic diagram showing a method of dividing each modified Golay series into three parts and storing necessary information in a memory Schematic showing an example of a method for generating a modified Golay sequence from information stored in a memory Flowchart illustrating a method for generating in advance information necessary for generating a preamble after rate conversion A graph for comparing the accuracy of the preamble generation method according to Patent Document 1 with the accuracy of the preamble generation method according to the present disclosure Schematic diagram showing a method of dividing each modified Golay series into two parts and storing necessary partial information in a memory without considering rear part information

  Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

  It will be understood that some or all of the drawings are schematic diagrams for illustration and do not necessarily depict the actual relative sizes of the elements shown. The drawings are provided to illustrate one or more embodiments of the disclosure with an explicit understanding, and are not used to limit the scope or meaning of the claims.

<Background to this disclosure>
In the millimeter wave communication standard, the same preamble format is used for both the SC and OFDM modes. Therefore, in order to use the OFDM mode, a rate for adjusting the sampling rate between the SC mode and the OFDM mode. Conversion processing is required.

  In “Method and apparatus of generating packet preamble” described in Patent Document 1, a method for transmitting a packet preamble for each mode of SC and OFDM in the physical layer (PHY) Has been proposed. In this method, three sequences are used to detect the signal, evaluate the channel, and select the transmitter modulation scheme.

  The first sequence, the second sequence, and the third sequence are generated from a pair of Golay sequences of Ga and Gb stored in the memory. Each sequence is then processed by digital processing including π / 2 shift BPSK modulation, pulse shaping filter and rate conversion.

  However, these processes in Patent Document 1 are executed every time a preamble is generated. Therefore, the amount of calculation by this method is large and consumes a lot of power.

  On the other hand, efforts have been made to reduce the power consumption of wireless communication terminals. However, it is desirable that the amount of power consumed by the wireless communication terminal is not sacrificed due to the high data rate requirement.

<Outline of this disclosure>
Hereinafter, definitions of terms used in the present specification will be shown.

  Preamble: Used to synchronize transmission timing between two or more devices. Part of a signal used in communication.

  Floating point arithmetic: Refers to a number of operations that can cover a wide range of values because the decimal point is not used as a fixed point representation.

  Fixed-point arithmetic: Refers to arithmetic on numbers where the number has a fixed number of digits before and after the radix point.

  The present disclosure shows a preamble generation method and preamble generation apparatus that require rate conversion. This method and apparatus, as an embodiment, is advantageous for a communication system using a millimeter wave band operable in a single layer (SC) mode or a multicarrier mode (eg, OFDM mode) in the physical layer (PHY). It is.

  However, the present disclosure is not limited to communication systems using millimeter wave bands, as applications to other bands can be obtained from embodiments similar to the present disclosure.

  In the preamble generation method of the present disclosure, preamble samples that are stored in advance in the memory and rate-converted by floating-point arithmetic are used. An advantage of using the preamble samples stored in the memory is that operations for π / 2 shift BPSK modulation and rate conversion can be omitted. Therefore, the power consumed by the calculation can be reduced.

  In addition, preamble samples that have been rate-converted using floating-point arithmetic have higher accuracy than preamble samples that have been rate-converted using fixed-point arithmetic.

  In the preamble generation method of the present disclosure, a memory is designed in consideration of the relationship between three consecutive complementary sequences (for example, Golay sequences) in order to reduce the memory capacity required to generate the preamble.

  The preamble has a short training field (STF) and a channel estimation field (CEF). Each field is configured using a plurality of Golay sequences (Ga and Gb).

  The preamble generation method includes reconstructing a preamble by using a modified Golay sequence obtained from a memory. Each modified Golay sequence is divided into three parts, that is, front part information, intermediate part information, and rear part information.

  The front part information and the rear part information are preamble samples that are determined by convolution filtering with Golay sequences that are adjacent to each other in time series within a series of sequences such as STF and CEF, for example. In other words, even the front part information of Ga has different contents depending on the combination of (Ga, Ga) and (Gb, Ga). The same applies to the rear part information.

  The intermediate part information is a part that does not depend on the Golay series adjacent in time. That is, the Golay series: Ga and the Golay series: Gb are fixed values.

  Therefore, the length M of the front part information and the length N of the back part information depend on truncation and the number of taps K of the interpolation filter, respectively.

  Note that the rate conversion process may include truncation of the preamble samples when the length of the interpolation filter output is increased by K-1.

  In the preamble generation method, the memory capacity can be further reduced by removing an area for some front part information or rear part information from the memory.

  FIG. 1 is a schematic diagram showing an example of a frame structure of a preamble for each mode of SC and OFDM in a physical layer (PHY) of a communication system using a millimeter wave band. This embodiment is applicable not only to the millimeter wave band but also to a system for rate conversion.

In FIG. 1, the preamble is a Golay sequence having Ga ₁₂₈ and Gb ₁₂₈ . The length of the Golay sequence in this embodiment is 128. The preamble 100 shown in FIG. 1 has a short training field (STF) 101 and a channel estimation field (CEF) 102). The STF 101 has 16 Golay series “Ga ₁₂₈ ” and 1 Golay series “−Ga ₁₂₈ ”. The CEF 102 has 9 Golay sequences. The nine Golay sequences can be divided into two subgroups, Gv512 103 and Gu512 104, and one -Gb ₁₂₈ .

The minus sign “-” before a binary sequence (eg, Ga ₁₂₈ or Gb ₁₂₈ ) in this disclosure is used to represent the inversion of the binary value of that binary sequence. For example, the binary number “1” is inverted to the binary number “0” by the minus sign “−”.

  In order to construct an efficient preamble, it is desirable that the preambles for SC and OFDM modes have a similar format or structure. However, since the transmission rate in the SC mode and the transmission rate in the OFDM mode are different, it is necessary to perform rate conversion in the physical layer (PHY) in the OFDM mode. As a result of this rate conversion processing, the preamble rate in the OFDM mode is set to, for example, 1.5 times the preamble rate in the SC mode.

(First embodiment)
FIG. 2 is a block diagram illustrating an internal configuration of the preamble generation apparatus according to the first embodiment. In FIG. 2, the preamble generation apparatus includes a memory 101, an address controller 103, a sign inversion unit 105, and a DAC (Digital-to-Analog Converter) 107.

The memory 101 stores information that is the basis of the preamble after rate conversion, obtained in advance by calculation. FIG. 2 shows an example in which each information of “M ₁ , M ₂ ,..., M _N ” is stored in the memory 101. Each piece of information “M ₁ , M ₂ ,..., M _N ” is determined by calculation according to the method of the present disclosure described later. “M ₁ , M ₂ ,..., M _N ” are all separate information.

  The address controller 103 reads, from the memory 101, information necessary to configure the preamble 111 after rate conversion based on timing information input from the outside.

  The sign inversion unit 105 inverts the sign of information read from the memory 101 based on timing information input from the outside.

  The DAC 107 converts the rate-converted preamble 111 that is digital data into an analog baseband signal 113.

  Hereinafter, the relationship between preambles before and after rate conversion and the partial information stored in the memory 101 will be described.

  In the preamble frame configuration example shown in FIG. 1, the length of the preamble before rate conversion can be calculated as 3328 (= 26 × 128) samples. When the rate conversion ratio is 1.5, the length of the preamble after rate conversion is 4992 (= 3328 × 1.5) samples.

  In the present disclosure, a rate-converted preamble having 4992 preamble samples is generated by a modified Golay sequence reconstructed using partial information read from the memory 101.

  The modified Golay sequence is associated with the preamble frame structure before rate conversion. The length of each modified Golay sequence is 192 (= 128 × 1.5) samples.

Each modified Golay sequence can be divided into three parts: front part information, intermediate part information, and rear part information. FIG. 3 is a schematic diagram illustrating a method of dividing each modified Golay sequence into three parts and storing necessary partial information in a memory. Sy shown in FIG. 3 is a modified Golay sequence in which 128 levels of Gy ₁₂₈ are converted to 192 levels. Note that the Golay sequence Gx ₁₂₈ , Gy ₁₂₈ , and Gz ₁₂₈ before rate conversion is one of binary sequences represented by Ga ₁₂₈ , Gb ₁₂₈ , -Ga _128, or -Gb ₁₂₈ .

For this reason, in order to construct the modified Golay sequence Sy, it is necessary to use the context of 128 levels of Gx ₁₂₈ , Gy ₁₂₈ and Gz ₁₂₈ . In FIG. 3, Gx ₁₂₈ is a 128-level Golay sequence preceding Gy ₁₂₈ , and Gz ₁₂₈ is a 128-level Golay sequence following Gy ₁₂₈ .

In FIG. 3, the front part information, the intermediate part information, and the rear part information of the modified Golay series Sy are stored in the memory 101 as “f_Gx_Gy”, “m_Gy”, and “b_Gy_Gz”, respectively. The front partial information “f_Gx_Gy” is associated with convolution filtering by an interpolation filter between two Golay sequences adjacent in time, that is, the first two Golay sequences Gx ₁₂₈ and Gy ₁₂₈ .

The intermediate partial information “m_Gy” is independently associated with convolution filtering by an interpolation filter with the Golay sequence Gy ₁₂₈ independently of Gx ₁₂₈ or Gz ₁₂₈ .

The rear partial information “b_Gy_Gz” is associated with convolution filtering by an interpolation filter between two Golay sequences adjacent in time, that is, the last two Golay sequences Gy ₁₂₈ and Gz ₁₂₈ . Note that the length of each piece of partial information constituting the modified Golay sequence depends on the number of taps of the interpolation filter and the implementation of the rate conversion process.

FIG. 4 is a schematic diagram illustrating an example of a method for generating a modified Golay sequence from partial information stored in a memory. In the example illustrated in FIG. 4, 128-level −Ga ₁₂₈ 502 is a Golay sequence in which the sign of Ga ₁₂₈ 501 is inverted. However, the modified Golay sequence S ₂₅ does not match the Golay sequence in which the sign of the modified Golay sequence S ₁₉ is inverted.

  This is because the modified Golay sequence is a 192-level Golay sequence, and is configured by the correlation between the Golay sequence corresponding to the obtained corrected Golay sequence and the Golay sequence adjacent thereto.

That is, since the modified Golay sequence S ₁₉ is a combination of (-Gb, Ga, -Gb) and the modified Golay sequence S ₂₅ is a combination of (Gb, -Ga, -Gb), temporally adjacent Golay sequences Are different combinations. For this reason, even partial information for Ga is different partial information.

In 128 the level of the preamble shown in FIG. _{4, Ga} 128 501 _{is, [- Gb 128; Ga 128} ; -Gb 128] in the middle of the Golay sequences. Therefore, the modified Golay sequence S ₁₉ corresponding to Ga ₁₂₈ 501 is indicated as “nGb_Ga_nGb”. Here, the notation “nGb” indicates “−Gb ₁₂₈ ”.

  As described above with reference to FIG. 3, the modified Golay sequence can be divided into front part information, intermediate part information, and rear part information. In addition, the front part information, the middle part, and the rear part information of the modified Golay sequence are represented as “f_Gx_Gy”, “m_Gy”, and “b_Gy_Gz”, respectively.

Therefore, the modified Golay series S ₁₉ is configured using “f_nGb_Ga” 507 as the previous partial information, “m_Ga” 508 as the intermediate partial information, and “b_Ga_nGb” 509 as the rear partial information.

Further, in the preamble shown in FIG. _{4, -Ga} 128 502 _lies in the middle of the Golay sequences _{[Gb 128; -Gb 128; -Ga} 128]. Therefore, the modified Golay sequence S ₂₅ corresponding to -Ga ₁₂₈ 502 is denoted as “Gb_nGa_nGb”.

Therefore, the modified Golay sequence S ₂₅ includes a code inversion block of “f_nGb_Ga” 507 as the previous partial information, a code inversion block of “m_Ga” 508 as the intermediate partial information, “b_nGa_nGb” 510 as the rear partial information, It is the structure containing. The sign inversion is performed by the sign inversion unit 105 shown in FIG.

As described above, in generating the corrected Golay sequence S ₁₉ and the corrected Golay sequence S ₂₅ , “f_nGb_Ga” 507 and “m_Ga” 508 stored in the memory 101 can be shared. Further, when limited to the modified Golay sequences S ₁₉ and S ₂₅ , partial information necessary for generating these modified Golay sequences is “f_nGb_Ga” 507, “m_Ga” 508, “b_Ga_nGb” 509, and “b_nGa_nGb” 510. Are four pieces of partial information.

  Accordingly, when information for generating each modified Golay sequence is stored in the memory 101, the memory capacity necessary for generating the modified Golay sequence can be reduced by removing duplicate information over the entire 192 level preamble. .

  FIG. 5 is a flowchart illustrating a method for generating in advance partial information necessary for generating a preamble after rate conversion. Note that the method of FIG. 5 is not performed by the preamble generation apparatus shown in FIG. 2, but by a computer that can execute a program (hereinafter referred to as “information generation apparatus”). In the following description, it is assumed that the number of taps of the interpolation filter is K and the length of the modified Golay sequence is L = 192.

First, the information generation apparatus selects the _first modified Golay sequence S1 in the 192-level preamble obtained by rate-converting the 128-level preamble in advance using an interpolation filter, for example (step S101). Then, the information generating apparatus divides modified Golay sequence _{S 1} the front part information, into three parts of the intermediate portion information and the rear part information (step S103).

For the previous partial information, the information generating apparatus stores the _first M preamble samples of the modified Golay sequence S1 in the memory 101 (step S105). Next, the information generation apparatus labels the stored preamble samples on the basis of the notation of the 128-level Golay sequence (Gy ₁₂₈ ) corresponding to the modified Golay sequence S ₁ and the previous Golay sequence (Gx ₁₂₈ ), respectively (f_Gx_Gy). ) Is added (step S107).

The intermediate partial information, the information generating device stores the M + 1 th corrected Golay sequences _{S 1} to L-N th preamble samples into the memory 101 (step S109). Next, the information generating apparatus attaches a label (m_Gy) to the stored preamble sample based on the notation of the 128-level Golay sequence (Gy ₁₂₈ ) corresponding to the modified Golay sequence S ₁ (step S111).

For the rear partial information, the information generating device stores the N preamble samples at the tail of the modified Golay sequence S _{1 in} the memory 101 (step S113). Next, the information generation device labels the stored preamble samples based on the respective notations of the 128-level Golay sequence (Gy ₁₂₈ ) corresponding to the modified Golay sequence S ₁ and the subsequent Golay sequence (Gz ₁₂₈ ) ( b_Gy_Gz) (step S115).

  Note that the values of M and N may be related to the number of taps K and the downsampling coefficient as M + N = (K−1) / 2. In the expression on the left, the downsampling coefficient is ½.

  Next, the information generating apparatus determines whether or not the current modified Golay sequence is the last modified Golay sequence in the 192-level preamble (step S117), and if it is the last modified Golay sequence, proceeds to step S119. If it is not a modified Golay series, the process proceeds to step S121. In step S121, the information generating apparatus selects the next modified Golay series (step S121), and returns to step S103. On the other hand, in step S119, the information generation apparatus deletes one of the preamble samples stored in the memory 101 while leaving one of the preamble samples with overlapping labels. Since the information stored in the memory 101 is merged by the process in step S119, the memory capacity can be reduced.

Hereinafter, a case where the method of the first embodiment described above is applied to a modified Golay sequence corresponding to the 128-level preamble shown in FIG. 1 will be described. First, the labels “f_0_Ga”, “m_Ga”, and “b_Ga_Ga” are attached to the front partial information, the intermediate partial information, and the rear partial information of the first modified Golay sequence S ₁ , respectively. The term “0” indicates that there is no previous Golay sequence at the 128th level, that is, the first Golay sequence. Next, the label “f_Ga_Ga”, “m_Ga”, and “b_Ga_Ga” are attached to the front part information, the intermediate part information, and the back part information of the second modified Golay series S ₂ , respectively.

Similarly, the labels “f_Ga_Ga”, “m_Ga”, and “b_Ga_Ga” are attached to the front part information, the intermediate part information, and the rear part information of the third modified Golay series S ₃ , respectively. This process, before the partial information of the last modification Golay sequence _{S 26,} the intermediate partial information, until each label in the rear section information is repeated for all modifications Golay sequence. Finally, in step S119, the labeled information stored in the memory 101 is merged.

For generation of the modified Golay series S ₂ and the modified Golay series S ₃ , three pieces of information “f_Ga_Ga”, “m_Ga”, and “b_Ga_Ga” can be shared. In addition, two pieces of information “m_Ga” and “b_Ga_Ga” can be shared to generate the modified Golay sequence S ₁ and the modified Golay sequence S ₂ . For this reason, in order to generate the modified Golay sequences S _{1 to} S ₂₆ , it is sufficient that the following information is stored in the memory 101.

・ Two intermediate part information:
“M_Ga”, “m_Gb”
・ 7 front part information:
“F_0_Ga”,
“F_Ga_Ga”, “f_Ga_nGa”,
“F_Ga_Gb”, “f_Ga_nGb”,
“F_Gb_Ga”, “f_Gb_nGa”
7 pieces of back information:
“B_Ga_Ga”, “b_Ga_nGa”,
“B_Ga_Gb”, “b_nGa_Gb”,
“B_Gb_nGa”, “b_nGb_nGa”,
“B_nGb_0”

  As described above, the length of each part constituting the modified Golay sequence depends on the number of taps of the interpolation filter and the implementation of the rate conversion process. For example, when the number of taps K = 71, the length of the modified Golay sequence L = 192, the length of the previous partial information of the modified Golay sequence M = 17, and the length of the subsequent partial information of the modified Golay sequence N = 18, the modified Golay sequence The lengths of the front part information, the middle part information, and the rear part information are 17 samples, 157 samples, and 18 samples, respectively.

  In the present embodiment described above, the modified Golay sequence that constitutes the preamble after rate conversion is divided into three parts, and the information of each part is stored in a state that is labeled depending on the Golay sequence before rate conversion. 101.

  For this reason, in the rate conversion of the preamble, it is possible to read the labeled information from the memory 101 to generate a modified Golay sequence, and to reduce power consumption due to the calculation for rate conversion. Therefore, power consumption can be reduced in the generation of the preamble after rate conversion.

  In addition, duplicate information in the labeled information stored in the memory 101 can be omitted. For this reason, the area | region which memorize | stores the information for producing | generating the correction | amendment Golay series in the memory 101 can be reduced. For example, in the preamble shown in FIG. 1, when all the preamble samples are stored in the memory, it is necessary to store all 26 × 192 = 4992 preamble samples according to the conventional method. On the other hand, according to the present embodiment, 2 × 157 + 7 × 17 + 7 × 18 = 559 preamble samples may be stored. In this way, it is possible to reduce the memory capacity exceeding 88.8%.

  FIG. 6 is a graph comparing the accuracy of the preamble generation method according to Patent Document 1 with the accuracy of the preamble generation method according to the present disclosure.

  In Patent Document 1, a preamble is generated by a filtering process using fixed point arithmetic, and in the method of the present disclosure, information is calculated using floating point arithmetic to generate a preamble. Also, the information calculated by the method shown in FIG. 5 is stored in the memory by changing the calculation result obtained by the floating point calculation to a fixed point.

  Graphs 702 and 706 shown in FIG. 6 show the correlation results of the Golay sequence Ga using fixed-point arithmetic, and graphs 704 and 708 show the correlation results of the Golay sequence Gb. In each graph, the horizontal axis represents the number of samples, and the vertical axis represents the amplitude indicating the correlation of the Golay series.

  For both preamble generation methods of FIG. 6, the average peak amplitude of the Golay correlator output of all Golay sequences in the preamble (including both STF and CEF) is calculated. At the transmitter, the same 5-bit width (1 bit for the sign, 1 bit for the integer part, 3 bits for the fractional part) is set for both methods. In the receiver, the same Golay correlator (Ga and Gb) having a 5 bit width (1 bit for the sign, 1 bit for the integer part, 3 bits for the fragment part) is used. The average peak shown by the graphs 702 and 704 based on the preamble generation method according to Patent Document 1 shown in FIG. 6 is 142.35, and the average peak shown by the graphs 706 and 708 based on the preamble generation method according to the present disclosure is 170.4. is there.

  Thus, the disclosed method exhibits a 1.6 dB improvement in average peak amplitude with high computational accuracy.

(Second Embodiment)
In the second embodiment, a description will be given of a preamble generation method in which each modified Golay sequence is divided into two parts by not considering either the Gox sequence Gx ₁₂₈ or Gz ₁₂₈ in FIG. FIG. 7 is a schematic diagram illustrating a method of storing each necessary information in a memory by dividing each modified Golay sequence into two parts without considering Gz ₁₂₈ .

  In the example shown in FIG. 7, the rear part information of the modified Golay series is treated as a fixed value. That is, the rear partial information is combined with the intermediate partial information mb_Gy by storing the (M + 1) th preamble sample of the modified Golay sequence up to the Lth preamble sample. In this case, “f_Gx_Gy” and “mb_Gy” are stored in the memory 101.

When this embodiment is applied to the modified Golay sequence corresponding to the 128-level preamble shown in FIG. 1, the previous partial information and the intermediate-rear partial information of the first modified Golay sequence S ₁ are labeled “f_0_Ga”, “Mb_Ga” is attached. Next, the label “f_Ga_Ga” and “mb_Ga” are attached to the front part information and the middle-back part information of the second modified Golay series S ₂ , respectively.

This process, before the partial information of the last modification Golay sequence _{S 26,} the intermediate - to the rear portion information is respectively labeled, it is repeated for all modifications Golay sequence.

  Finally, redundant information is omitted from the labeled information stored in the memory 101.

For generation of the modified Golay sequence S ₂ and the modified Golay sequence S ₃ , two pieces of information “f_Ga_Ga” and “mb_Ga” can be shared. Further, the information of “mb_Ga” can be shared for generation of the modified Golay sequence S ₁ and the modified Golay sequence S ₂ . For this reason, in order to generate the modified Golay sequences S _{1 to} S ₂₆ , it is sufficient that the following information is stored in the memory 101.

Two middle-rear information:
“Mb_Ga”, “mb_Gb”
・ 7 front part information:
“F_0_Ga”,
“F_Ga_Ga”, “f_Ga_nGa”,
“F_Ga_Gb”, “f_Ga_nGb”,
“F_Gb_Ga”, “f_Gb_nGa”

  Here, the intermediate-rear partial information “mb_Ga” and “mb_Gb” are intermediate-rear partial information stored in Ga and Gb, respectively. According to this method, the intermediate-rear part information is a factor that degrades the consistency with the original preamble sample, but the amount of samples stored in the memory 101 can be reduced.

Mb_Ga modifications Golay sequence, since the Golay sequence _{Gz 128} are _different, but not store separate preamble samples in the memory 101 in accordance with the _{Gz 128,} be different Golay sequences _{Gz 128,} a memory 101 a particular one mb_Ga1 Preamble samples can be reduced by storing in. For example, the specific mb_Ga may have the same content as the preamble sample in which the intermediate part information “m_Ga” and the rear part information “b_Ga_Ga” in Embodiment 1 are linked.

The same applies to the case where Gx ₁₂₈ of each modified Golay series is not considered.

  According to this embodiment, since the amount of information stored in the memory 101 is reduced, the memory capacity can be further reduced.

  In this embodiment, the preamble sample of the rear part information is treated as a fixed value, and the front part information and the middle-rear part information of each modified Golay sequence are labeled, but the preamble sample of the front part information is fixed. It may be handled as a value, and the front-intermediate part information and the rear part information of each modified Golay sequence may be labeled.

(Third embodiment)
In the third embodiment, the memory capacity is changed by omitting information on some parts of the modified Golay series. When the present embodiment is applied to the modified Golay sequence corresponding to the 128-level preamble shown in FIG. 1, the combination of adjacent Golay sequences preferentially replaces combinations other than different types of Golay sequences.

For example, the previous partial information “f_Ga_nGa” of the _17th modified Golay series S ₁₇ is preferentially replaced with “f_Ga_Ga”.

  Although “f_Ga_nGa” has been replaced, the partial information to be replaced differs depending on the permissible range of inconsistency errors for each system using the present embodiment.

For example, depending on the system, the previous partial information “f_0_Ga” of the first modified Golay sequence S ₁ is further replaced with “f_Ga_Ga”.

The memory 101 stores the following information.
・ Two intermediate part information:
“M_Ga”, “m_Gb”
・ Five front part information:
“F_Ga_Ga”,
“F_Ga_Gb”, “f_Ga_nGb”,
“F_Gb_Ga”, “f_Gb_nGa”
7 pieces of back information:
“B_Ga_Ga”, “b_Ga_nGa”,
“B_Ga_Gb”, “b_nGa_Gb”,
“B_Gb_nGa”, “b_nGb_nGa”,
“B_nGb_0”

  According to this embodiment, since the amount of information stored in the memory 101 is reduced, the memory capacity can be further reduced.

  Note that the degree of further reduction of the memory capacity described in the second and third embodiments is determined by the balance between the system performance and the mismatch error.

  It should be appreciated by those skilled in the art that the various parameters disclosed herein (eg, Golay sequence length, upsampling factor, downsampling factor) can be extended to any other value. The specified parameters are used to better understand the present disclosure.

  In each of the above-described embodiments, the present disclosure has been described by taking as an example a configuration using hardware. However, the present disclosure can also be realized by software in cooperation with hardware.

  In addition, each functional block used in the description of each of the above embodiments is typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them. The name used here is LSI, but it may also be called IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

  Further, the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection or setting of the circuit cells inside the LSI may be used.

  Further, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology. Biotechnology may also be applied.

Each embodiment described above includes disclosure of the following aspects.
<Disclosure 1 of preamble generation method>
A method of generating a preamble using a plurality of types of code sequences,
For each code sequence before rate conversion, selecting a plurality of pieces of partial information of the code sequence after rate conversion generated in advance for each combination pattern of code sequences adjacent to each code sequence;
Generating a code sequence after the rate conversion using the selected plurality of partial information;
including,
Preamble generation method.

<Disclosure 2 of preamble generation method>
A preamble generation method according to disclosure 1 above,
The generating step includes
A code inversion step of inverting the codes of the selected plurality of partial information in accordance with each code sequence before the rate conversion;
Preamble generation method.

<Disclosure 3 of preamble generation method>
A preamble generation method according to disclosure 1 above,
The partial information is
First partial information having different information depending on a combination pattern of code sequences adjacent to each of the code sequences;
In all patterns of combinations of code sequences adjacent to the respective code sequences, the second partial information having the same information,
Preamble generation method.

<Disclosure 4 of preamble generation method>
A preamble generation method according to disclosure 3 above,
The first partial information is
Among the code sequences adjacent to each of the code sequences, the previous partial information whose information is different depending on the combination pattern with the code sequence adjacent in time earlier,
Including the rear partial information whose information is different depending on the combination pattern with the code sequence adjacent in the time sequence among the code sequences adjacent to the respective code sequences,
Preamble generation method.

<Disclosure 5 of preamble generation method>
A preamble generation method according to disclosure 3 above,
The first partial information is
Of the code sequences adjacent to each of the code sequences, the information differs depending on the combination pattern with the code sequence adjacent in time earlier,
The second partial information is
Among all the code sequences adjacent to each of the code sequences, the information is the same in all patterns in combination with the code sequence adjacent to the back in time.
Preamble generation method.

<Disclosure 6 of preamble generation method>
A preamble generation method according to disclosure 3 above,
The first partial information is
Of the code sequences adjacent to each of the code sequences, the information varies depending on the combination pattern with the code sequence adjacent in time,
The second partial information is
Among the code sequences adjacent to each of the code sequences, the information is the same in all patterns of combinations with code sequences adjacent in time before,
Preamble generation method.

<Disclosure 7 of preamble generation method>
A preamble generation method according to disclosure 3 above,
In the first partial information,
Among the combinations of code sequences adjacent to each of the code sequences, the combination pattern of the same type of code sequences having different codes uses any one pattern.
Preamble generation method.

<Disclosure 1 of Preamble Generation Device>
A preamble generation device that generates a preamble using a plurality of types of code sequences,
For each code sequence before rate conversion, a memory for accumulating a plurality of pieces of partial information of the code sequence after rate conversion generated in advance for each combination pattern of code sequences adjacent to each code sequence;
A controller for controlling the timing of outputting the partial information from the memory according to each code sequence before the rate conversion;
including,
Preamble generator.

<Disclosure 2 of preamble generator>
A preamble generation device according to the disclosure 1, wherein
A code inversion unit for inverting the code of the partial information output from the memory according to each code sequence before the rate conversion;
Preamble generator.

<Disclosure 3 of Preamble Generation Device>
A preamble generation device according to the disclosure 1, wherein
The partial information is
First partial information having different information depending on a combination pattern of code sequences adjacent to each of the code sequences;
In all patterns of combinations of code sequences adjacent to the respective code sequences, the second partial information having the same information,
Preamble generator.

<Disclosure 4 of Preamble Generation Device>
A preamble generation apparatus according to the third disclosure,
The first partial information is
Among the code sequences adjacent to each of the code sequences, the previous partial information whose information is different depending on the combination pattern with the code sequence adjacent in time earlier,
Including the rear partial information whose information is different depending on the combination pattern with the code sequence adjacent in the time sequence among the code sequences adjacent to the respective code sequences,
Preamble generator.

<Disclosure 5 of Preamble Generation Device>
A preamble generation apparatus according to the third disclosure,
The first partial information is
Of the code sequences adjacent to each of the code sequences, the information differs depending on the combination pattern with the code sequence adjacent in time earlier,
The second partial information is
Among all the code sequences adjacent to each of the code sequences, the information is the same in all patterns in combination with the code sequence adjacent to the back in time.
Preamble generator.

<Disclosure 6 of preamble generator>
A preamble generation apparatus according to the third disclosure,
The first partial information is
Of the code sequences adjacent to each of the code sequences, the information varies depending on the combination pattern with the code sequence adjacent in time,
The second partial information is
Among the code sequences adjacent to each of the code sequences, the information is the same in all patterns of combinations with code sequences adjacent in time before,
Preamble generator.

<Disclosure 7 of Preamble Generation Device>
A preamble generation apparatus according to the third disclosure,
In the first partial information,
Among the combinations of code sequences adjacent to each of the code sequences, the combination pattern of the same type of code sequences having different codes uses any one pattern.
Preamble generator.

  The preamble generation method according to the present disclosure is useful as a method for reducing power consumption used for generation of a preamble in a system that requires rate conversion.

101 Memory 103 Address controller 107 DAC
105 Sign inversion unit

Claims (14)

A method of generating a preamble using a plurality of types of code sequences,
For each code sequence before rate conversion, selecting a plurality of pieces of partial information of the code sequence after rate conversion generated in advance for each combination pattern of code sequences adjacent to each code sequence;
Generating a code sequence after the rate conversion using the selected plurality of partial information;
including,
Preamble generation method. The preamble generation method according to claim 1, comprising:
The generating step includes
A code inversion step of inverting the codes of the selected plurality of partial information in accordance with each code sequence before the rate conversion;
Preamble generation method. The preamble generation method according to claim 1, comprising:
The partial information is
First partial information having different information depending on a combination pattern of code sequences adjacent to each of the code sequences;
In all patterns of combinations of code sequences adjacent to the respective code sequences, the second partial information having the same information,
Preamble generation method. The preamble generation method according to claim 3, wherein
The first partial information is
Among the code sequences adjacent to each of the code sequences, the previous partial information whose information is different depending on the combination pattern with the code sequence adjacent in time earlier,
Including the rear partial information whose information is different depending on the combination pattern with the code sequence adjacent in the time sequence among the code sequences adjacent to the respective code sequences,
Preamble generation method. The preamble generation method according to claim 3, wherein
The first partial information is
Of the code sequences adjacent to each of the code sequences, the information differs depending on the combination pattern with the code sequence adjacent in time earlier,
The second partial information is
Among all the code sequences adjacent to each of the code sequences, the information is the same in all patterns in combination with the code sequence adjacent to the back in time.
Preamble generation method. The preamble generation method according to claim 3, wherein
The first partial information is
Of the code sequences adjacent to each of the code sequences, the information varies depending on the combination pattern with the code sequence adjacent in time,
The second partial information is
Among the code sequences adjacent to each of the code sequences, the information is the same in all patterns of combinations with code sequences adjacent in time before,
Preamble generation method. The preamble generation method according to claim 3, wherein
In the first partial information,
Among the combinations of code sequences adjacent to each of the code sequences, the combination pattern of the same type of code sequences having different codes uses any one pattern.
Preamble generation method. A preamble generation device that generates a preamble using a plurality of types of code sequences,
For each code sequence before rate conversion, a memory for accumulating a plurality of pieces of partial information of the code sequence after rate conversion generated in advance for each combination pattern of code sequences adjacent to each code sequence;
A controller for controlling the timing of outputting the partial information from the memory according to each code sequence before the rate conversion;
including,
Preamble generator. The preamble generation device according to claim 8, wherein
A code inversion unit for inverting the code of the partial information output from the memory according to each code sequence before the rate conversion;
Preamble generator. The preamble generation device according to claim 8, wherein
The partial information is
First partial information having different information depending on a combination pattern of code sequences adjacent to each of the code sequences;
In all patterns of combinations of code sequences adjacent to the respective code sequences, the second partial information having the same information,
Preamble generator. The preamble generation device according to claim 10, wherein
The first partial information is
Among the code sequences adjacent to each of the code sequences, the previous partial information whose information is different depending on the combination pattern with the code sequence adjacent in time earlier,
Including the rear partial information whose information is different depending on the combination pattern with the code sequence adjacent in the time sequence among the code sequences adjacent to the respective code sequences,
Preamble generator. The preamble generation device according to claim 10, wherein
The first partial information is
Of the code sequences adjacent to each of the code sequences, the information differs depending on the combination pattern with the code sequence adjacent in time earlier,
The second partial information is
Among all the code sequences adjacent to each of the code sequences, the information is the same in all patterns in combination with the code sequence adjacent to the back in time.
Preamble generator. The preamble generation device according to claim 10, wherein
The first partial information is
Of the code sequences adjacent to each of the code sequences, the information varies depending on the combination pattern with the code sequence adjacent in time,
The second partial information is
Among the code sequences adjacent to each of the code sequences, the information is the same in all patterns of combinations with code sequences adjacent in time before,
Preamble generator. The preamble generation device according to claim 10, wherein
In the first partial information,
Among the combinations of code sequences adjacent to each of the code sequences, the combination pattern of the same type of code sequences having different codes uses any one pattern.
Preamble generator.

Images