JP2014002787A - Multi-core processor system, cache coherency control method, and cache coherency control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce operations within a cache coherency mechanism.SOLUTION: A multi-core processor system 100 includes an execution unit 503 that executes coherency of the value of shared data stored in a cache memory that is accessed by each of CPUs. The multi-core processor system 100 detects a first thread executed by a CPU #0, and specifies a second thread under execution by a CPU #1 other than the CPU #0. After the specification, the multi-core processor system 100 determines whether there are shared data that are accessed by the first and second threads in common. When it is determined that there are not shared data, the multi-core processor system 100 makes the execution unit 503 stop the execution of coherency between a snooping cache #0 corresponding to the CPU #0 and a snooping cache #1 corresponding to the CPU #1.

Description

  The present invention relates to a multi-core processor system that controls a cache coherency mechanism, a cache coherency control method, and a cache coherency control program.

  In recent years, multi-core processor systems are equipped with an independent cache memory for each core, and the cache coherency mechanism is used to maintain the consistency of the cache memory. In a multi-core processor system using a cache coherency mechanism, parallel software for a multi-core processor can be easily created in order to maintain the consistency of shared data stored in a cache memory with hardware.

  Since the cache coherency mechanism monitors the operation of the cache memory, a delay occurs when the cache memory is accessed. As a technique for preventing a delay, a technique for controlling a cache coherency mechanism based on SMP (Symmetric Multi Processing) or ASMP (Asymmetric Multi Processing) is disclosed (for example, see Patent Document 1 below). In Patent Document 1, a case where a plurality of cores executes a plurality of processes is referred to as SMP, and a case where a plurality of cores execute a single process is referred to as ASMP. A process is a program execution unit, and one or more threads belong to one process. Threads belonging to the same process access the same memory space.

  As another technique, a technique is disclosed in which a plurality of cores execute coherency when executing threads belonging to the same process, and do not execute coherency when executing threads belonging to different processes. (For example, see Patent Document 2 below.)

  In addition, as a technology for analyzing the dependency relationship between threads, a technology is disclosed in which information representing access to shared data is created by executing each thread for each statement, and the dependency relationship for each statement of the thread is analyzed. (For example, refer to Patent Document 3 below.)

Japanese Patent Laid-Open No. 10-97465 Japanese Patent Laid-Open No. 2004-133753 JP 2000-207248 A

  In the prior art described above, the techniques according to Patent Documents 1 and 2 determine whether or not to execute coherency in units of processes. When many functions such as embedded devices are not used at the same time, they are often executed in a single process. Therefore, even if the techniques according to Patent Documents 1 and 2 are applied to an embedded device, coherency is always executed, and the operation of the cache coherency mechanism increases, causing delay to the cache memory and increasing power consumption. There was a problem of inviting.

  Further, when the technique according to Patent Document 3 is used, the access information of the shared data is analyzed for each statement, so that the cache coherency mechanism is controlled for each statement, and the number of times of control is greatly increased. was there.

  An object of the present invention is to provide a multi-core processor system, a cache coherency control method, and a cache coherency control program capable of reducing the operation of a cache coherency mechanism in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, a disclosed multi-core processor system is a multi-core processor system having a plurality of cache memories accessed by each of a plurality of cores, and any one of the plurality of cores is When a first thread executed by the first core among the plurality of cores is detected, a second thread being executed by the second core other than the first core among the plurality of cores is detected. If there is no shared data that is commonly accessed during execution of the first thread and the second thread, the first cache memory corresponding to the first core and the second core among the plurality of cache memories The coherency process with the corresponding second cache memory is stopped.

  According to the multi-core processor system, the cache coherency control method, and the cache coherency control program, operations in the cache coherency mechanism can be reduced, and power consumption can be reduced and delay can be prevented.

It is a block diagram which shows the hardware of the multi-core processor system 100 concerning embodiment. 2 is a block diagram showing a part of hardware and software of the multi-core processor system 100. FIG. It is a block diagram which shows the inside of snoop corresponding | compatible cache # 0. It is explanatory drawing which shows the detail of the bus | bath 110 corresponding to a snoop. 2 is a block diagram showing functions of a multi-core processor system 100. FIG. It is explanatory drawing which shows the execution state and stop state of cache coherency. 2 is an operation overview of the multi-core processor system 100. It is explanatory drawing which shows the registration method of the dependence information. It is explanatory drawing which shows an example of the member list of the extended thread | sled data structure 901, and the memory content. It is a flowchart which shows the line fetch process by the snoop control part # 0. It is a flowchart which shows the write-in process to the line by the snoop control part # 0. It is a flowchart which shows a coherency control process. It is a flowchart which shows a coherency target CPU determination process.

  Exemplary embodiments of a multi-core processor system, a cache coherency control method, and a cache coherency control program according to the present invention will be described below in detail with reference to the accompanying drawings.

(Hardware of the multi-core processor system 100)
FIG. 1 is a block diagram illustrating hardware of a multi-core processor system 100 according to the embodiment. In FIG. 1, a multi-core processor system 100 includes CPUs 101 on which a plurality of CPUs are mounted, a ROM (Read-Only Memory) 102, and a RAM (Random Access Memory) 103. The multi-core processor system 100 includes a flash ROM 104, a flash ROM controller 105, and a flash ROM 106. The multi-core processor system 100 includes a display 107, an I / F (Interface) 108, and a keyboard 109 as input / output devices for a user and other devices. Each unit is connected by a bus 110.

  Here, the CPUs 101 govern the overall control of the multi-core processor system 100. CPUs 101 refers to all CPUs in which single-core processors are connected in parallel. Details of the CPUs 101 will be described later with reference to FIG. A multi-core processor system is a computer system including a processor having a plurality of cores. In the present embodiment, in order to simplify the explanation, a processor group in which single-core processors are arranged in parallel will be described as an example.

  The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPUs 101. The flash ROM 104 stores system software such as an OS (Operating System), application software, and the like. For example, when updating the OS, the multi-core processor system 100 receives the new OS through the I / F 108 and updates the old OS stored in the flash ROM 104 to the received new OS.

  The flash ROM controller 105 controls data read / write with respect to the flash ROM 106 according to the control of the CPUs 101. The flash ROM 106 stores data written under the control of the flash ROM controller 105. Specific examples of the data include image data and video data acquired by the user using the multi-core processor system 100 through the I / F 108. As the flash ROM 106, for example, a memory card, an SD card, or the like can be adopted.

  A display 107 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As the display 107, for example, a TFT liquid crystal display can be adopted.

  The I / F 108 is connected to a network 111 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to other devices via the network 111. The I / F 108 controls an internal interface with the network 111 and controls data input / output from an external device. For example, a modem or a LAN adapter can be employed as the I / F 108. The keyboard 109 includes keys for inputting numbers, various instructions, and the like, and inputs data. The keyboard 109 may be a touch panel type input pad or a numeric keypad.

  FIG. 2 is a block diagram showing a part of hardware and software of the multi-core processor system 100. The hardware shown in FIG. 2 is a cache coherency mechanism 201, a shared memory 202, and CPUs # 0 to CPU # 3 included in the CPUs 101. The shared memory 202 and the CPUs # 0 to # 3 are connected by a cache coherency mechanism 201. In addition, the CPUs # 0 to # 3 hold a cache memory in which the data in the shared memory 202 is copied in order to be able to access the data in the shared memory 202 at high speed. The cache memories of CPU # 0 to CPU # 3 in the present embodiment exist inside the cache coherency mechanism 201.

  The cache coherency mechanism 201 is a device that takes consistency of the cache memory accessed by the CPUs # 0 to # 3. The cache coherency mechanism is roughly classified into a snoop method and a directory method.

  The snoop method is a method in which the cache memory manages the update state of its own cache memory and the cache memory of another CPU and exchanges update state information with other cache memories. By exchanging information on the update state, the cache coherency mechanism adopting the snoop method determines in which cache memory the latest data exists. In addition, the cache coherency mechanism using the snoop method changes the state of its own cache memory or invalidates the cache memory so that each cache memory can acquire the latest data.

  The directory system is a system in which the consistency of cache memory is centrally managed in a dedicated area called a directory. In a cache coherency mechanism using a directory system, data is sent from a cache memory to a directory, and all the cache memories share the data.

  In any method, the cache coherency mechanism 201 determines whether the cache memory of each CPU matches the shared memory 202 serving as the main memory. When a mismatch occurs, the cache coherency mechanism 201 resolves the mismatch by copying, updating, invalidating, etc. the cache memory to achieve a match. The cache coherency mechanism 201 in the present embodiment will be described by a snoop method, but the present embodiment can be applied even by a directory method.

  In the cache coherency mechanism 201, there is a snoop-compatible cache # 0 to snoop-compatible cache # 3 and a snoop-compatible bus 110. CPU # 0 to CPU # 3 access the corresponding snoop corresponding cache # 0 to snoop corresponding cache # 3, respectively. For example, CPU # 0 accesses snoop-compatible cache # 0. Details of the snoop-compatible cache will be described later with reference to FIG.

  The snoop compatible bus 110 is a bus that has a function added to support snoop in addition to the conventional bus function. Details of the snoop compatible bus 110 will be described later with reference to FIG. The snoop-compatible cache # 0 is connected to the snoop-compatible bus 110 by the master I / F # 0 and the slave I / F # 0. Similarly, the snoop-compatible cache # 1 to the snoop-compatible cache # 3 are also connected to the snoop-compatible bus 110 at each master I / F and slave I / F.

  The shared memory 202 is a storage area accessible from the CPUs # 0 to # 3. Specifically, the storage area is, for example, the ROM 102, the RAM 103, and the flash ROM 104.

  The software shown in FIG. 2 is the OS 203 and thread # 0 to thread # 3. The OS 203 is a program that controls the multi-core processor system 100. Specifically, the OS 203 performs software scheduling processing executed by the CPUs # 0 to # 3. Thread # 0 to thread # 3 are threads assigned to CPU # 0 to CPU # 3 by OS 203. Thread # 0 to thread # 3 may belong to the same process or may belong to different processes.

  FIG. 3 is a block diagram showing the inside of the snoop-compatible cache # 0. In FIG. 3, the inside will be described using the snoop compatible cache # 0 out of the snoop compatible cache # 0 to the snoop compatible cache # 3.

  Snoop-compatible cache # 0 includes a cache line storage unit # 0 and a cache line control unit # 0. The cache line storage unit # 0 includes a data field, an address field, and a state field. The data field stores data in units of continuous data called lines of about several tens of bytes. The address field stores an address corresponding to the line stored in the data field on the shared memory 202. The state field stores the state of the data field. The address field and the state field are combined into a tag area.

  The states that the state field can take vary depending on the protocol that implements the snoop method, but there are four typical states: M state, E state, S state, and I state.

  The M state indicates a state in which the corresponding line exists only in the corresponding cache memory and is changed from the main memory. The E state indicates a state in which the corresponding line exists only in the corresponding cache memory and has not been changed from the main memory. The S state indicates a state where corresponding lines exist in a plurality of cache memories and are not changed from the main memory. The I state indicates a state where the corresponding line is invalid. In addition, as an O state different from the above four states, there is a protocol that uses a state in which the corresponding line exists in a plurality of cache memories, the corresponding line is updated, and is responsible for writing back to the main memory. To do.

  Protocols for realizing the snoop method are roughly classified into an invalid protocol and an update protocol. The invalid protocol is a protocol for invalidating a corresponding line of all the caches being referred to as an address being dirty when a certain cache memory updates a reference address from a plurality of cache memories. The update-type protocol is a protocol for notifying update data to the main memory and other cache memories when data is updated with respect to addresses referenced by a plurality of cache memories.

  As an example of the invalid protocol, MESI (Illinois) protocol that takes four states of M state, E state, S state, and I state, or four states of M state, O state, S state, and I state There is a MOSI (Berkeley) protocol and the like. As an example of the update type protocol, MEI (Firefly) protocol that takes three states of M state, E state, and I state, or MOES (DRAGON) that takes four states of M state, O state, E state, and S state ) Protocols exist.

  In the present embodiment, the MESI protocol, which is one of the invalid protocols, will be described as an example. However, the present embodiment can be applied to other invalid protocols and update protocols. it can.

  The cache line control unit # 0 has various functions such as a data storage structure determination process, a line replacement process, a data update process, and the like required to realize the cache memory function. The cache line control unit # 0 is connected to the corresponding CPU # 0 via a CPU I / F, and is connected to the bus 110 via a master I / F # 0 and a slave I / F # 0.

  Further, the cache line control unit # 0 includes a snoop control unit # 0 to cope with snoop. The snoop control unit # 0 has a function of controlling the cache line storage unit # 0 according to a protocol that realizes the snoop method. The snoop control unit # 0 in the present embodiment controls the cache line storage unit # 0 according to the MESI protocol. The snoop control unit # 0 performs processing for newly fetching a cache line and processing for writing to the cache line. The above two processes will be described later with reference to FIGS.

  Since snoop-compatible caches exist for each of CPU # 0 to CPU # 3, there are also cache line storage units and cache line control units that are internal structures of the snoop-compatible cache for each CPU. For example, the cache line storage unit # 1 indicates the cache line storage unit of the snoop-compatible cache # 1. The cache line storage unit # 2 and the cache line storage unit # 3 also correspond to the snoop compatible cache # 2 and the snoop compatible cache # 3, respectively. The same applies to the cache line control unit and the snoop control unit.

  FIG. 4 is an explanatory diagram showing details of the bus 110 corresponding to the snoop. A line in FIG. 4 is one physical signal line, and a black circle represents a connection between the signal lines. Bus 110 receives signals from master I / F # 0 to master I / F # 3 and slave I / F # 0 to slave I / F # 3. The master I / F sends out address information and command information such as read or write. The controller 401 outputs a select signal to the corresponding slave I / F based on the address information and the mapping information registered in the controller 401 in advance. The slave I / F that has received the select signal receives address information and command information, and exchanges data according to the command information.

  In the example of FIG. 4, the controller 401 receives the signal transmitted by the master I / F # 0. For example, the controller 401 outputs a select signal to the slave I / F # 1 to the slave I / F # 3. The slave IF # 1 to slave I / F # 3 that have received the select signal receive the address information and the command information, and exchange data according to the command information.

  Furthermore, the bus 110 corresponding to the snoop is added with three functions such as broadcast, block, and invalidate. Broadcasting is a function for sending a request for a combination of command information and data information from a master I / F to all slave I / Fs set in advance as broadcast destinations. The block is a function for forcibly releasing the current bus connection. Invalidation is a function for invalidating a line corresponding to an address for a cache memory. By using these functions, the bus 110 satisfies the functions required as a cache coherency mechanism.

(Functions of the multi-core processor system 100)
Next, functions of the multi-core processor system 100 will be described. FIG. 5 is a block diagram showing functions of the multi-core processor system 100. The multi-core processor system 100 includes an execution unit 503, a detection unit 504, a specifying unit 505, a determination unit 506, and a control unit 507. The function (detection unit 504 to control unit 507) serving as the control unit is realized by, for example, CPU # 0 executing a program stored in the storage device. Specifically, the storage device is, for example, the ROM 102, the RAM 103, the flash ROM 104, or the like shown in FIG. The execution unit 503 realizes its function by the cache coherency mechanism 201 executing it.

  In addition, the multi-core processor system 100 can access the dependency information 501 that stores a list of threads that do not access the same shared data and an interprocess communication area that is not accessed by any thread. . Details of the dependency information 501 will be described later with reference to FIG.

  The detection unit 504 to the control unit 507 may exist as an internal function in the scheduler 502, or may exist outside the scheduler 502 and in a state in which the processing result of the scheduler 502 can be notified. . The scheduler 502 is software included in the OS 203 and has a function of determining a process to be assigned to the CPU. In FIG. 5, the detection unit 504 to the control unit 507 exist in the CPU # 0, but may exist in any of the CPUs # 1 to # 3, or the CPUs # 0 to # 0. It may exist in all of CPU # 3.

  For example, the scheduler 502 determines the next thread to be assigned to the CPU based on the priority set for the thread. When the predetermined time comes, the scheduler 502 assigns the thread for which the dispatcher is determined to the CPU. There is a form including a dispatcher as one of the functions of the scheduler. In the present embodiment, a dispatcher function exists in the scheduler 502.

  The execution unit 503 has a function of executing coherency of the value of the shared data stored in the cache memory accessed by each of the plurality of cores. For example, the cache coherency mechanism 201 serving as the execution unit 503 executes coherency of values of shared data in the snoop-compatible cache # 0 accessed by the CPU # 0 and the snoop-compatible cache # 1 accessed by the CPU # 1.

  The detection unit 504 has a function of detecting a first thread executed by the first core among the plurality of cores. For example, the detection unit 504 detects the thread A-1 executed by the CPU # 0 serving as the first core. Specifically, the timing at which the thread A-1 is detected is when the scheduler 502 makes a thread rescheduling request. The detected thread information is stored in a register of CPU # 0, a local memory, or the like.

  When the detecting unit 504 detects the first thread, the specifying unit 505 has a function of specifying the second thread being executed by the second core other than the first core from the plurality of cores. For example, when the thread A-1 is detected, the identifying unit 505 identifies the thread A-2 being executed by the CPU # 1 other than the CPU # 0 to CPU # 3, for example, the CPU # 1. The information on the identified thread is stored in a register of CPU # 0, a local memory, or the like.

  The determination unit 506 has a function of determining whether there is shared data that is commonly accessed by the first thread and the second thread specified by the specifying unit 505. The determination unit 506 may further determine whether or not the first and second threads belong to the same process. Further, the determination unit 506 determines whether the first and second threads belong to different processes and an interprocess communication area that is commonly used by the first and second threads exists. May be. Details of the inter-process communication area will be described later with reference to FIG.

  The determination unit 506 may determine whether there is an interprocess communication area in which the processes to which the first and second threads belong are used. In addition, when the determination unit 506 determines whether or not there is an interprocess communication area that is used in common, first, at least one of the first and second threads uses the interprocess communication area. You may judge the state which is not. When both the first and second threads use the interprocess communication area, the determination unit 506 determines whether there is an interprocess communication area commonly used by the first and second threads. It may be determined whether or not.

  For example, the determination unit 506 accesses the dependency information 501 and is commonly accessed by threads depending on whether or not the second thread is included in the list of threads that do not access the same shared data of the first thread. Determine whether shared data exists. Further, the determination unit 506 accesses the dependency information 501 and determines whether there is an interprocess communication area that is commonly used from the interprocess areas that are not accessed by the first and second threads. Also good. The determination result is stored in a register of CPU # 0, a local memory, or the like.

  When the determination unit 506 determines that there is no shared data accessed in common by the determination unit 506, the control unit 507 uses the first and second cache memories respectively corresponding to the first and second cores by the execution unit 503. Has a function of stopping the execution of coherency. When the control unit 507 determines that the first and second threads are the same process, and determines that there is no shared data to be accessed in common, the control unit 507 Execution of coherency with the memory may be stopped. Further, when it is determined that the first and second threads belong to different processes and there is no interprocess communication area used in common, the control unit 507 determines that the first and second cache memories The coherency execution may be stopped.

  In addition, when the execution of coherency with the first and second cache memories is stopped, the control unit 507 may delete the shared data stored in the first cache memory from the first cache memory.

  For example, it is assumed that the determination unit 506 determines that there is no shared data that is commonly accessed by the thread A-1 and the thread A-2. At this time, the control unit 507 causes the cache coherency mechanism 201 to stop executing the coherency of the snoop-compatible cache # 0 and the snoop-compatible cache # 1. Further, the control unit 507 flushes the shared data stored in the snoop-compatible cache # 0, thereby deleting the shared data from the snoop-compatible cache # 0. A specific flash operation will be described later with reference to FIG.

  FIG. 6 is an explanatory diagram showing an execution state and a stop state of cache coherency. A block diagram denoted by reference numeral 601 shows threads held by the process A operating in the multi-core processor system 100 and memory accessed by each thread. The process A has a thread A-1, a thread A-2, and a thread A-3. The thread A-1 accesses data A in the process A data area of the shared memory 202. The thread A-2 accesses the data B. The thread A-3 accesses data A and data B.

  Under the premise indicated by reference numeral 601, in the multi-core processor system 100 indicated by reference numeral 602, the thread A- 1 is assigned to the CPU # 0 and the thread A- 3 is assigned to the CPU # 1. In the state indicated by reference numeral 602, the cache coherency mechanism 201 executes cache coherency, so that the CPU # 0 and the CPU # 1 can share the data A in a consistent state.

  Next, in the multi-core processor system 100 denoted by reference numeral 603, the thread assigned to the CPU # 1 is switched from the thread A-3 to the thread A-2 from the state denoted by reference numeral 602. In the state indicated by reference numeral 603, the CPU # 0 and the CPU # 1 do not have shared data to be accessed, so the cache coherency mechanism 201 may stop executing the cache coherency. In order to invalidate the cache coherency, for example, when performing broadcast transmission on the bus 110 corresponding to the snoop described above with reference to FIG. 4, the execution of cache coherency is stopped by excluding it from the broadcast destination.

  As a specific invalidation method, there is a method of stopping broadcasting of the snoop-compatible cache # 0 and the snoop-compatible cache # 1 on the bus 110. For example, when the cache coherency mechanism 201 broadcasts an invalidation notification or the like from the master I / F # 0 of the snoop-compatible cache # 0, the cache coherency mechanism 201 does not transmit the slave I / F # 1 to the slave I / F # 2. To the slave I / F # 3. As described above, in the cache coherency mechanism 201, when the execution of cache coherency between specific CPUs is stopped, the number of transmission destinations decreases, so the traffic amount and processing amount of the bus 110 decrease, power consumption is reduced, and Delay can be prevented.

  FIG. 7 is an outline of the operation of the multi-core processor system 100. In FIG. 7, processing 701 to processing 710 are shown as processing groups for realizing switching between execution and stop of the cache coherency mechanism 201 based on shared data accessed by threads as shown in FIG. 6. Processing 701 and processing 702 are executed when the multi-core processor system 100 is designed, and processing 703 to processing 710 are executed during the operation of the multi-core processor system 100.

  In the process 701, the dependency between threads belonging to the target process is analyzed by using an ESL (Electronic System Level) simulator or the like. A specific analysis example will be described later with reference to FIG. After the analysis, in the process 702, the program that is the source of the target process is rewritten by the compiler. Specifically, the compiler adds information on a thread having a dependency relationship with a specific thread to the head of the specific thread.

  In processing 703, the CPU that executes the target process newly generates a thread. After the generation, in the process 704, the CPU adds the dependency relationship information added by the compiler to the dependency information 501 in the OS 203. Details of the dependency information 501 will be described later with reference to FIG. After the addition, the target process makes a thread allocation request to the OS 203, and in step 705, the CPU determines the allocation by the scheduler 502 in the OS 203 and executes the generated thread.

  In process 706, the scheduler 502 of the OS 203 determines a thread to be assigned to the target CPU. The thread to be determined is determined from the thread generated in the process 703 and the thread in an executable state. After determining the thread, the scheduler 502 acquires a thread being executed by another CPU in a process 707.

  After acquiring the executing thread, the scheduler 502 determines execution or stop of coherency from the registered dependency information 501 in processing 708. After the determination, in step 709, the scheduler 502 controls the cache coherency mechanism 201 according to the determined content. After the control, the scheduler 502 assigns the determined thread to the target CPU in process 710. Details of processing 706 to processing 710 will be described later with reference to FIGS.

  FIG. 8 is an explanatory diagram showing a method for registering the dependency information 501. FIG. 8 shows a method for registering the dependency information 501 for the process A indicated by reference numeral 601. At the time of designing the multi-core processor system 100, the ESL simulator investigates the data area used by each thread for the thread in the process A that performs thread parallel processing.

  There are static methods to obtain the data area to be used by analyzing the source code, and dynamic methods to obtain the data area to be used by the thread from the memory access record by actually executing the thread. . If complete analysis of the data area of the thread is difficult, a combination of threads that are clearly found not to share the data area may be recorded.

  In addition to the data area sharing investigation, if the investigation target thread has an area that is obviously not used in the inter-process communication area provided by the OS 203, that area is also recorded. The inter-process communication area is an area for performing communication between a plurality of processes, and is provided by the OS 203 using an API (Application Programming Interface) or the like. In general, the memory space is independent between processes, and it is not possible to directly access each other's memory space. Therefore, when information is transmitted / received between processes, the process transmits / receives information using an inter-process communication area. For example, the OS 203 secures a chunk that becomes a lump of memory space, and provides the secured chunk as an interprocess communication area to a process.

  Reference numeral 801 denotes a program that is a source of the process A. The ESL simulator registers the information of the thread that does not share data and the information of the inter-process communication area that is not used as a result of the investigation into the dependency information 501 when the thread is activated during the execution of the process A. Change the program. The compiler compiles the changed program and generates an execution code. Specifically, in FIG. 8, since there is no shared data that is commonly accessed in the thread A-1 and the thread A-2, the ESL simulator includes the thread A-1 and the thread A in the program of the process A. -2 adds no dependency.

  The OS 203 registers information on threads that do not share data in the dependency information 501. In the dependency relationship 802 between threads of the process A shown in FIG. 8, “no dependency” is registered in the thread A-1 and the thread A-2. The OS 203 extends the thread data structure as dependency information 501 for managing information on threads that do not share data and interprocess communication areas that are not used. The extended thread data structure will be described later with reference to FIG.

  FIG. 9 is an explanatory diagram showing an example of a member list and stored contents of the extended thread data structure 901. In FIG. 9, as an example of the expanded thread data structure 901 and the stored contents of the thread data structure 901, a table 902, a thread ID list 903, a thread ID list 904, an inter-process communication area list 905, and an inter-process communication area list 906 Is shown.

  In the thread ID field of the thread data structure 901, a value assigned for each thread is set. In the thread function field, the function name of the thread is set. In addition, a field existing in the conventional thread data structure exists as a field of the thread data structure 901. Also, the thread ID list field that does not share data and the inter-process communication area list field that is not used, which are the entities of the dependency information 501, are fields expanded in this embodiment.

  In the thread ID list field that does not share data, a pointer to a thread ID list that does not share data with the target thread is set. For example, in Table 902, for the Browser_Main thread whose thread ID is “1”, the thread ID list 903 is set in the thread ID list field that does not share data. In the thread ID list 903, threads having a thread ID “2” and a thread ID “3” are registered. As a result, the Browser_Main thread indicates that there is no data sharing between the Browser_Download thread whose thread ID is “2” and the Browser_Upload thread whose thread ID is “3”.

  Similarly, a thread ID list 904 is set in the thread ID list field that does not share data of the Browser_Download thread. The content of the thread ID list 904 indicates that the Browser_Download thread does not share data with the Browser_Main thread.

  In the unused inter-process communication area list field, a pointer to an inter-process communication area list that is not used by a thread is set. For example, in the Browser_Main thread, the inter-process communication area list 905 is set in the inter-process communication area list field that is not used. Chunk 3 and chunk 4 are registered in the inter-process communication area list 905.

  Further, the FTP_Download thread with the thread ID “4” executed as a process different from the Browser_Main thread has the inter-process communication area list 906 set in the inter-process communication area list field that is not used. Chunk 1 and chunk 2 are registered in the inter-process communication area list 906. When the chunks secured by the OS 203 are chunk 1 to chunk 4, the inter-process communication area list 905 and the inter-process communication area list 906 do not have an inter-process communication area used in common.

  As described with reference to FIG. 9, the OS 203 manages threads by the thread data structure 901. Similarly, the OS 203 may manage processes that are sets of threads. Furthermore, the OS 203 may generate an inter-process communication area list that is not used for each process.

  FIG. 10 is a flowchart showing line fetch processing by the snoop control unit # 0. In FIG. 10, the snoop-compatible cache # 0 receives a read request from the CPU # 0 to the cache, and the cache requested by the CPU # 0 does not exist in the cache line storage unit # 0, and the line by the snoop control unit # 0 It is assumed that fetch processing has occurred. Snoop control units # 1 to # 3 other than the snoop control unit # 0 also perform line fetch processing in response to a read request from the corresponding CPU.

  The snoop control unit # 0 determines a new line fetch (step S1001). After the determination, the snoop control unit # 0 sends a read request for one line to the bus 110 from the master I / F # 0 as a broadcast (step S1002).

  The snoop control unit # 1 to snoop control unit # 3 that has received the read request starts a response to the line fetch process. In addition, since all of the snoop control unit # 1 to the snoop control unit # 3 perform the same processing, in the following description, the description will be given by the snoop control unit # 1 for simplification of description. The snoop control unit # 1 searches the tag area of the cache line storage unit # 1 for a line having an address that matches the requested address (step S1003). When searching for a line having a matching address, the line is searched from a line other than the I state which is an invalid state.

  After the search, the snoop control unit # 1 determines whether there is a line having a matching address (step S1004). When there is no line having the matching address (step S1004: No), the snoop control unit # 1 ends the response of the line fetch process. If there is a line having a matching address (step S1004: Yes), the snoop control unit # 1 issues a block command to the transmission source of the read request, that is, the snoop control unit # 0 in the example of FIG. 10 (step S1005). ).

  After the issuance, the snoop control unit # 1 determines whether the matched line is in the M state (step S1006). When the state of the matched line is the M state (step S1006: Yes), the snoop control unit # 1 writes the matched line data in the shared memory 202 (step S1007). After completion of writing or when the state of the searched line is other than the M state (step S1006: No), the snoop control unit # 1 changes the line to the S state (step S1008), and returns a response of the line fetch process. finish.

  The snoop control unit # 0 determines whether any of the snoop control unit # 1 to the snoop control unit # 3 is blocked by the block command (step S1009). If not blocked (step S1009: No), the snoop control unit # 0 stores the read line in the cache line storage unit # 0 in the E state (step S1010), and ends the line fetch process. When blocked (step S1009: Yes), the snoop control unit # 0 retransmits the read request for one line to the bus 110 (step S1011). After the retransmission, the snoop control unit # 0 stores the read line in the cache line storage unit # 0 in the S state (step S1012), and ends the line fetch process.

  FIG. 11 is a flowchart showing a write process to a line by the snoop control unit # 0. In FIG. 11, it is assumed that the snoop-compatible cache # 0 receives a write request to the cache from the CPU # 0. The snoop control unit # 1 to the snoop control unit # 3 other than the snoop control unit # 0 are also subjected to the write process in response to a write request from the corresponding CPU.

  The snoop control unit # 0 determines writing to the line (step S1101). After the determination, the snoop control unit # 0 determines whether the line to be written is in the S state (step S1102). When it is in the S state (step S1102: Yes), the snoop control unit # 0 issues an invalidation request to the snoop control unit # 1 to the snoop control unit # 3 by broadcast (step S1103). After sending the invalidation request or when not in the S state (step S1102: No), the snoop control unit # 0 changes the line to be written to the M state (step S1104). After the change, the snoop control unit # 0 writes data to the line to be written (step S1105), and ends the line writing process.

  The snoop control unit # 1 to the snoop control unit # 3 that has received the invalidation request in the process of step S1103 starts a response to the line writing process. In addition, since all of the snoop control unit # 1 to the snoop control unit # 3 perform the same processing, in the following description, the description will be given by the snoop control unit # 1 for simplification of description.

  The snoop control unit # 1 searches the tag area of the cache line storage unit # 1 for a line having an address that matches the requested address (step S1106). When searching for a line having a matching address, the line is searched from a line other than the I state which is an invalid state. After the search, the snoop control unit # 1 determines whether there is a line having a matching address (step S1107). If there is a line having a matching address (step S1107: Yes), the snoop control unit # 1 invalidates the line by setting it to the I state (step S1108). After the line is invalidated or when there is no line having a matching address (step S1107: No), the snoop control unit # 1 ends the response to the writing process to the line.

  FIG. 12 is a flowchart showing the coherency control process. The coherency control process is executed by any of the CPUs # 0 to # 3. In FIG. 12, a description will be given of a case where the CPU # 0 executes the coherency control process.

  CPU # 0 detects acceptance of a reschedule request (step S1201). The coherency control process is executed each time a thread is rescheduled. Therefore, the coherency control process may be inside the scheduler 502 or may be outside the scheduler 502 and can be notified. CPU # 0 determines a thread to be assigned to the target CPU for rescheduling (step S1202). The CPU to be rescheduled may be CPU # 0, or may be another CPU for which a rescheduling request is accepted when the scheduler 502 is also performing scheduling processing for another CPU. .

  After the determination, CPU # 0 determines whether the assignment prohibition flag is set (step S1203). When the allocation prohibition flag is set (step S1203: Yes), the CPU # 0 executes step S1203 again after a predetermined time. When the allocation prohibition flag is not set (step S1203: No), the CPU # 0 sets an allocation prohibition flag to a CPU other than the target CPU (step S1204).

  After setting the allocation prohibition flag, the CPU # 0 executes a coherency target CPU determination process (step S1205). Details of the coherency target CPU determination process will be described later with reference to FIG. After the execution, the CPU # 0 determines whether there is a CPU that has changed from the state where the coherency is being executed to the stop by the coherency target CPU determination process (step S1206). If there is a CPU that has changed to stop (step S1206: Yes), the CPU # 0 flushes the cache of the target CPU (step S1207). The flash is an operation in which, for example, the snoop control unit writes a line in which data is updated, such as the M state, to the shared memory 202 and sets all the lines including the M state to the I state.

  If there is no CPU changed to stop after the flush (step S1206: No), the CPU # 0 controls the cache coherency mechanism 201 (step S1208). As a specific control content, it is assumed that the target CPU is CPU # 0 and it is determined in step S1205 that execution of coherency between CPU # 0 and CPU # 1 is stopped.

  In this case, the CPU # 0 instructs the snoop compatible cache # 0 to remove the snoop compatible cache # 1 from the broadcast destination. Specifically, the CPU # 0 changes the setting register of the snoop corresponding cache # 0 to remove the snoop corresponding cache # 1 from the broadcast destination.

  Similarly, the CPU # 0 instructs the snoop compatible cache # 1 to remove the snoop compatible cache # 0 from the broadcast destination. By excluding from the broadcast destination, the transmission amount of broadcast performed in the processing of step S1002 and step S1103 can be reduced, and the traffic amount in the bus 110 can be reduced. In addition, the snoop-compatible cache removed from the broadcast destination does not need to perform each response process, so the processing amount can be reduced.

  After control, CPU # 0 cancels the allocation prohibition flag of the other CPU (step S1209), and allocates the determined thread to the target CPU (step S1210). After the allocation, CPU # 0 ends the coherency control process.

  FIG. 13 is a flowchart showing a coherency target CPU determination process. The coherency target CPU determination process is also executed by any of the CPUs # 0 to # 3 as in the coherency control process. In FIG. 13, as in FIG. 12, the case where the CPU # 0 performs the coherency target CPU determination process will be described. In the coherency target CPU determination process, the target CPU and a target thread that is a thread scheduled to be allocated are acquired as an argument from the coherency control process.

  CPU # 0 selects an unselected CPU from CPUs other than the target CPU (step S1301). After selection, the CPU # 0 determines whether the process to which the target thread belongs and the process to which the thread being executed by the selected CPU belongs are the same (step S1302).

  If they are the same (step S1302: Yes), the CPU # 0 determines whether the thread being executed by the selected CPU is included in the thread ID list field that does not share the data of the target thread (step S1303). . If included (step S1303: Yes), the CPU # 0 determines to stop coherency between the target CPU and the selected CPU (step S1304). If not included (step S1303: No), the CPU # 0 determines execution of coherency between the target CPU and the selected CPU (step S1305).

  If the process to which the target thread belongs and the process to which the thread being executed by the selected CPU belongs are not the same (step S1302: No), the CPU # 0 determines whether the processes use the same inter-process communication area. (Step S1306). When using the same inter-process communication area (step S1306: Yes), the CPU # 0 determines whether the target thread and the thread being executed by the selected CPU use the same inter-process communication area (step S1306: Yes). S1307).

  When using the same inter-process communication area (step S1307: Yes), the CPU # 0 determines execution of coherency between the target CPU and the selected CPU (step S1308). When the same inter-process communication area is not used (step S1306: No, step S1307: No), the CPU # 0 determines to stop coherency between the target CPU and the selected CPU (step S1309).

  After any of steps S1304, S1305, S1308, and S1309, CPU # 0 determines whether there is an unselected CPU from other CPUs than the target CPU (step S1310). If there is an unselected CPU (step S1310: Yes), the CPU # 0 proceeds to the process of step S1301. If there is no unselected CPU (step S1310: No), the CPU # 0 ends the coherency target CPU determination process.

  As described above, according to the multi-core processor system, the cache coherency control method, and the cache coherency control program, the areas accessed by the first and second threads being executed in the first and second cores are different. Judging. When it is determined that the areas are different, the multi-core processor system stops coherency between the first cache memory corresponding to the first core and the second cache memory corresponding to the second core. Since the accessed areas are different, shared data inconsistency does not occur even if coherency is stopped. Therefore, the multi-core processor system can reduce power consumption by reducing the traffic amount of the cache coherency mechanism, and can prevent a delay due to an increase in the traffic amount.

  The multi-core processor system may stop coherency when it is determined that the first and second threads belong to the same process and there is no shared data to be accessed in common. Thereby, even if two cores are executing the thread of the same process, the multi-core processor system can reduce the traffic amount of the cache coherency mechanism, and can reduce power consumption. In an embedded device typified by a mobile phone, there are few cases where a plurality of processes are activated simultaneously, and there are many opportunities to execute a plurality of threads belonging to the same process. Therefore, this embodiment is particularly effective.

Furthermore, an embedded OS installed in an embedded device has no concept of a process, and there is an OS in which all threads (tasks) access the same memory space. For example, μITRON described in Reference Document 1 below.
(Reference 1: Suitable place for embedded OS << Windows (registered trademark) Embedded CE Edition (1)}-First, understand the difference between μITRON and Windows (registered trademark) Embedded CE | Tech Village / CQ Publishing Co., Ltd .: [ online], [searched on May 13, 2010], Internet <URL: http: // www.

  In the OS as described above, since all threads can access the entire memory space, even if the conventional method is applied, the state is always in a state where coherency is executed. However, the multi-core processor system 100 according to the present embodiment can reduce the traffic amount and the processing amount of the cache coherency mechanism when it is determined that there is no shared data to be accessed in common, which is particularly effective. is there.

  In addition, the multi-core processor system stops coherency when the first and second threads belong to different processes and there is no interprocess communication area commonly used by the first and second threads. May be. As a result, the multi-core processor system reduces the traffic volume and processing volume by stopping the coherency except when the coherency should be executed even in different processes, thereby reducing the power consumption and increasing the traffic volume. Can prevent delay.

  The multi-core processor system may determine whether there is an interprocess communication area in which the processes to which the first and second threads belong are used. When determining whether there is an area of interprocess communication that is commonly used by the first and second threads, the multi-core processor system starts with at least one of the first and second threads being a process. A state where the inter-communication area is not used may be determined.

  The determination of whether or not the interprocess communication area is used has a smaller processing amount than the determination of whether or not the interprocess communication area used in common exists. Therefore, it is determined first whether or not the first and second threads are using the interprocess communication area. If both areas are used, it is determined whether there is an area that is commonly used. The total processing amount can be reduced by the processing order of “Yes”.

  In addition, when the multi-core processor system stops coherency execution between the first cache memory and the second cache memory, the multi-core processor system erases the shared data stored in the first cache memory from the first cache memory. Also good. As a result, the multi-core processor system can maintain the consistency of the shared memory even if the execution of coherency is stopped.

  Note that the cache coherency control method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The cache coherency control program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The cache coherency control program may be distributed via a network such as the Internet.

# 0, # 1 CPU, Snoop-compatible cache A-1, A-2 Thread 100 Multi-core processor system 110 Bus 501 Dependent information 502 Scheduler 503 Execution unit 504 Detection unit 505 Identification unit 506 Determination unit 507 Control unit

Claims (3)

With multiple cores,
A multi-core processor system having a plurality of cache memories accessed by each of the plurality of cores, wherein any one of the plurality of cores is:
When a first thread executed by a first core among the plurality of cores is detected, a second thread being executed by a second core other than the first core among the plurality of cores is detected. A first cache memory corresponding to the first core among the plurality of cache memories when there is no shared data to be detected and accessed in common during execution of the first thread and the second thread And coherency processing with the second cache memory corresponding to the second core,
A multi-core processor system characterized by that. A cache coherency control method for a multi-core processor system having a plurality of cache memories accessed by each of a plurality of cores, wherein any one of the plurality of cores includes:
When a first thread executed by a first core among the plurality of cores is detected, a second thread being executed by a second core other than the first core among the plurality of cores is detected. A first cache memory corresponding to the first core among the plurality of cache memories when there is no shared data to be detected and accessed in common during execution of the first thread and the second thread And coherency processing with the second cache memory corresponding to the second core,
A cache coherency control method characterized by executing processing. A cache coherency control program for a multi-core processor system having a plurality of cache memories accessed by each of a plurality of cores, wherein any one of the plurality of cores includes:
When a first thread executed by a first core among the plurality of cores is detected, a second thread being executed by a second core other than the first core among the plurality of cores is detected. A first cache memory corresponding to the first core among the plurality of cache memories when there is no shared data to be detected and accessed in common during execution of the first thread and the second thread And coherency processing with the second cache memory corresponding to the second core,
A cache coherency control program characterized by causing processing to be executed.

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