JP2013534712A - Plasma doping apparatus, plasma doping method, semiconductor element manufacturing method, and semiconductor element - Google Patents

Abstract

Disclosed is a plasma doping apparatus capable of reducing damage to a substrate to be processed and performing uniform processing in doping.
A plasma doping apparatus includes a processing vessel for injecting a dopant into a substrate to be processed therein, a gas supply unit for supplying a doping gas and an inert gas for plasma excitation into the processing vessel, A biasing power is applied to the support base 34, which is disposed in the processing container 32 and supports the substrate W to be processed thereon, a plasma generation mechanism 39 that generates plasma in the processing container 32 using microwaves, and the support base 34. A high-frequency power source 58 that can be supplied and a control unit 28 that controls the plasma doping apparatus 31 are provided. Here, the control unit 28 controls the bias power supplied from the high-frequency power source 58 so that the ion energy of the dopant is less than 100 eV.
[Selection] Figure 2

Description

  The present invention relates to a plasma doping apparatus, a plasma doping method, a method for manufacturing a semiconductor element, and a semiconductor element, and in particular, a plasma doping apparatus, a plasma doping method, and a semiconductor element used for manufacturing a semiconductor element. The present invention relates to a method and a semiconductor device.

  Semiconductor elements such as LSI (Large Scale Integrated Circuit) and MOS (Metal Oxide Semiconductor) transistors are used for doping, etching, CVD (Chemical Vapor Deposition), sputtering, etc. on a semiconductor substrate (wafer) to be processed. It is manufactured by applying.

  Here, a technique related to a plasma doping apparatus that performs doping using a plasma in relation to ion implantation for doping a substrate to be processed, that is, doping, is disclosed in Japanese Patent Laid-Open No. 2008-300687 (Patent Document 1). Yes. According to Patent Document 1, a predetermined dopant is doped using plasma generated using microwaves.

JP 2008-300687 A

  Conventionally, an ion implantation apparatus has been used for implanting a dopant into a substrate to be processed from the viewpoint of ease of controlling a dose amount. However, such an ion implantation apparatus has the following problems.

  The conventional ion implantation apparatus is a system in which ion clusters are sequentially collided with a substrate to be processed as a doping target, and ion implantation is performed. However, since the ion energy is high, damage to the crystal structure during doping is likely to occur. The crystal structure on the doped side has been made largely amorphous. In such an amorphized layer, recovery can be performed in an annealing process that is a process after doping, but if the formation region of the amorphous layer is large or deep, this annealing process also takes a long time. And processing at high temperatures is required.

  In addition, there is a risk that contaminants such as unintended metal ions may be doped during doping. That is, ions having high energy collide with not only the substrate to be processed but also members constituting the inside of the processing apparatus, and unintentional contaminants such as metal ions are generated therefrom. Such unintentional contaminants such as metal ions are deposited in a region on the substrate to be processed that has not been doped. There has been a problem that these contaminants are implanted into the substrate to be processed together with the dopant during ion implantation. In particular, in recent years, from the viewpoint of reducing the junction breakdown voltage and junction leakage at the PN junction required in a 30 nm transistor, the damage to the substrate to be processed at the ultra-shallow junction (Xj) is reduced, and the contamination of the doped contaminants Reduction is required. Further, in the ion implantation apparatus, isotropic ion implantation is difficult because doping is performed by colliding ion clusters from above the substrate to be processed. For example, with respect to the substrate to be processed having a concave portion with a high aspect ratio, the upper side layer and the side side layer are uniformly and, more specifically, doped in substantially the same amount to a desired doping depth. Is difficult to do. That is, there is a problem that isotropic doping is difficult.

  Here, it is conceivable to perform doping using plasma generated by ICP (Inductively-coupled Plasma) or the like. However, even with ICP plasma, plasma doping is performed in a state where the electron temperature is relatively high, and the generated ion energy is large, so that plasma damage to the substrate to be processed is large. Therefore, further reduction of damage is required. Furthermore, in recent years, improvement in processing uniformity at the time of doping is also strongly demanded, which is a problem when performing plasma doping using ICP or the like.

  An object of the present invention is to provide a plasma doping apparatus capable of reducing damage to a substrate to be processed and reducing contaminants to be doped.

  Another object of the present invention is to provide a plasma doping method capable of reducing damage to a substrate to be processed and reducing contaminants to be doped.

  Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing damage to a substrate to be processed and reducing contaminants to be doped.

  Still another object of the present invention is to provide a semiconductor device capable of reducing damage to a substrate to be processed and reducing contaminants to be doped.

  A plasma doping apparatus according to the present invention is a plasma doping apparatus that performs doping by injecting a dopant into a substrate to be processed using plasma, and a processing container for injecting the dopant into the substrate to be processed therein, and a processing container A gas supply unit for supplying a doping gas and an inert gas for plasma excitation therein, a support base disposed in the processing container and supporting a substrate to be processed thereon, and a plasma in the processing container using microwaves A plasma generating mechanism for generating the pressure, a pressure adjusting mechanism for adjusting the pressure in the processing container, a bias power supply mechanism capable of supplying bias power to the support base, and a controller for controlling the plasma doping apparatus. The control unit controls the bias power supplied by the bias power supply mechanism so that the ion energy of the dopant is less than 100 eV.

  Thus, when doping is performed using plasma, plasma is generated using microwaves, and the bias power is controlled so that the ion energy of the dopant during plasma doping is less than 100 eV. At the same time, plasma damage to the substrate to be processed can be reduced, and the amorphous structure of the crystal structure at the time of doping can be suppressed. By suppressing the amorphization, the surface state of the substrate to be processed can be improved, and the annealing process for recovering the amorphous layer formed later can be omitted or simplified. Moreover, according to such plasma doping using microwaves, the entire surface of the substrate to be processed can be processed almost uniformly, and the surface of the substrate to be processed by supplying an inert gas for plasma excitation during doping. Since the state can be cleaned, it is possible to reduce the risk of doping with contaminants such as metal ions that become contaminants or ions as unintended impurities. Furthermore, since there is no deposition of such contaminants, energy loss due to the deposit is small, and deeper doping can be performed with low energy. In addition, since it can be uniformly doped from the surface layer to a desired depth without causing the shape of the substrate to be processed, even a substrate to be processed having a recess with a high aspect ratio can be processed uniformly. It can be performed. That is, isotropic doping can be performed. Thus, the layer doped in this way has very good properties. As described above, such a plasma doping apparatus can reduce damage to the substrate to be processed and reduce contaminants to be doped.

  In another aspect of the present invention, a plasma doping method is a plasma doping method that performs doping by injecting a dopant into a substrate to be processed using plasma, the plasma doping method being performed on a support table disposed in a processing vessel. A substrate is supported, a doping gas and an inert gas for plasma excitation are supplied into the processing container, plasma is generated in the processing container using microwaves, and the ion energy of the dopant is less than 100 eV. Bias power is supplied to inject dopant into the substrate to be processed.

  In still another aspect of the present invention, a plasma doping method is a plasma doping method for performing doping by injecting a dopant into a substrate to be processed using plasma, the plasma doping method being performed on a support base disposed in a processing container. A processing substrate is supported, a doping gas and an inert gas for plasma excitation are supplied into the processing container, plasma is generated in the processing container using microwaves, and a bias power is not supplied to the support base. A dopant is implanted into the processing substrate.

  In still another aspect of the present invention, a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device manufactured by injecting a dopant into a substrate to be processed using plasma, and a support disposed in a processing container. A substrate to be processed is supported on a stage, a doping gas and an inert gas for plasma excitation are supplied into the processing container, plasma is generated in the processing container using microwaves, and the ion energy of the dopant is less than 100 eV. A step of supplying a bias power to the support base and implanting a dopant into the substrate to be processed is included.

  In still another aspect of the present invention, a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device manufactured by injecting a dopant into a substrate to be processed using plasma, and a support disposed in a processing container. A substrate to be processed is supported on a table, a doping gas and an inert gas for plasma excitation are supplied into the processing container, plasma is generated in the processing container using microwaves, and bias power is supplied to the supporting table. And a step of implanting a dopant into the substrate to be processed.

  In still another aspect of the present invention, the semiconductor element is a semiconductor element manufactured by injecting a dopant into a substrate to be processed using plasma, and the substrate to be processed is placed on a support table disposed in the processing container. A doping gas and an inert gas for plasma excitation are supplied into the processing vessel, plasma is generated in the processing vessel using microwaves, and a bias is applied to the support so that the ion energy of the dopant is less than 100 eV. It is manufactured by supplying electric power and injecting a dopant into a substrate to be processed.

  In still another aspect of the present invention, the semiconductor element is a semiconductor element manufactured by injecting a dopant into a substrate to be processed using plasma, and the substrate to be processed is placed on a support table disposed in the processing container. Supporting the substrate, supplying a doping gas and an inert gas for plasma excitation into the processing container, generating a plasma in the processing container using microwaves, and supplying a bias power to the substrate to be processed without supplying a bias power to the support table Manufactured by implanting dopant.

  According to such a plasma doping apparatus, a plasma doping method, and a semiconductor device manufacturing method, when doping is performed using plasma, plasma is generated using microwaves, and the ion energy of the dopant during plasma doping is set to 100 eV. Since the bias power is controlled to be less than the value, plasma damage to the substrate to be processed at the time of plasma doping can be reduced, and the amorphous structure of the crystal structure at the time of doping can be suppressed. By suppressing the amorphization, the surface state of the substrate to be processed can be improved, and the annealing process for recovering the amorphous layer formed later can be omitted or simplified. Moreover, according to such plasma doping using microwaves, the entire surface of the substrate to be processed can be processed almost uniformly, and the surface of the substrate to be processed by supplying an inert gas for plasma excitation during doping. Since the state can be cleaned, it is possible to reduce the risk of doping with contaminants such as metal ions that become contaminants or ions as unintended impurities. Furthermore, since there is no deposition of such contaminants, energy loss due to the deposit is small, and deeper doping can be performed with low energy. In addition, since it can be uniformly doped from the surface layer to a desired depth without causing the shape of the substrate to be processed, even a substrate to be processed having a recess with a high aspect ratio can be processed uniformly. It can be performed. That is, isotropic doping can be performed. Thus, the layer doped in this way has very good properties. As described above, damage to the substrate to be processed can be reduced and contaminants to be doped can be reduced.

  Further, in such a semiconductor element, damage to a substrate to be processed is reduced, and a contaminant to be doped is reduced.

It is a schematic sectional drawing which shows a part of MOS type semiconductor element. It is a schematic sectional drawing which shows the principal part of the plasma doping apparatus used for the manufacturing method of the semiconductor element concerning one Embodiment of this invention. It is the figure which looked at the slot antenna board contained in the plasma doping apparatus shown in FIG. 2 from the plate | board thickness direction. It is a graph which shows the relationship between the distance from the lower surface of a dielectric material window, and the electron temperature of plasma. It is a graph which shows the relationship between the distance from the lower surface of a dielectric material window, and the electron density of plasma. It is a graph which shows the relationship between the electron temperature and electron density in ICP and RLSA plasma. It is the schematic of the silicon substrate before performing plasma doping. It is a schematic diagram of a silicon substrate in the state where plasma was generated. It is the schematic of the silicon substrate which performed plasma doping. It is the schematic which shows the state which made the ion cluster collide with the silicon substrate in an ion implantation apparatus. It is the schematic of the silicon substrate which doped in the ion implantation apparatus. It is the schematic in the case where DC pulse bias is OFF in doping by ICP. FIG. 6 is a schematic diagram when a DC pulse bias is on in doping by ICP. It is a figure which shows the state which analyzed a part of to-be-processed substrate at the time of doping with P (phosphorus) with the plasma doping apparatus which concerns on this invention with the atom probe. It is a TEM photograph near the surface of the silicon substrate when the bias power is 0 W. It is a TEM photograph near the surface of the silicon substrate when the bias power is 100 W. It is a TEM photograph near the surface of the silicon substrate when the bias power is 200 W. It is a TEM photograph near the surface of a silicon substrate when bias power is 300W. It is a TEM photograph near the surface of a silicon substrate at the time of performing plasma doping by ICP. It is a TEM photograph near the surface of the silicon substrate when the bias power is 100 W and the bias frequency is 13.56 MHz. It is a TEM photograph near the surface of the silicon substrate when the bias power is 100 W and the bias frequency is 400 kHz. It is the schematic which shows the external appearance of FinFET (Field Effect Transistor). It is the schematic which shows the state which performs doping by an ion implantation apparatus in a FinFET structure. It is the schematic which shows the state which performs doping by plasma doping in a FinFET structure. In a FinFET structure, it is an SSRM (Scanning Spreading Resistance Microscopy) image diagram when performing plasma doping with a bias power of 0 W. FIG. In the FinFET structure, it is an SSRM image diagram when plasma doping is performed with a bias power of 100 W and a bias frequency of 400 kHz. In the FinFET structure, it is an SSRM image diagram when plasma doping is performed with a bias power of 100 W and a bias frequency of 13.56 MHz.

  Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of a semiconductor element according to an embodiment of the present invention will be described. FIG. 1 is a schematic sectional view showing a part of a MOS type semiconductor device according to an embodiment of the present invention. In the MOS type semiconductor device shown in FIG. 1, the conductive layer is indicated by hatching.

  According to FIG. 1, the MOS type semiconductor element 11 includes an element isolation region 13, a p-type well 14a, an n-type well 14b, a high-concentration n-type impurity diffusion region 15a, and a high-concentration p-type impurity diffusion on a silicon substrate 12. Region 15b, n-type impurity diffusion region 16a, p-type impurity diffusion region 16b, and gate oxide film 17 are formed. Either of the high-concentration n-type impurity diffusion regions 15a formed with the gate oxide film 17 interposed therebetween, or any of the high-concentration p-type impurity diffusion regions 15b formed with the gate oxide film 17 interposed therebetween One of them becomes a drain and the other becomes a source.

  In addition, a gate electrode 18 serving as a conductive layer is formed on the gate oxide film 17, and a gate sidewall 19 serving as an insulating film is formed on a side portion of the gate electrode 18. Furthermore, an insulating film 21 is formed on the silicon substrate 12 on which the gate electrode 18 and the like are formed. A contact hole 22 is formed in the insulating film 21 so as to be connected to the high-concentration n-type impurity diffusion region 15 a and the high-concentration p-type impurity diffusion region 15 b, and a buried electrode 23 is formed in the contact hole 22. Further, a metal wiring layer 24 serving as a conductive layer is formed thereon. Further, an interlayer insulating film (not shown) to be an insulating layer and a metal wiring layer to be a conductive layer are alternately formed, and finally a pad (not shown) to be a contact point with the outside is formed. Thus, the MOS type semiconductor element 11 is formed.

  The MOS type semiconductor device 11 according to an embodiment of the present invention is formed by implanting a dopant in a n-type impurity diffusion region 16a and a p-type impurity diffusion region 16b by a plasma doping apparatus described later, that is, doping. ing. Specifically, for example, in the n-type impurity diffusion region 16a, B2H6 gas is used as a doping gas, and B (boron: boron) is implanted as a dopant. In such a region, formation of an ultra-shallow junction, so-called shallow junction is required, and a reduction in junction breakdown voltage and junction leakage is required, but according to a plasma doping apparatus according to an embodiment of the present invention described later, It is possible to reduce damage to the substrate to be processed and reduce contaminants to be doped.

  Next, the configuration and operation of a plasma doping apparatus used in the method for manufacturing a semiconductor device according to one embodiment of the present invention will be described.

  FIG. 2 is a schematic cross-sectional view showing the main part of the plasma doping apparatus according to one embodiment of the present invention. FIG. 3 is a view of the slot antenna plate included in the plasma doping apparatus shown in FIG. 2 as viewed from below, that is, from the direction of arrow III in FIG. In FIG. 2, some of the members are not hatched for easy understanding.

  2 and 3, a plasma doping apparatus 31 includes a processing container 32 for performing plasma doping on the substrate W to be processed therein, a plasma excitation gas in the processing container 32, and a dopant base to be injected. A gas supply unit 33 for supplying a doping gas, a disk-like support base 34 for supporting the substrate W to be processed, and a plasma generating mechanism 39 for generating plasma in the processing chamber 32 using microwaves. And a control unit 28 that controls the operation of the entire plasma doping apparatus 31. The control unit 28 controls the entire plasma doping apparatus 31 such as the gas flow rate in the gas supply unit 33 and the pressure in the processing container 32.

  The processing container 32 includes a bottom portion 41 located on the lower side of the support base 34 and a side wall 42 extending upward from the outer periphery of the bottom portion 41. The side wall 42 is substantially cylindrical. An exhaust hole 43 for exhaust is provided in the bottom 41 of the processing container 32 so as to penetrate a part thereof. The upper side of the processing container 32 is open, and a lid 44 disposed on the upper side of the processing container 32, a dielectric window 36 described later, and a seal member interposed between the dielectric window 36 and the lid 44. The processing container 32 is configured to be hermetically sealed by an O-ring 45 as a sealing member.

  The gas supply unit 33 includes a first gas supply unit 46 that blows gas toward the center of the substrate to be processed W, and a second gas supply unit 47 that blows gas from the outside of the substrate to be processed W. The gas supply hole 30 for supplying gas in the first gas supply section 46 is more dielectric than the lower surface 48 of the dielectric window 36 which is the center in the radial direction of the dielectric window 36 and faces the support base 34. It is provided at a position retracted inward of the body window 36. The first gas supply unit 46 supplies an inert gas and a doping gas for plasma excitation while adjusting a flow rate and the like by a gas supply system 49 connected to the first gas supply unit 46. The second gas supply unit 47 is formed by providing a plurality of gas supply holes 50 for supplying an inert gas and a doping gas for plasma excitation in the processing container 32 in a part of the upper side of the side wall 42. Yes. The plurality of gas supply holes 50 are equally provided in the circumferential direction. The first gas supply unit 46 and the second gas supply unit 47 are supplied with the same type of inert gas and doping gas for plasma excitation from the same gas supply source. In addition, according to a request | requirement and the content of control, another gas can also be supplied from the 1st gas supply part 46 and the 2nd gas supply part 47, and those flow ratios etc. can also be adjusted.

  A high frequency power source 58 for RF (radio frequency) bias is electrically connected to the electrode in the support table 34 via the matching unit 59. The high frequency power supply 58 can output a high frequency of 13.56 MHz, for example, with a predetermined power (bias power). The matching unit 59 accommodates a matching unit for matching between the impedance on the high frequency power source 58 side and the impedance on the load side such as an electrode, plasma, and the processing vessel 32, and the matching unit is included in this matching unit. A blocking capacitor for self-bias generation is included.

  The support base 34 can support the substrate W to be processed thereon by an electrostatic chuck (not shown). The support table 34 includes a heater (not shown) for heating and the like, and can be set to a desired temperature by a temperature adjustment mechanism 29 provided in the support table 34. The support base 34 is supported by an insulating cylindrical support 51 that extends vertically upward from the lower side of the bottom 41. The exhaust hole 43 described above is provided so as to penetrate a part of the bottom 41 of the processing container 32 along the outer periphery of the cylindrical support part 51. An exhaust device (not shown) is connected to the lower side of the annular exhaust hole 43 via an exhaust pipe (not shown). The exhaust device has a vacuum pump such as a turbo molecular pump. The inside of the processing container 32 can be depressurized to a predetermined pressure by the exhaust device.

  The plasma generation mechanism 39 is provided outside the processing vessel 32, and is disposed at a position facing the microwave generator 35 for generating plasma excitation microwaves and the support base 34, and is generated by the microwave generator 35. A dielectric window 36 for introducing the microwaves into the processing container 32 and a plurality of slot holes 40 are provided. The dielectric window 36 is disposed above the dielectric window 36 and radiates the microwaves to the dielectric window 36. It includes a slot antenna plate 37 and a dielectric member 38 disposed above the slot antenna plate 37 and propagating in the radial direction a microwave introduced by a coaxial waveguide 56 described later.

  A microwave generator 35 having a matching mechanism 53 is connected to an upper portion of a coaxial waveguide 56 for introducing a microwave through a mode converter 54 and a waveguide 55. For example, a TE mode microwave generated by the microwave generator 35 passes through the waveguide 55, is converted to a TEM mode by the mode converter 54, and propagates through the coaxial waveguide 56. For example, 2.45 GHz is selected as the frequency of the microwave generated by the microwave generator 35.

  The dielectric window 36 has a substantially disk shape and is made of a dielectric. A part of the lower surface 48 of the dielectric window 36 is provided with an annular recess 57 that is recessed in a tapered shape for facilitating generation of a standing wave by the introduced microwave. Due to the concave portion 57, microwave plasma can be efficiently generated on the lower side of the dielectric window 36. Specific materials for the dielectric window 36 include quartz and alumina.

  The slot antenna plate 37 has a thin plate shape and a disk shape. As shown in FIG. 3, the plurality of slot-shaped slot holes 40 are provided so that a pair of slot holes 40 are orthogonal to each other in a substantially letter C shape, and the pair of slot holes 40 is circumferential. Are provided at predetermined intervals. Also in the radial direction, a plurality of pairs of slot holes 40 are provided at predetermined intervals.

  The microwave generated by the microwave generator 35 is propagated to the dielectric member 38 through the coaxial waveguide 56. The microwave has a circulation path 29 for circulating a refrigerant and the like inside thereof, and the inside of the dielectric member 38 sandwiched between the cooling jacket 52 and the slot antenna plate 37 for adjusting the temperature of the dielectric member 38 and the like is arranged in the radial direction. It spreads radially outward and is radiated to the dielectric window 36 from a plurality of slot holes 40 provided in the slot antenna plate 37. The microwave transmitted through the dielectric window 36 generates an electric field immediately below the dielectric window 36 and generates plasma in the processing chamber 32. That is, microwave plasma subjected to processing in the plasma doping apparatus 31 is radiated from a radial line slot antenna (RLSA) including the cooling jacket 52, the slot antenna plate 37, and the dielectric member 38 having the above-described configuration. Is generated in the processing container 32 by the microwave. In the following description, the plasma generated in this way may be referred to as RLSA plasma.

  FIG. 4 is a graph showing the relationship between the distance from the lower surface 48 of the dielectric window 36 in the processing chamber 32 and the plasma electron temperature when plasma is generated in the plasma doping apparatus 31. FIG. 5 is a graph showing the relationship between the distance from the lower surface 48 of the dielectric window 36 in the processing chamber 32 and the electron density of the plasma when plasma is generated in the plasma doping apparatus 31.

Referring to FIGS. 4 and 5, the region immediately below dielectric window 36, specifically, region 26 up to approximately 10 mm indicated by the alternate long and short dash line is called a so-called plasma generation region. In this region 26, the electron temperature is high and the electron density is higher than 1 × 10 ¹² cm ⁻³ . On the other hand, a region 27 exceeding 10 mm indicated by a two-dot chain line is called a plasma diffusion region. In this region 27, the electron temperature is about 1.0 to 1.3 eV, lower than at least 1.5 eV, and the electron density is higher than about 1 × 10 ¹² cm ⁻³ , and at least higher than 1 × 10 ¹¹ cm ⁻³ . Plasma doping for the substrate W to be processed, which will be described later, is performed in such a plasma diffusion region, for example. That is, in the plasma doping process, microwave plasma having a plasma electron temperature lower than 1.5 eV and a plasma electron density higher than 1 × 10 ¹² cm ⁻³ is used in the vicinity of the surface of the substrate W to be processed. Is desirable.

For reference, the relationship between the electron temperature and the electron density in ICP will be described. FIG. 6 is a graph showing a relationship between electron temperature and electron density in microwave plasma using ICP and the above-described RLSA, so-called RLSA plasma. In FIG. 6, the vertical axis indicates the electron temperature (eV), and the horizontal axis indicates the electron density (/ cm ³ ). In FIG. 6, the black triangle mark indicates the case of ICP in which the pressure in the processing container is 20 mTorr, the white triangle mark indicates the case of ICP in which the pressure in the processing container is 50 mTorr, and the black circle mark indicates the treatment The case of RLSA plasma in which the pressure in the vessel is 20 mTorr is shown, and the white circle indicates the case of RLSA plasma in which the pressure in the processing vessel is 50 mTorr.

  Referring to FIG. 6, in the plasma doping process, in order to realize a high electron density and a low electron temperature, it is preferable that the data is close to the lower right side of the graph. Regarding this, the following can be considered. This is because the high electron density state also means a high ion density, and the number of dopants to be doped increases, so that doping is efficient, that is, more dopants can be implanted in a short time. In addition, since the high electron density state works in the direction of complete dissociation of the doping gas, it is more suitable than a dopant suitable for doping, that is, a dopant that is completely decomposed into atoms, specifically, for example, a PH molecule. This is because a state in which more P atoms can be generated can be obtained. In addition, in a low electron density state, low damage to the substrate to be processed in plasma doping can be achieved.

  In the case of ICP, when the pressure is high, the plasma uniformity is very poor due to the plasma generation mechanism. In addition, since the collision between the electrons and the doping gas increases, the density decreases. That is, in the case of ICP, it is extremely difficult to form a high-density plasma state at a high pressure. Therefore, in the case of ICP, processing is generally performed at a very low pressure of several mTorr, which is not preferable from the viewpoint of the process.

  On the other hand, according to the present invention, higher electron density and lower electron temperature can be realized in RLSA plasma in which the pressure in the processing vessel is 50 mTorr or more. That is, according to the RLSA plasma in which the pressure in the processing container is increased, plasma processing can be performed at a relatively low electron temperature and a relatively high electron density.

  The plasma doping apparatus 31 having the above-described configuration can also be applied as a plasma etching apparatus and a plasma CVD apparatus. That is, for example, the etching of the substrate W to be processed can be performed by supplying an etching gas and a gas for plasma excitation from the gas supply unit and setting the conditions to be suitable for the etching.

  Next, a method for manufacturing a semiconductor element manufactured by implanting a dopant into a substrate to be processed using the plasma doping apparatus 31 described above will be described.

  With reference to FIGS. 1 to 6 and FIGS. 7 to 9 to be described later, first, a substrate W to be processed serving as a base of a semiconductor element is supported by an electrostatic chuck on a support base 34 disposed in the processing container 32. Let Here, an extremely thin natural oxide film is formed on the surface of a silicon substrate as a substrate to be processed. On this natural oxide film, contaminants such as CH4, CO2, and H2O are adsorbed. This state is shown using FIG. FIG. 7 is a schematic cross-sectional view showing a cross section in which the contaminant 63 is adsorbed to the natural oxide film 62 formed on the surface of the silicon substrate 61 as the substrate to be processed. Note that the thickness of the natural oxide film 62 is approximately less than 1 nm.

  Next, an inert gas such as He gas, Ar gas, Xe gas, or Kr gas is supplied from the gas supply unit 33 as a plasma excitation gas. Here, the bias power supplied by the bias power supply mechanism is set so that the ion energy of the dopant is less than 100 eV. Further, it is performed while controlling the pressure in the processing container 32 so that the pressure in the processing container 32 becomes 50 mTorr. Further, the temperature of the silicon substrate 61 supported on the support table 34 is set to 400 ° C. using the temperature adjustment mechanism 29 provided in the support table 34. That is, as will be described later, the substrate to be processed is heated to a temperature at which molecules or atoms of the doping gas decomposed selectively by plasma are adsorbed on the surface of the substrate to be doped. In such a state, microwave plasma is generated in the processing container 32.

  FIG. 8 is a schematic view showing a state in which the microwave plasma 65 is generated. In this case, the natural oxide film 62 formed on the surface of the silicon substrate 61 and adsorbed with the contaminant 63 is removed by the generated microwave plasma 65, and becomes a clean surface 64 of the silicon substrate 61. In this case, cleaning such as removal of contaminants can be performed by supplying an inert gas before generating plasma.

Next, a doping gas is supplied into the processing container 32 to perform plasma doping. FIG. 9 is a schematic view showing a state in which a doping gas is supplied. The doping gas is supplied using the gas supply unit 33. In this case, the doping gas is supplied so as to be mixed with an inert gas for plasma excitation. As doping species, B (boron), P (phosphorus), As (arsenic), C (carbon), N (nitrogen), F (fluorine), Ge (germanium), Si (silicon), BF ₂ ( Boron fluoride) and the like. Gas species for doping such a doping species include gases such as B ₂ H ₆ , PH ₃ , AsH ₃ , GeH ₄ , CH ₄ , NH ₃ , NF ₃ , N ₂ , HF, and SiH _4. is there. That is, the doping gas supplied from the gas supply unit 33 is selected from the group consisting of B ₂ H ₆ , PH ₃ , AsH ₃ , GeH ₄ , CH ₄ , NH ₃ , NF ₃ , N ₂ , HF, and SiH _4. Containing at least one kind of gas.

In this case, first, the dopant 66 supplied by the doping gas is first adsorbed near the surface 64 of the silicon substrate 61 as shown in FIG. In this case, the surface 64 of the silicon substrate 61 is cleaned in advance by the microwave plasma 65 made of an inert gas, and therefore adsorbs with almost no adsorption of the contaminant 63. At this time, if the temperature of the substrate to be processed is heated to, for example, about 400 ° C., a contaminant such as CH ₄ , CO ₂ , and H ₂ O can be hardly adsorbed.

  Then, ions are accelerated in a plasma sheath portion formed between the microwave plasma 65 and the silicon substrate 61, and the dopant diffuses in the interior by energy colliding with molecules or atoms adsorbed on the surface. In this way, plasma doping with microwave plasma is performed. In this way, plasma doping is performed to obtain a semiconductor device including a silicon substrate according to an embodiment of the present invention.

  As described above, when doping is performed using plasma, plasma is generated using microwaves, and the ion energy of the dopant during plasma doping is controlled to be less than 100 eV. Plasma damage to the processing substrate can be reduced, and the amorphous structure of the crystal structure at the time of doping can be suppressed. Therefore, the annealing process for recovering the formed amorphous layer required after doping can be omitted or simplified. In addition, the entire surface of the substrate to be processed can be processed almost uniformly, and the surface state of the substrate to be processed can be cleaned by supplying an inert gas for plasma excitation during doping. The risk of doping with contaminants such as ions or ions as unintended impurities can be reduced. In addition, since it can be uniformly doped from the surface layer to a desired depth without causing the shape of the substrate to be processed, even a substrate to be processed having a recess with a high aspect ratio can be processed uniformly. It can be performed. That is, isotropic doping can be performed. Thus, the layer doped in this way has very good properties.

  Moreover, since the pressure in the processing container 32 is 50 mTorr, plasma processing can be performed at a higher electron density and a lower electron temperature in the generated RLSA plasma. Therefore, plasma damage can be greatly reduced.

In this case, since the temperature of the silicon substrate 61 supported on the support base 34 is set to 400 ° C., the surface 64 of the silicon substrate 61 is not adsorbed with contaminants that are relatively easily adsorbed at a low temperature, and the doping gas is positively applied. Can be absorbed. Specifically, it is possible to make it difficult to adsorb contaminants such as CH ₄ , CO ₂ , and H ₂ O. Therefore, ion implantation of contaminants can be significantly reduced. Further, as described above, the energy loss at the time of implantation due to the accumulation of contaminants can be greatly reduced.

This will be described in more detail as follows. For example, when plasma doping is performed using a mixed gas of PH ₃ gas and He gas, radical species of P, PH, PH ₂ , PH ₃ , H, H ₂ , and He are generated by the plasma. Here, a gas component adsorbed on the surface of the substrate to be processed will be considered. First, He is not adsorbed even at room temperature. H is desorbed at about 200 ° C. That is, when the temperature of the substrate to be processed is about 200 ° C. at which H is adsorbed, the surface of the substrate to be processed is in a state where H and P are adsorbed, and H is also doped with P together. Since this H doping is desorbed in a later annealing process, the energy required for the H doping is completely wasted. Therefore, for example, when the temperature of the substrate to be processed is higher than 200 ° C. so that only P electrons are adsorbed, and a state in which only P is adsorbed on the surface of the substrate to be processed is formed, very efficient doping is achieved. That is, the intended dopant can be more deeply doped with lower energy.

  Here, in such plasma doping, the diffusion depth of the dopant, so-called doping depth, is determined by the penetration depth when ions such as an inert gas (for example, He gas) are accelerated.

  As described above, according to such plasma doping, it is possible to reduce damage to the substrate to be processed and reduce contaminants to be doped.

  For reference, a mechanism when doping is performed with an ion implantation apparatus will be described. FIG. 10 is a schematic view showing a state in the vicinity of the surface of the silicon substrate when doping is performed using an ion implantation apparatus.

  Referring to FIG. 10, in the ion implantation apparatus, a large lump ion cluster 74 composed of a plurality of dopants 75 is scanned as a beam on each region of silicon substrate 71 to form dopant clusters 75 constituting ion clusters 74. Is injected into the silicon substrate 71. A natural oxide film 72 is formed on the silicon substrate 71, and various deposited layers 73 are adsorbed on the natural oxide film 72. The deposited layer 73 is composed of a dopant 75 and a contaminant generated when the ion cluster 74 collides. Then, the ion clusters 74 collide with the silicon substrate 71 by ion implantation. Then, when the ion cluster 74 collides, a part of the dopant 75 is implanted into the inner side of the silicon substrate 71. In this way, ion implantation is performed. However, when the ion clusters 74 collide, damage 76 due to collision energy occurs in the inner layer near the surface of the silicon substrate 71. In addition to the dopant 75, a part of the deposited layer 73 deposited near the surface layer is implanted as contamination. Furthermore, the crystal structure is broken even near the surface of the silicon substrate 71, and an amorphous layer 77 is formed. A part of the lump of the dopant 75 that is broken at the time of collision is deposited as a deposition layer 73 in another region, thereby inhibiting ion implantation in the other region.

  With respect to the silicon substrate 71 thus doped, as shown in FIG. 11, although the dopant 75 is appropriately implanted, many damages 76 of the silicon substrate 71 occur in the vicinity of the surface layer, and the surface layer is amorphous. Layer 77 will be formed. Furthermore, other than the dopant 75 is also implanted by doping, which is not preferable.

  For reference, a mechanism when doping is performed using ICP will also be described. 12 and 13 are schematic views showing a state in the vicinity of the surface of the silicon substrate when doping is performed by ICP. In doping with ICP, a DC pulse bias is applied. FIG. 12 shows a case where the DC pulse bias is off, and FIG. 13 shows a case where the DC pulse bias is on. Here, as shown in FIG. 12, when the DC pulse bias is off, no bias power is applied, and the dopant 82 is adsorbed on the surface of the silicon substrate 81 on the lower side of the generated plasma 83. It is in a state of being. Then, as shown in FIG. 13, when the DC pulse bias is on, the dopant 82 is drawn into the silicon substrate 81 by the DC pulse bias. Here, the energy of ions generated by the ICP is as high as 500 to 1000 eV, and the damage 84 is caused by the influence of the ion pull-in by the DC pulse bias as in the case of the ion implantation apparatus described above. Occurs in the inner layer. Furthermore, the crystal structure of the surface layer portion is destroyed, and an amorphous layer 85 is formed.

  Such damage to the inner layer of the silicon substrate can be recovered by annealing, but if high temperature and long time annealing is required, throughput increases and junction width increases. From the point of view, it is not preferable.

  That is, in the present invention, silicon generated when a dopant is drawn by using a plasma having a relatively high electron density and a relatively low electron temperature and suppressing the application of bias power to reduce ion energy during doping. This is intended to reduce damage inside the substrate. Furthermore, when the dopant is implanted by the plasma described above, ion implantation is performed on the entire surface of the silicon substrate without causing deposits and without destroying the surface layer structure of the crystal structure of the silicon substrate. It is. Furthermore, even if plasma damage occurs, the damage is very small. When recovering damage by annealing, it can be recovered by annealing at a lower temperature for a shorter time. it can.

  In the above embodiment, the ion energy of the dopant at the time of plasma doping is controlled to be less than 100 eV. However, for that purpose, it is not necessary to apply bias power, Plasma doping may be performed while applying a relatively weak bias power so that the ion energy of the implanted dopant does not increase. Specifically, for example, the dopant is implanted by applying a bias power so that the ion energy of the dopant is less than 100 eV. A dopant ion energy of 100 eV corresponds to, for example, a case where a bias power of 300 W is applied.

  In the above embodiment, when plasma doping is performed, an inert gas serving as a plasma excitation gas is supplied to the surface of the substrate to be processed, and the surface of the substrate to be processed is cleaned. Not limited to this, an inert gas may be supplied to the surface of the substrate to be processed before the plasma doping to clean the surface of the substrate to be processed. In this way, the risk of doping with contaminants can be further reduced. Further, even after the plasma doping, cleaning may be performed by supplying an inert gas to the surface of the substrate to be processed. By doing so, the influence of contaminants can be reduced in the post-doping process.

  Here, the surface property of the silicon substrate was observed using an AFM (Atomic Force Microscope). Table 1 shows the surface roughness of the silicon substrate after each treatment. In Table 1, the surface roughness Ra indicates the arithmetic average roughness, and the surface roughness Rmax indicates the maximum height. In either case, the unit is nm (nanometer).

  Referring to Table 1, the reference, that is, the surface roughness Ra of the silicon substrate when no doping process is performed is 0.10 nm, and the surface roughness Rmax is 1.12 nm. On the other hand, in the case of Sample A to which no bias power is applied in plasma doping, the surface roughness Ra of the silicon substrate is 0.09 nm and the surface roughness Rmax is 0.97 nm. Further, in the case of Sample B in which no bias is applied in plasma doping and DI rinsing is performed later, the surface roughness Ra of the silicon substrate is 0.09 nm and the surface roughness Rmax is 1.02 nm. In the case of Sample C in which the bias power is 100 W and the frequency is 13.56 MHz in the plasma doping, the surface roughness Ra of the silicon substrate is 0.09 nm and the surface roughness Rmax is 1.11 nm. . In addition, in the case of Sample D in which DI (De Ionize) rinse is performed with a bias power of 100 W and a frequency of 13.56 MHz in plasma doping, the surface roughness Ra of the silicon substrate is 0.11 nm. The surface roughness Rmax is 1.13 nm. That is, in any case, it can be understood that both the surface roughness Ra and the surface roughness Rmax of the silicon substrate are very small, and the values hardly change compared to the surface of the silicon substrate when no doping is performed. Therefore, from the observation of the surface property of the silicon substrate by AFM, it can be seen that the shape is good when the bias power is in the range from 0 W to 100 W.

  In other words, the present invention does not dare to form an amorphous layer on the surface of the substrate to be processed and dope the layer, but only reduces plasma damage to the substrate to be processed and suppresses the formation of the amorphous layer as much as possible. Then, doping is performed.

  Next, the state of doping when doping is performed will be described. FIG. 14 is a view showing a state in which a part of the substrate to be processed is analyzed by an atom probe when P (phosphorus) is doped by the plasma doping apparatus according to the present invention. In this case, the bias power is 300 W. The black dots in FIG. 14 indicate the presence of phosphorus atoms, and the portion where the density of black dots is high is considered to be that many phosphorus atoms are concentrated. The region shown in FIG. 14 is a so-called shoulder region of a FinFET described later. Referring to FIG. 14, it can be understood that the distribution state of phosphorus atoms is isotropic.

  Next, TEM photographs in the vicinity of the surface of each silicon substrate when plasma doping is performed with bias power of 0 W, 100 W, 200 W, and 300 W are shown. FIG. 15 is a TEM photograph near the surface of the silicon substrate when the bias power is 0 W, FIG. 16 is a TEM photograph near the surface of the silicon substrate when the bias power is 100 W, and FIG. FIG. 18 is a TEM photograph in the vicinity of the surface of the silicon substrate when the bias power is 300 W. FIG. In FIG. 18 and the like, a dark color area, that is, a black area portion indicates an area that has undergone plasma damage.

Referring to FIGS. 15 to 18, it can be understood that the region subjected to plasma damage is widened as the bias power is increased. Further, it can be understood that EOR (End Of Range: end layer) damage has occurred in the regions 86 and 87 surrounded by the solid line. Further, it can be understood that the area of the amorphous layer in the surface layer portion increases as the bias power increases. That is, it can be understood that as the bias power increases, the plasma damage generated in the silicon substrate increases, and the surface area of the amorphous layer increases. This is greater than the thickness of the amorphous layer shown by A ₁ in FIG. 17, it can be understood from the fact that the direction of the thickness of the amorphous layer shown by A ₂ in FIG. 18 is thicker. The state shown in FIG. 18 is a state where the bias power is 300 W, and plasma doping is preferably performed so as to suppress such a state. Then, the ion energy of the dopant is preferably less than 100 eV corresponding to the bias power of 300 W. Here, the thickness of the amorphous layer represented by A ₁ and A ₂ is about ₂ to 3 nm.

  For reference, a TEM photograph in the vicinity of the surface of the silicon substrate when plasma doping is performed by ICP is shown in FIG. Referring to FIG. 19, it can be understood that an amorphous layer is clearly formed in the vicinity of the surface layer. The thickness of the amorphous layer here is about 5 nm.

  Next, the bias frequency when a bias is applied will be described. FIG. 20 is a TEM photograph near the surface of the silicon substrate when the bias power is 100 W and the bias frequency is 400 kHz. FIG. 21 is a TEM photograph near the surface of the silicon substrate when the bias power is 100 W and the bias frequency is 13.56 MHz. Also in FIG. 20 and the like, a dark region, that is, a black region portion indicates a region that has undergone plasma damage.

  Referring to FIGS. 20 and 21, it can be understood that there are more dark regions near the surface layer in the case shown in FIG. 21 than in FIG. That is, it can be seen that the higher the bias frequency when applying the bias, the smaller the plasma damage. In this case, plasma damage can be reduced by setting the frequency of the bias power to 13.56 MHz. Note that, in an actual use situation, it is preferable to set a region larger than 13.56 MH, specifically within a range of 13.56 to 300 MHz applied to plasma processing by microwaves.

  Note that such plasma doping can be effectively applied to the structure of a 3D device such as a FinFET. FIG. 22 is a schematic perspective view showing a schematic configuration of a FinFET. Referring to FIG. 22, FinFET 91 is formed so that a portion called fin 92 that protrudes upward from the surface of the silicon substrate extends in the front and back direction of the drawing. A gate 93 is formed so as to cover a part of the fin 92. Of the fins 92, a source 94 is formed on the front side of the gate 93, and a drain 95 is formed on the back side. The present invention can be effectively applied to such plasma doping for the structure of the FinFET 91. Note that plasma doping is performed on the FinFET 91 having such a structure in a region indicated by hatching 96 in FIG.

  FIG. 23 is a diagram showing a case where such a fin 92 is doped using an ion implantation apparatus. On the other hand, FIG. 24 is a diagram showing a case where plasma doping according to the present invention is performed. First, referring to FIG. 23, a photoresist layer 98 formed on silicon substrate 97 is formed relatively high with respect to fins 92. In such a case, in the doping using the ion implantation apparatus, since the ion implantation has anisotropy, ions irradiated from an oblique direction indicated by a dotted line 99 in FIG. As a result, ions cannot be appropriately implanted into the fin 92. That is, in the fins 92 disposed in the vicinity of the photoresist layer 98, ion implantation on the photoresist layer 98 side becomes insufficient.

  On the other hand, referring to FIG. 24, in the plasma by the microwave, the plasma is evenly generated and diffused in the region where the fins 92 are formed regardless of the height of the photoresist layer 98. Regardless of the height of the photoresist layer 98, the entire surface of the fin 92 is isotropically plasma-doped. Therefore, appropriate doping is possible for such a FinFET 91.

  Further, in such a FinFET structure, erosion, that is, a change in shape in processing, specifically, so-called shoulder drop at the corners of the fins can be suppressed, and processing uniformity is improved. be able to. FIG. 25 is a diagram illustrating the SSRM of the FinFET when the bias power is 0 W. FIG. 26 is a diagram showing the SSRM of the FinFET when the bias power is 100 W and the frequency of the bias power is 400 kHz. FIG. 27 is a diagram illustrating the SSRM of the FinFET when the bias power is 100 W and the frequency of the bias power is 13.56 MHz. The samples shown in FIGS. 25 to 27 are subjected to lamp annealing, also called RTA (Rapid Thermal Anneal), here, annealing at 950 ° C. for 60 seconds. Further, in FIGS. 25 to 27, the relatively dark gray regions denoted by reference numerals 67, 68, and 69 respectively indicate low resistance, that is, regions into which dopant is implanted.

  Referring to FIG. 25, when the bias power is 0 W, it can be understood that the dopant is appropriately implanted along the shape of the fin. That is, it can be understood that a relatively dark region of gray is formed along the outer shape of the fin. Similarly in FIG. 27, it can be understood that the dopant is implanted along the outer shape of the fin. On the other hand, in the case shown in FIG. 26, the ion implantation is slightly non-uniform. This is presumably because when the bias frequency was set to 400 kHz, the crystal structure was damaged as compared with 13.56 MHz, so that the diffusion during annealing became non-uniform. That is, when doping into such a FinFET shape, the uniformity of dopant implantation can be sufficiently ensured when the bias frequency is 13.56 MHz as shown in FIGS. .

  In the above-described embodiment, the plasma processing is performed by the microwave by RLSA using the slot antenna plate. However, the plasma processing is not limited to this, and the microwave plasma processing apparatus or the slot having the comb-shaped antenna unit is used. A microwave plasma processing apparatus that emits microwaves and generates surface wave plasma may be used.

In the above-described embodiment, the plasma treatment is a treatment using microwave plasma in which the plasma electron temperature is lower than 1.5 eV and the plasma electron density is higher than 1 × 10 ¹¹ cm ^−3. However, the present invention is not limited to this. For example, the present invention is also applied to a region where the electron density of plasma is lower than 1 × 10 ¹¹ cm ⁻³ .

  In the above-described embodiment, the silicon substrate is used as the substrate to be processed. However, the present invention is not limited to this. For example, the present invention can be sufficiently applied to doping in an interlayer film.

  As mentioned above, although embodiment of this invention was described with reference to drawings, this invention is not limited to the thing of embodiment shown in figure. Various modifications and variations can be made to the illustrated embodiment within the same range or equivalent range as the present invention.

  11 MOS type semiconductor device, 12, 61, 71, 81, 97 silicon substrate, 13 element isolation region, 14a p type well, 14b n type well, 15a high concentration n type impurity diffusion region, 15b high concentration p type impurity diffusion region 16a n-type impurity diffusion region, 16b p-type impurity diffusion region, 17 gate oxide film, 18 gate electrode, 19 gate side wall, 21 insulating film, 22 contact hole, 23 hole filling electrode, 24 metal wiring layer, 26, 27, 86, 87 region, 28 control unit, 29 temperature adjustment mechanism, 31 plasma doping apparatus, 32 processing vessel, 33, 46, 47 gas supply unit, 34 support base, 35 microwave generator, 36 dielectric window, 37 slot antenna Plate, 38 Dielectric member, 39 Plasma generation mechanism, 40 Slot hole, 41 Bottom, 42 Wall, 43 Exhaust hole, 44 Lid, 45 O-ring, 48 Lower surface, 49 Gas supply system, 30, 50 Gas supply hole, 51 Cylindrical support, 52 Cooling jacket, 53 Matching mechanism, 54 Mode converter, 55 Wave tube, 56 coaxial waveguide, 57 recess, 58 high frequency power supply, 59 matching unit, 60 circuit, 62,72 natural oxide film, 63 contaminant, 64 surface, 65,83 plasma, 66,75,82 dopant, 73 deposition layer, 74 ion cluster, 76,84 damage, 77,85 amorphous layer, 91 FinFET, 92 fin, 93 gate, 94 source, 95 drain, 96 hatching, 98 photoresist layer, 99 dotted line.

Claims (22)

A plasma doping apparatus that performs doping by injecting a dopant into a substrate to be processed using plasma,
A processing container for injecting a dopant into the substrate to be processed therein;
A gas supply unit for supplying a doping gas and an inert gas for plasma excitation into the processing vessel;
A support base disposed in the processing container and supporting the substrate to be processed thereon;
A plasma generation mechanism for generating plasma in the processing vessel using a microwave;
A pressure adjusting mechanism for adjusting the pressure in the processing vessel;
A bias power supply mechanism capable of supplying bias power to the support base;
A controller for controlling the plasma doping apparatus;
With
The plasma doping apparatus, wherein the control unit controls bias power supplied by the bias power supply mechanism so that ion energy of the dopant is less than 100 eV.   The plasma doping apparatus according to claim 1, wherein the control unit controls the bias power supply mechanism so as not to supply bias power to the support base.   The plasma doping apparatus according to claim 1, wherein the control unit sets a frequency of bias power supplied by the bias power supply mechanism in a range of 13.56 to 300 MHz.   The plasma doping apparatus according to any one of claims 1 to 3, wherein the control unit controls the pressure adjusting mechanism so that a pressure in the processing container becomes 50 mTorr or more.   The said control part heats the said to-be-processed substrate to the temperature which adsorb | sucks the molecule | numerator or atom of the doping gas selectively decomposed | disassembled by plasma on the surface of the to-be-processed substrate to which doping is performed. The plasma doping apparatus according to claim 1.   The said control part supplies the said inert gas to the surface of the said to-be-processed substrate which performs doping, before supplying the said doping gas from the said gas supply part. Plasma doping equipment.   The said control part supplies the said inert gas to the surface of the said to-be-processed substrate which doped the said to-be-processed substrate, The plasma as described in any one of Claims 1-6. Doping equipment.   The plasma generation mechanism includes a microwave generator that generates a microwave for plasma excitation, a dielectric window that transmits the microwave generated by the microwave generator into the processing container, and a plurality of slot holes. The plasma doping apparatus according to claim 1, further comprising: a slot antenna plate that radiates the microwave to the dielectric window.   The plasma doping apparatus according to claim 8, wherein the microwave plasma generated by the plasma generation mechanism is generated by a radial line slot antenna (RLSA). The gas supply unit is at least one selected from the group consisting of B ₂ H ₆ , PH ₃ , AsH ₃ , GeH ₄ , CH ₄ , NH ₃ , NF ₃ , N ₂ , HF, and SiH ₄ as a doping gas. The plasma doping apparatus according to claim 1, wherein the gas is supplied. A plasma doping method that performs doping by injecting a dopant into a substrate to be processed using plasma,
A substrate to be processed is supported on a support table arranged in a processing container, a doping gas and an inert gas for plasma excitation are supplied into the processing container, and plasma is generated in the processing container using microwaves. And applying a bias power to the support so that the ion energy of the dopant is less than 100 eV, and implanting the dopant into the substrate to be processed. A plasma doping method that performs doping by injecting a dopant into a substrate to be processed using plasma,
A substrate to be processed is supported on a support table arranged in a processing container, a doping gas and an inert gas for plasma excitation are supplied into the processing container, and plasma is generated in the processing container using microwaves. Then, a plasma doping method of injecting a dopant into the substrate to be processed without supplying a bias power to the support base.   The plasma doping method according to claim 11, wherein the frequency of the bias power to be supplied is in the range of 13.56 to 300 MHz.   The plasma doping method according to any one of claims 11 to 13, wherein a dopant is implanted into the substrate to be processed at a pressure in the processing vessel of 50 mTorr or higher.   The said to-be-processed substrate is heated to the temperature which adsorb | sucks the molecule | numerator or atom of the doping gas selectively decomposed | disassembled by the plasma on the surface of the to-be-processed substrate which performs doping. Plasma doping method.   The plasma doping method according to any one of claims 11 to 15, wherein the inert gas is supplied to the surface of the substrate to be processed before the doping gas is supplied.   The plasma doping method according to any one of claims 11 to 16, wherein the inert gas is supplied to a surface of the doped substrate after doping the substrate to be treated.   The plasma doping method according to claim 11, wherein the plasma generated using the microwave is generated by a radial line slot antenna (RLSA). A method of manufacturing a semiconductor device manufactured by injecting a dopant into a substrate to be processed using plasma,
A substrate to be processed is supported on a support table arranged in a processing container, a doping gas and an inert gas for plasma excitation are supplied into the processing container, and plasma is generated in the processing container using microwaves. And supplying a bias power to the support so that the ion energy of the dopant is less than 100 eV, and injecting the dopant into the substrate to be processed. A method of manufacturing a semiconductor device manufactured by injecting a dopant into a substrate to be processed using plasma,
A substrate to be processed is supported on a support table arranged in a processing container, a doping gas and an inert gas for plasma excitation are supplied into the processing container, and plasma is generated in the processing container using microwaves. And a step of implanting a dopant into the substrate to be processed without supplying bias power to the support base. A semiconductor device manufactured by injecting a dopant into a substrate to be processed using plasma,
A substrate to be processed is supported on a support table arranged in a processing container, a doping gas and an inert gas for plasma excitation are supplied into the processing container, and plasma is generated in the processing container using microwaves. A semiconductor device manufactured by supplying a bias power to the support so that the ion energy of the dopant is less than 100 eV and injecting the dopant into the substrate to be processed. A semiconductor device manufactured by injecting a dopant into a substrate to be processed using plasma,
A substrate to be processed is supported on a support table arranged in a processing container, a doping gas and an inert gas for plasma excitation are supplied into the processing container, and plasma is generated in the processing container using microwaves. A semiconductor device manufactured by implanting a dopant into the substrate to be processed without supplying bias power to the support base.