JP2013512657A5 - - Google Patents
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Description
例示的な実施の形態において、比較器ロジック回路は3つの比較器を含む。第1の比較器は、出力信号を基準参照電圧の第1の割合を有する第1の参照電圧信号と比較して第1の比較信号を生成し、第1の比較信号は、出力信号電圧が基準参照電圧の第1の割合を上回るかどうかを示す。第2の比較器は、出力信号を、基準参照電圧の第1の割合よりも大きい、基準参照電圧の第2の割合を有する第2の参照電圧信号と比較して第2の比較信号を生成する。第2の比較信号は、出力信号電圧が基準参照電圧の第2の割合を上回るかどうかを示す。第3の比較器は、出力信号を、基準参照電圧の第2の割合よりも大きい、基準参照電圧の第3の割合を有する第3の参照電圧信号と比較して第3の比較信号を生成する。第3の比較信号は、出力信号電圧が基準参照電圧の第3の割合を上回るかどうかを示す。 In the exemplary embodiment, the comparator logic circuit includes three comparators. The first comparator compares the output signal with a first reference voltage signal having a first percentage of the reference reference voltage to generate a first comparison signal, the first comparison signal having an output signal voltage of Indicates whether the first percentage of the reference reference voltage is exceeded. The second comparator generates a second comparison signal by comparing the output signal with a second reference voltage signal having a second ratio of the reference reference voltage that is greater than the first ratio of the reference reference voltage. To do. The second comparison signal indicates whether the output signal voltage exceeds a second percentage of the reference reference voltage. The third comparator generates a third comparison signal by comparing the output signal with a third reference voltage signal having a third ratio of the reference reference voltage that is greater than the second ratio of the reference reference voltage. To do. The third comparison signal indicates whether the output signal voltage exceeds a third percentage of the reference reference voltage.
図5Aおよび図5Bに示されるように、第3の構成において、スイッチマトリクス16は、図5Aに示される第1のフェーズ構成、または図5Bに示される第2のフェーズ構成において容量12および14を相互接続し得る。この第3の構成は、本明細書において「2/3モード」と呼ばれる。その理由は、このモードにおける動作が、出力ノード26における出力電圧信号を、公称的に、バッテリ電圧の約2/3の電圧レベルにすることを目的とするためである。 As shown in FIGS. 5A and 5B, in the third configuration, the switch matrix 16, capacitor 12 and in a second phase configuration shown in the first phase structure, and FIG. 5 B shown in FIG. 5 A 14 may be interconnected. This third configuration is referred to herein as “2/3 mode”. The reason is that the operation in this mode is aimed at bringing the output voltage signal at the output node 26 to a nominal voltage level of about 2/3 of the battery voltage.
例示的な実施の形態における電圧コンバータ10の動作の一例が図9に示される。明確さの目的のために示されていないが、出力電圧(V_OUT)は、0ボルトまたは接地(GND)の初期レベルで始まる。示された例において、参照電圧(V_REF)が入力される。最初に、すなわち、時刻94以前に、V_REFは、バッテリ電圧の1/2(1/2(V_BATT))と、バッテリ電圧の2/3(2/3(V_BATT))の間のレベルの電圧を有する。最初に、比較信号30(V_UD,V_13,V_12,V_23)の状態の組合せが1/3モードに対応するが、それは、V_OUTがバッテリ電圧の1/3(1/3(V_BATT))未満であるためである。すなわち、モード選択信号36(図1)は、次のモードが1/3モードであることを示す。1/3モードにおいて、容量回路の動作により、V_OUTは1/3(V_BATT)のレベルへと立上り始める。なお、図9に示されたクロック信号(CLOCK)の周波数は、単に例示することを意図しており、他の実施の形態では、それより高くなることもあり得る。図9に示されたクロック信号は、明確さの目的のため、比較的低い周波数を有するものとして示されているが、容量回路の充電および放電に対応するV_OUTのわずかな変動は、容量回路がクロックサイクルの1/2毎にスイッチマトリクス16によって切換わるので、図9には明らかにはされていない。 An example of the operation of the voltage converter 10 in an exemplary embodiment is shown in FIG. Although not shown for clarity purposes, the output voltage (V_OUT) begins at an initial level of 0 volts or ground (GND). In the example shown, a reference voltage (V_REF) is input. Initially, that is, before time 94, V_REF has a voltage level between 1/2 (1/2 (V_BATT)) of the battery voltage and 2/3 (2/3 (V_BATT)) of the battery voltage. Have. Initially, the combination of the states of the comparison signal 30 (V_UD, V_13, V_12, V_23 ) corresponds to the 1/3 mode, which is that V_OUT is less than 1/3 of the battery voltage (1/3 (V_BATT)). Because. That is, the mode selection signal 36 (FIG. 1) indicates that the next mode is the 1/3 mode. In the 1/3 mode, V_OUT starts to rise to a level of 1/3 (V_BATT) by the operation of the capacitor circuit. Note that the frequency of the clock signal (CLOCK) shown in FIG. 9 is intended to be merely illustrative, and may be higher in other embodiments. The clock signal shown in FIG. 9 is shown as having a relatively low frequency for purposes of clarity, but slight variations in V_OUT corresponding to the charging and discharging of the capacitive circuit will cause the capacitive circuit to Since it is switched by the switch matrix 16 every half of the clock cycle, it is not clarified in FIG.
時刻94において、V_OUTは1/3(V_BATT)のレベルに達する。応じて、比較信号30(V_UD,V_13,V_12,V_23)の状態の組合せは変化して、1/2Aモードに対応するが、その理由は、V_OUTが1/3(V_BATT)を上回るが、1/2(V_BATT)未満となるためである。なお、現在のモード、またはデコーダロジック回路92の出力(図8)は、他のクロックサイクル毎に変化して次のモードの値をラッチする。1/2Aモードにおいて、容量回路の動作により、V_OUTが1/2V_BATTのレベルへと上昇し続ける。 At time 94, V_OUT reaches a level of 1/3 (V_BATT). Accordingly, the combination of the states of the comparison signals 30 (V_UD, V_13, V_12, V_23 ) changes to correspond to the 1 / 2A mode because V_OUT exceeds 1/3 (V_BATT). This is because it becomes less than / 2 (V_BATT). Note that the current mode or the output of the decoder logic circuit 92 (FIG. 8) changes every other clock cycle to latch the value of the next mode. In the 1 / 2A mode, V_OUT continues to rise to the level of 1 / 2V_BATT by the operation of the capacitor circuit.
この例において、時刻96において、V_OUTは、1/2(V_BATT)のレベルに達する。応じて、比較信号30(V_UD,V_13,V_12およびV_23)の状態の組合せは変化して、2/3モードに対応するが、その理由は、V_OUTが1/2(V_BATT)を上回るが、2/3(V_BATT)未満となるためである。2/3モードにおいて、容量回路の動作により、V_OUTは、2/3V_BATTのレベルへと上昇し続ける。しかしながら、時刻98において、V_OUTはV_REFに達する。応じて、比較信号30(V_UD,V_13,V_12およびV_23)の状態の組合せは変化して、1/2Bモードに対応する。1/2Bモードにおいて、容量回路の動作により、V_OUTは、1/2(V_BATT)のレベルへと下がる。しかしながら、時刻100において、V_OUTはV_REFと再び交差する。応じて、比較信号30(V_UD,V_13,V_12およびV_23)の状態の組合せは変化して2/3モードに対応し、時刻103において、V_OUTは2/3(V_BATT)のレベルへと再び上昇し始める。したがって、V_OUTがV_REFに一旦達すると、V_OUTは、それが2/3モード構成へと上昇するときにはV_REFと交差し、それが1/2Bモード構成へと下がるときには、V_REFへと交差するように、V_REFと交互に交差する。時刻98と時刻102との間において、平均的に、V_OUTはV_REFにほぼ等しい電圧に維持される。V_REFからのV_OUTのばらつきまたは偏差は、容量28(図1)のような電圧コンバータ10の出力におけるフィルタ回路を含むことによって最小化され得る。 In this example, at time 96, V_OUT reaches a level of 1/2 (V_BATT). Accordingly, the combination of the states of the comparison signals 30 (V_UD, V_13, V_12 and V_23 ) changes to correspond to the 2/3 mode because V_OUT exceeds 1/2 (V_BATT). This is because it is less than / 3 (V_BATT). In the 2/3 mode, V_OUT continues to rise to the level of 2/3 V_BATT by the operation of the capacitor circuit. However, at time 98, V_OUT reaches V_REF. Accordingly, the combination of the states of comparison signals 30 (V_UD, V_13, V_12 and V_23 ) changes to correspond to the 1 / 2B mode. In the 1 / 2B mode, V_OUT is lowered to a level of 1/2 (V_BATT) by the operation of the capacitor circuit. However, at time 100, V_OUT crosses V_REF again. Accordingly, the combination of the states of comparison signals 30 (V_UD, V_13, V_12 and V_23 ) changes to correspond to the 2/3 mode, and at time 103, V_OUT rises again to the level of 2/3 (V_BATT). start. Thus, once V_OUT reaches V_REF, V_OUT crosses V_REF when it rises to the 2/3 mode configuration and crosses to V_REF when it falls to the 1 / 2B mode configuration. Crosses alternately with V_REF. Between time 98 and time 102, on average, V_OUT is maintained at a voltage approximately equal to V_REF. Variations or deviations in V_OUT from V_REF can be minimized by including a filter circuit at the output of voltage converter 10 such as capacitor 28 (FIG. 1).
図9に示された例において、時刻104において、V_REFは1/3(V_BATT)と1/2(V_BATT)の間の新しいレベルへと変化する。応じて、比較信号30(V_UD,V_13,V_12およびV_23)の状態の組合せは変化して、1/3モードに対応する。1/3モードにおいて、容量回路の動作により、V_OUTが1/3(V_BATT)のレベルへと下がる。しかしながら、時刻106において、V_OUTはV_REFに達する。応じて、比較信号30(V_UD,V_13,V_12およびV_23)の状態の組合せは変化して、1/2Aモードに対応する。1/2Aモードにおいて、容量回路の動作により、V_OUTが1/2(V_BATT)のレベルへと上昇させる。しかしながら、時刻108において、V_OUTはV_REFと再び交差する。応じて、比較信号30(V_UD,V_13,V_12およびV_23)の状態の組合せは変化して1/3モードに対応し、V_OUTは1/3(V_BATT)のレベルへと再び低下する。すなわち、V_OUTが新しいV_REFレベルに一旦達すると、V_OUTは、交互に、1/2モード構成に向けて上昇するときにV_REFと交差し、1/3モード構成へと低下するときにV_REFと交差する。ほぼ時刻106の後において、平均的に、V_OUTは新しいV_REFにほぼ等しい電圧に維持される。 In the example shown in FIG. 9, at time 104, V_REF changes to a new level between 1/3 (V_BATT) and 1/2 (V_BATT). Accordingly, the combination of the states of the comparison signals 30 (V_UD, V_13, V_12 and V_23 ) changes to correspond to the 1/3 mode. In the 1/3 mode, V_OUT decreases to a level of 1/3 (V_BATT) by the operation of the capacitor circuit. However, at time 106, V_OUT reaches V_REF. Accordingly, the combination of the states of the comparison signals 30 (V_UD, V_13, V_12 and V_23 ) changes to correspond to the 1 / 2A mode. In the 1 / 2A mode, V_OUT is raised to a level of 1/2 (V_BATT) by the operation of the capacitor circuit. However, at time 108, V_OUT crosses V_REF again. Accordingly, the combination of the states of the comparison signals 30 (V_UD, V_13, V_12 and V_23 ) changes to correspond to the 1/3 mode, and V_OUT drops again to the level of 1/3 (V_BATT). That is, once V_OUT reaches the new V_REF level, V_OUT alternately crosses V_REF when rising towards the 1/2 mode configuration and crosses V_REF when falling to the 1/3 mode configuration. . After approximately time 106, on average, V_OUT is maintained at a voltage approximately equal to the new V_REF.
Claims (18)
複数のモード構成を有するスイッチマトリクスを用いて、モード制御信号に応答してモード構成を選択するステップを備え、各々のモード構成は、複数の出力信号電圧のうちの1つに対応し、
前記選択するステップは、電位と、選択されたモードに対応する構成への出力ノードとの間に互いに接続された容量回路の複数の容量を構成するステップを含み、
前記選択するステップは、さらに、クロック信号に応答して、前記容量回路が充電される、選択されたモード構成のうちの第1のフェーズ構成と、前記容量回路が放電される、前記選択されたモード構成のうちの第2のフェーズ構成とを切換えて、前記選択されたモード構成に対応する出力信号電圧を有する出力ノードにおいて出力信号を生成するステップを含み、
前記出力信号を参照信号と比較して、方向比較信号を生成するステップと、
前記方向比較信号に応答して前記モード制御信号を生成するステップとをさらに備える、方法。 A voltage conversion method in a voltage converter,
Using a switch matrix having a plurality of mode configurations to select a mode configuration in response to a mode control signal, each mode configuration corresponding to one of the plurality of output signal voltages;
The step of selecting includes configuring a plurality of capacitors of a capacitor circuit connected to each other between a potential and an output node to a configuration corresponding to the selected mode;
The selecting step further includes a first phase configuration of selected mode configurations in which the capacitive circuit is charged in response to a clock signal, and the capacitive circuit is discharged. Switching a second phase configuration of mode configurations to generate an output signal at an output node having an output signal voltage corresponding to the selected mode configuration;
Comparing the output signal with a reference signal to generate a direction comparison signal;
Generating the mode control signal in response to the direction comparison signal.
前記モード制御信号を生成するステップは、
前記参照信号が前記出力信号よりも大きいことを示す前記方向比較信号に応答して、前記参照信号よりも大きい出力信号電圧に対応するモード構成を選択するステップと、
前記出力信号が前記参照信号よりも大きいことを示す前記方向比較信号に応答して、前記参照信号よりも小さい出力信号電圧に対応するモード構成を選択するステップとを含む、請求項1に記載の方法。 The direction comparison signal indicates which of the output signal and the reference signal is greater in intensity;
Generating the mode control signal comprises:
Selecting a mode configuration corresponding to an output signal voltage greater than the reference signal in response to the direction comparison signal indicating that the reference signal is greater than the output signal;
In response to the direction comparing signal indicating that said output signal is greater than the reference signal, and selecting the corresponding mode configuration to a smaller output signal voltage than the reference signal, according to claim 1 Method.
基本参照電圧の1/3の出力信号電圧に対応する第1のモード構成と、
前記参照電圧の1/2の出力信号電圧に対応する第2のモード構成と、
前記参照電圧の2/3の出力信号電圧に対応する第3のモード構成とを含む、請求項2に記載の方法。 The plurality of mode configurations are:
A first mode configuration corresponding to an output signal voltage of 1/3 of the basic reference voltage;
A second mode configuration corresponding to an output signal voltage of ½ of the reference voltage;
The third mode configuration and the including method according to 請 Motomeko 2 corresponding to 2/3 the output signal voltage of the reference voltage.
少なくとも1つのモード制御信号に基づいて、第1のモード構成において電圧コンバータのスイッチマトリクスを動作させるステップを備え、前記スイッチマトリクスは、容量回路の複数の容量が電位と出力ノードとの間で異なって接続される、少なくとも3つの異なるモード構成を有し、前記3つの異なるモード構成は、3つの異なる出力信号の電圧レベルに対応し、
前記方法は、
前記出力信号を参照信号と比較するステップと、
前記比較に基づいて前記3つの異なるモード構成のうちの第2のモード構成において、前記電圧コンバータの前記スイッチマトリクスを動作させるステップとをさらに備える、方法。 An electronically implemented method of operating a voltage converter, the method comprising:
Operating a switch matrix of a voltage converter in a first mode configuration based on at least one mode control signal, wherein the switch matrix includes a plurality of capacitors of a capacitance circuit that differ between a potential and an output node. Having at least three different mode configurations connected, the three different mode configurations corresponding to voltage levels of three different output signals;
The method
Comparing the output signal with a reference signal;
Operating the switch matrix of the voltage converter in a second of the three different mode configurations based on the comparison .
前記出力電圧レベルを前記出力ノードにおけるバッテリ電圧の約1/3にさせる1/3モード構成と、A 1/3 mode configuration that causes the output voltage level to be about 1/3 of the battery voltage at the output node;
前記出力電圧レベルを前記出力ノードにおける前記バッテリ電圧の約1/2にさせる1/2モード構成と、A ½ mode configuration for causing the output voltage level to be about ½ of the battery voltage at the output node;
前記出力電圧レベルを前記出力ノードにおける前記バッテリ電圧の約2/3にさせる2/3モード構成とを含む、請求項6に記載の方法。7. A method according to claim 6, comprising a 2/3 mode configuration that causes the output voltage level to be approximately 2/3 of the battery voltage at the output node.
複数のモード構成を有するスイッチマトリクスを備え、各々のモード構成は、出力信号の複数の電圧レベルのうちの1つに対応し、前記スイッチマトリクスは、モード選択信号に応答して前記複数のモード構成のうちの選択された1つで動作するように構成され、A switch matrix having a plurality of mode configurations, each mode configuration corresponding to one of a plurality of voltage levels of an output signal, wherein the switch matrix is responsive to a mode selection signal Configured to operate with a selected one of
前記出力信号と参照信号との比較に基づいて方向比較信号を生成するように構成された比較器回路をさらに備え、前記比較器回路は、また、複数の比較器を有し、前記複数の比較器の各々は、前記複数の比較器の他の比較器と異なる電圧を受けるように構成された第1の入力を有し、And further comprising a comparator circuit configured to generate a direction comparison signal based on a comparison between the output signal and a reference signal, the comparator circuit also comprising a plurality of comparators, the plurality of comparisons Each of the comparators has a first input configured to receive a voltage different from other comparators of the plurality of comparators;
前記方向比較信号および前記複数の比較器の1以上の出力に基づいて前記モード選択信号を生成するように構成された制御ロジック回路をさらに備える、電圧コンバータ。A voltage converter further comprising a control logic circuit configured to generate the mode selection signal based on the direction comparison signal and one or more outputs of the plurality of comparators.
前記スイッチマトリクスは、前記複数のモード構成のうちの異なるモード構成において、電位と、出力ノードとの間で前記複数の容量を、異なるように接続する、請求項11に記載の電圧コンバータ。12. The voltage converter according to claim 11, wherein the switch matrix connects the plurality of capacitors differently between a potential and an output node in a different mode configuration among the plurality of mode configurations.
異なる複数の電圧を生成して、前記異なる複数の電圧を、前記複数の比較器のそれぞれの第1の入力に与えるように構成された電圧レベル発生器を含む、請求項11に記載の電圧コンバータ。The voltage converter of claim 11, comprising a voltage level generator configured to generate different voltages and provide the different voltages to a first input of each of the plurality of comparators. .
基本参照電圧の第1の割合となる出力信号に対応する第1のモード構成と、A first mode configuration corresponding to an output signal that is a first proportion of a basic reference voltage;
前記基本参照電圧の第2の割合となる出力信号に対応する第2のモード構成と、A second mode configuration corresponding to an output signal that is a second proportion of the basic reference voltage;
前記基本参照電圧の第3の割合となる出力信号に対応する第3のモード構成とを含む、請求項11に記載の電圧コンバータ。12. A voltage converter according to claim 11, comprising a third mode configuration corresponding to an output signal that is a third proportion of the basic reference voltage.
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