JP2013258424A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably control the threshold voltage of an N-channel MOSFET while preventing an increase in the threshold voltage of a P-channel MOSFET.SOLUTION: A semiconductor device 1 is manufactured by: forming a gate insulating film on a semiconductor substrate 10; forming a mask which has an opening on the gate insulating film formed in an N-channel MOSFET forming region and covers the gate insulating film formed in a P-channel MOSFET forming region; forming a first metal layer on the gate insulating film positioned in the N-channel MOSFET forming region, and on the mask formed in the P-channel MOSFET forming region; and diffusing a metal forming the first metal layer into the gate insulating film formed in the N-channel MOSFET forming region by heat treatment.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In recent years, with the progress of miniaturization of LSIs, drive current deterioration due to depletion of polysilicon gate electrodes constituting each MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), and gate leakage current due to thinning of the gate insulating film have occurred. It is a problem. Therefore, a technique for avoiding depletion of the electrode by using a metal gate electrode and a technique for reducing the gate leakage current by increasing the physical film thickness by using a high dielectric constant material for the gate insulating film are being studied. .

  As one of MOSFETs using a metal gate electrode and a high dielectric constant insulating film, there is a structure in which an interface insulating film such as SiO 2, a high dielectric constant insulating film, a metal gate electrode, and a polysilicon gate electrode are stacked on a semiconductor substrate. In a MOSFET having such a structure, it is important to adjust the threshold voltage. In the N-channel MOSFET, it is possible to control the work function and reduce the threshold voltage by localizing a small amount of metal different from the metal gate electrode between the interface insulating film and the high dielectric constant insulating film. .

In Patent Document 1, a hafnium silicate insulating film is formed on a base insulating film such as SiO ₂ , and then a metal material is patterned by photolithography and a metal etching process to thereby form an N-channel MOSFET on the hafnium silicate insulating film. A technique for forming a metal tantalum film is disclosed only in US Pat.
Further, Patent Document 2 discloses a MOSFET having a gate insulating film made of SiO _2, a technique for thermally diffusing a metal element such as La from the surface of the SiO ₂ gate insulating film is disclosed. As a result, the metal element concentration is highest on the surface of the SiO ₂ gate insulating film, the metal element concentration decreases as the depth of the gate insulating film increases, and the metal element concentration at a certain depth from the surface of the gate insulating film increases. A gate insulating film structure that is substantially zero is manufactured.

JP 2008-53283 A WO2004 / 008544

Here, referring to FIGS. 8 and 9, the silicon oxide film 116 which is an interface insulating film of the N-channel MOSFET and the HfO ₂ film which is a high dielectric constant insulating film are formed by patterning a metal material by photolithography and a metal etching process. An example of a method of manufacturing a semiconductor device in which La is localized only during 118 will be described.

First, as shown in FIG. 8A, a silicon oxide film 116 and an HfO ₂ film 118 are formed on a semiconductor substrate 110. Next, a La film 120 is deposited on the entire surface of the HfO ₂ film 118 by using a sputtering method or the like. On the semiconductor substrate 110, a P well 112, which is an N channel MOSFET formation region, an N well 113, which is a P channel MOSFET formation region, and an element isolation insulating film 111 are formed in advance.

Subsequently, as shown in FIG. 8B, a resist mask 122 is formed so as to cover only the La film 120 formed in the P well 112. Then, using the resist mask 122 as a mask, the La film 120 exposed in the P-channel MOSFET formation region is wet-etched with diluted hydrochloric acid (FIG. 8C), and then the resist mask 122 is formed by H ₂ / N ₂ plasma ashing. Remove. As a result, as shown in FIG. 9A, the La film 120 is formed only in the N channel MOSFET formation region, and the HfO ₂ film 118 is exposed in the P channel MOSFET formation region.

Next, as shown in FIG. 9B, a metal gate electrode 124 and a polysilicon electrode 126 are formed. Further, gate electrode processing is performed as shown in FIG. Thereafter, impurity implantation for forming source / drain regions, sidewall formation, heat treatment, and the like are performed to form N-channel and P-channel MOSFETs (not shown). In N-channel MOSFET, by heat treatment, La is diffused to the interface between the inside HfO ₂ film 118, and the HfO ₂ film 118 and the silicon oxide film 116.

In this semiconductor device manufacturing method, a La film 120 is formed once on the HfO ₂ film 118 formed in the P channel MOSFET formation region, and then the La film 120 located in the P channel MOSFET formation region is removed by wet etching. Processing is in progress. In this case, as shown in FIG. 8C, the La film 120 on the HfO ₂ film 118 formed in the P channel MOSFET formation region is not sufficiently removed by wet etching, and for example, La121 of about 1E14 atoms / cm ^2. Will remain on the surface of the HfO ₂ film 118. If the metal gate electrode 124 and the polysilicon electrode 126 are formed on the La 121 in a state where the La 121 remains, there arises a problem that the threshold voltage of the P-channel MOSFET increases.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device comprising a first conductivity type channel MOSFET and a second conductivity type channel MOSFET on a semiconductor substrate, wherein the first conductivity type channel MOSFET forming region of the semiconductor substrate is provided. And a step of forming a gate insulating film in the second conductivity type channel MOSFET formation region, an opening on the gate insulation film formed in the first conductivity type channel MOSFET formation region, and the second Forming a mask for covering the gate insulating film formed in the conductive channel MOSFET forming region; and on the gate insulating film located in the first conductive channel MOSFET forming region; and a second conductive channel MOSFET forming region Forming a first metal layer on the mask formed on the substrate; and the first conductivity type channel. In said gate insulating film formed on the MOSFET formation region, and a step of diffusing by heat treatment the metal forming the first metal layer, characterized in that.

  The semiconductor device of the present invention is a semiconductor device comprising a first conductivity type channel MOSFET and a second conductivity type channel MOSFET on a semiconductor substrate, wherein the first conductivity type channel MOSFET is formed on the semiconductor substrate. A first gate insulating film containing one metal and a metal gate electrode made of a second metal provided on the first gate insulating film, the first gate insulating film in the first gate insulating film The concentration of the first metal decreases from the interface between the first gate insulating film and the metal gate electrode made of the second metal toward the semiconductor substrate, and in the first gate insulating film. The second conductivity type channel MOSFET has a profile having a maximum value, and includes a second gate insulating film formed on the semiconductor substrate, and a second gold insulating film provided on the gate insulating film. A metal gate electrode made of, characterized in that it comprises a.

  According to the above configuration, in the state where the metal film is positioned on the gate insulating film of the first conductivity type channel MOSFET and the mask is positioned between the gate insulating film and the metal film of the second conductivity type channel MOSFET, The metal forming the metal layer is thermally diffused with respect to the gate insulating film. For this reason, the metal which forms a 1st metal layer does not remain on the gate insulating film of 2nd conductivity type channel MOSFET.

  According to the present invention, in a semiconductor device including a first conductivity type channel MOSFET and a second conductivity type channel MOSFET on a semiconductor substrate, the metal that forms the first metal layer on the gate insulating film of the second conductivity type channel MOSFET. Does not remain. For this reason, it is possible to reliably control the threshold voltage of the first conductivity type channel MOSFET while preventing an increase in the threshold voltage of the second conductivity type MOSFET.

It is sectional drawing which shows the semiconductor device of embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of embodiment of this invention. It is sectional drawing which shows an example of the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows an example of the manufacturing process of the conventional semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1A is a cross-sectional view showing a semiconductor device 1 in the present embodiment. The semiconductor device 1 includes an N channel MOSFET (first conductivity type channel MOSFET) and a P channel MOSFET (second conductivity type channel MOSFET) on a semiconductor substrate 10 such as silicon. The N channel MOSFET is formed in the P well 14, and the P channel MOSFET is formed in the N well 15. The N-channel MOSFET and the P-channel MOSFET are separated by an element isolation insulating film 12.

The N-channel MOSFET has a gate insulating film 25 (first gate insulating film) containing La provided on the semiconductor substrate 10 and a metal gate electrode 28. The metal forming the metal gate electrode 28 is at least one selected from the group consisting of TiN, W, TaN, TaSiN, Ru, TiAl, and Al. The gate insulating film 25 includes an interface insulating film 16 and a high dielectric constant film 26 having a dielectric constant higher than that of the interface insulating film 16. As the interface insulating film 16, for example, a silicon oxynitride film, a silicon oxide film, a silicon nitride film, or the like can be used. As the high dielectric constant film 26, for example, HfO ₂ or ZrO ₂ can be used. The gate electrode 63 of the N-channel MOSFET is composed of a film in which a metal gate electrode 28, a silicon electrode 52, and a silicide layer 62 are stacked.

  FIG. 1B is a diagram showing a La concentration profile in the gate insulating film 25. The concentration of La in the gate insulating film 25 has a profile that decreases from the interface between the gate insulating film 25 and the metal gate electrode 28 toward the semiconductor substrate 10 and has a maximum value in the gate insulating film 25. More specifically, the concentration of La decreases from the interface between the high dielectric constant film 26 and the metal gate electrode 28 toward the interface insulating film 16 and increases at the interface between the high dielectric constant film 26 and the interface insulating film 16. And have a profile forming a maximum value.

La is used as a threshold voltage control metal for the N-channel MOSFET. In the N-channel MOSFET, the threshold voltage can be controlled by La existing at the interface between the high dielectric constant film 26 and the interface insulating film 16. As the threshold voltage control metal, at least one selected from the group consisting of La, Dy, La ₂ O ₃ , and Dy ₂ O ₃ can be used.

The P-channel MOSFET has a gate insulating film 27 (second gate insulating film) provided on the semiconductor substrate 10 and a metal gate electrode 28. The gate insulating film 27 includes the interface insulating film 16 and the high dielectric constant film 18 having a higher dielectric constant than that of the interface insulating film 16. As the interface insulating film 16, for example, a silicon oxynitride film, a silicon oxide film, a silicon nitride film, or the like can be used. For example, HfO ₂ or ZrO ₂ can be used as the high dielectric constant film 18. The high dielectric constant film 18 does not contain La in the inside and upper and lower interfaces. The gate electrode 67 of the P-channel MOSFET is composed of a film in which a metal gate electrode 28, a silicon electrode 58, and a silicide layer 66 are stacked.

  Note that the N-channel MOSFET further includes an extension region 40, a deep SD region 50, and a silicide layer 60. The P-channel MOSFET further has an extension region 44, a deep SD region 56, and a silicide layer 64. An interlayer film 70 is formed on the N-channel MOSFET and the P-channel MOSFET. A contact 72 connected to the N-channel MOSFET and the P-channel MOSFET is embedded in the interlayer film 70.

  Next, the manufacturing method of the semiconductor device concerning embodiment of this invention is demonstrated with reference to FIGS. First, as illustrated in FIG. 2A, an element isolation insulating film 12 is formed on a semiconductor substrate 10. The element isolation insulating film 12 is formed by, for example, an STI (Shallow Trench Isolation) method. Thereafter, a P well 14 is formed in the N channel MOSFET formation region, and an N well 15 is formed in the P channel MOSFET formation region.

  Then, as shown in FIG. 2B, a 1.0 nm silicon oxynitride film is formed as the interface insulating film 16 in the N-channel MOSFET formation region and the P-channel MOSFET formation region. The interfacial insulating film 16 is formed, for example, by forming a silicon oxide film by sulfuric acid / hydrogen peroxide mixture, ozone water, hydrochloric acid / ozone water, after thermal oxidation, and then performing plasma nitridation.

Thereafter, as shown in FIG. 2C, a high dielectric constant film 18 is formed on the interface insulating film 16. The high dielectric constant film 18 is an insulating film selected from HfO ₂ and ZrO ₂ . In this embodiment, an HfO ₂ film is used. The film thickness of the high dielectric constant film 18 is 1.0 nm or more and 5.0 nm or less. The method for forming the high dielectric constant film 18 is a method selected from a CVD method, an ALCVD method, and a sputtering method.

  Then, as shown in FIG. 2D, a silicon oxide film 20 is formed on the entire surface of the high dielectric constant film 18 in the N channel MOSFET formation region and the P channel MOSFET formation region. The film thickness of the silicon oxide film 20 is 2 nm or more and 10 nm or less. As a method for forming the silicon oxide film 20, for example, a CVD method, a sputtering method, or the like can be used. As will be described later, the silicon oxide film 20 is used as a hard mask when La is selectively diffused into the high dielectric constant film of the N-channel MOSFET. Considering use as a hard mask for La diffusion, amorphous carbon or silicon nitride film may be used in addition to the silicon oxide film.

  Next, as shown in FIG. 3A, after a resist is formed so as to cover the entire surface of the silicon oxide film 20, the resist in the N channel MOSFET formation region is opened, and the silicon oxide film in the N channel MOSFET formation region is formed. 20 is exposed. Thereby, a resist mask 22 is formed.

Subsequently, as shown in FIG. 3B, the silicon oxide film 20 in the N-channel MOSFET formation region is removed. Thereby, an opening of the silicon oxide film 20 is formed in the N channel MOSFET formation region. The edge of the opening is preferably located on the element isolation insulating film 12. For removing the silicon oxide film 20, wet etching or dry etching with dilute HF can be used. Further, the resist mask 22 is removed by wet treatment using a sulfuric acid-hydrogen peroxide solution. For removing the resist mask 22, oxygen plasma ashing, H ₂ / N ₂ ashing, or the like may be used in addition to the sulfuric acid-hydrogen peroxide solution.

Next, as shown in FIG. 3C, a La film 24 is formed on the entire surface by sputtering. The film thickness ranges from 0.1 nm to 2.0 nm. Instead of the La film 24, it is also possible to use a Dy film, a La ₂ O ₃ film, or a Dy ₂ O ₃ film.

Thereafter, as shown in FIG. 3D, La is diffused into the high dielectric constant film 18 of the N-channel MOSFET by heat treatment using the silicon oxide film 20 as a hard mask. Thereby, the high dielectric constant film 26 containing La is formed in the N-channel MOSFET. The heat treatment temperature is 900 ° C. or higher and 1100 ° C. or lower. The heat treatment time is 10 msec or more and 30 sec or less. Thereby, as shown in FIG. 1B, the La concentration has a profile that decreases from the interface between the high dielectric constant film 26 containing La and the metal gate electrode 28 toward the interface insulating film 16. Since La has a low diffusion rate in the interface insulating film 16 that is a silicon oxynitride film, it has a profile that rises locally at the interface between the high dielectric constant film 26 and the interface insulating film 16. At this time, only La of 1E13 atoms / cm ² or less reacts with the silicon oxide film 20 at the interface between the silicon oxide film 20 and the La film 24. Then, La does not diffuse into the high dielectric constant film 18 in the P channel MOSFET formation region.

  Next, as shown in FIG. 4A, the excess La film 24 is removed. For removing the La film 24, for example, dilute hydrochloric acid is used. Thereafter, as shown in FIG. 4B, the silicon oxide film 20 in the P channel MOSFET formation region is removed by dilute HF.

  Then, as shown in FIG. 4C, a metal gate electrode 28 made of a second metal different from the first metal is formed. The metal gate electrode 28 is at least one metal selected from TiN, W, TaN, TaSiN, Ru, TiAl, and Al. The film thickness of the metal gate electrode 28 is 1.0 nm or more and 20.0 nm or less. Subsequently, a silicon electrode 30 made of amorphous silicon is formed. The film thickness of the silicon electrode 30 is 10 nm or more and 100 nm or less. Polysilicon may be used as the silicon electrode 30 in addition to amorphous silicon. Thereafter, a hard mask 32 is formed on the silicon electrode 30. The hard mask 32 is a film selected from a silicon oxide film and a silicon nitride film.

  Further, as shown in FIG. 4D, a resist mask 34 is formed on the hard mask 32. Next, as shown in FIG. 5A, the gate insulating film and the gate electrode are processed into a gate shape by dry etching and wet processing. Thereafter, as shown in FIG. 5B, the resist mask 34 and the hard mask 32 are removed.

  Then, as shown in FIG. 5C, a silicon nitride film is formed by ALCVD, and an offset spacer 36 is formed. The film for the offset spacer 36 may be a silicon oxide film or a stacked structure of silicon nitride film / silicon oxide film.

Thereafter, as shown in FIG. 5D, an extension region 40 is formed by ion implantation in the N-channel MOSFET formation region with the resist channel 38 masking the P-channel MOSFET formation region. The implantation conditions are As 2 keV 8E14 atoms / cm ² 0 degrees and BF ₂ 50 keV 3E13 atoms / cm ² 30 degrees.

Subsequently, as shown in FIG. 6A, an extension region 44 is formed by ion implantation in the P channel MOSFET region in a state where the N channel MOSFET formation region is similarly masked by the resist mask 42. The implantation conditions are BF ₂ 3 keV 8E14 atoms / cm ² 0 degrees and As 50 keV 3E13 atoms / cm ² 30 degrees.

  Subsequently, a sidewall spacer 46 is formed as shown in FIG. 6B by forming a silicon nitride film or a silicon oxide film and then performing dry etching.

Thereafter, as shown in FIG. 6C, a Deep SD region 50 is formed by ion implantation in the N-channel MOSFET formation region in a state where the P-channel MOSFET formation region is masked by the resist mask 48. The implantation conditions are As 20 keV 3E15 atoms / cm ² 0 degrees and P 20 keV 5E13 atoms / cm ² 0 degrees. At this time, ions are also implanted into the silicon electrode, and an N-type silicon electrode 52 is formed.

Thereafter, the resist mask 48 is removed as shown in FIG. Subsequently, a Deep SD region 56 is formed in the P channel MOSFET region by ion implantation in a state where the N channel MOSFET formation region is similarly masked by the resist mask 54. The implantation conditions are B 7 keV 5.0E13 atoms / cm ² 0 degrees and BF2 9 keV 2E15 atoms / cm ² 0 degrees. At this time, ions are also implanted into the silicon electrode, and a P-type silicon electrode 58 is formed.

  Then, after removing the resist mask 54, heat treatment is performed to activate the extension and deep SD regions. The heat treatment conditions are 1050 ° C. and 0 seconds.

  Thereafter, silicide films 60, 62, 64 and 66 are formed as shown in FIG. A method of forming the silicide films 60, 62, 64, 66 is as follows. First, a metal film such as a NiPt alloy film is formed with a film thickness of about 8 nm by sputtering. The Pt content in the NiPt alloy film is about 5%. Subsequently, heat treatment is performed at a temperature of 375 ° C. to form a primary silicide layer. Then, the unreacted NiPt film is removed with aqua regia to expose the surface of the primary silicide layer. Next, a secondary silicide film is formed by heat treatment at a temperature of 500.degree. Thereby, silicide films 60, 62, 64, 66 made of, for example, NiPtSi are formed. As the silicide films 60, 62, 64, and 66, NiSi or PtSi may be used in addition to NiPtSi.

  Next, as shown in FIG. 7B, a contact etching stopper film 68 is formed. The film type of the contact etching stopper film 68 is a silicon nitride film. The film thickness is 10 nm or more and 100 nm or less. Further, as shown in FIG. 7C, after an interlayer insulating film 70 made of a silicon oxide film is formed, a contact 72 is formed as shown in FIG. 7D.

Next, the effect of this embodiment is demonstrated. In the method of manufacturing the semiconductor device in the above embodiment, as shown in FIG. 3D, La is formed in a state where the high dielectric constant film 18 of the P-channel MOSFET is covered with the hard mask made of the silicon oxide film 20. Thermal diffusion. At this time, since only La of 1E13 atoms / cm ² or less reacts with the silicon oxide film 20 in the P channel MOSFET formation region at the interface between the silicon oxide film 20 and the La film 24, the high dielectric of the P channel MOSFET formation region. La does not diffuse into the rate film 18. Therefore, after removing the excess La and the silicon oxide film 20, La does not remain on the gate insulating film of the P-channel MOSFET. Therefore, it is possible to reliably control the threshold voltage of the N-channel MOSFET while preventing an increase in the threshold voltage of the P-channel MOSFET.

In FIG. 3B, a sulfuric acid-hydrogen peroxide solution can be used for removing the resist mask 22. This is because the base of the resist mask 22 is the silicon oxide film 20. Thus, since the resist mask 22 can be removed without using H ₂ / N ₂ plasma, the high dielectric constant film and the silicon oxynitride film are not nitrided. Therefore, the threshold voltage of the MOSFET does not fluctuate. This has an excellent effect in the case where the resist mask 22 is peeled off and the re-process is performed when patterning deviation of the resist mask 22 occurs.

On the other hand, in the manufacturing method shown in FIG. 8, in the process of FIG. 8B, when the resist 122 is peeled off and re-processed due to the occurrence of patterning deviation or the like, a non-oxidizing atmosphere such as H ₂ / N _{2 is used.} Ashing is required. At this time, the HfO ₂ film 118 and the silicon oxide film 116 are nitrided by the H ₂ / N ₂ plasma, causing a problem that a desired threshold voltage varies.

The semiconductor device according to the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the above embodiment, La is diffused in the high dielectric constant film 18 of the N-channel MOSFET, and La is not diffused in the high dielectric constant film 18 of the P-channel MOSFET. However, the present invention is also effective for a configuration in which Al is diffused in the high dielectric constant film 18 of the P-channel MOSFET and Al is not diffused in the high dielectric constant film 18 of the N-channel MOSFET. In this case, the high dielectric constant film 18 in the N channel MOSFET formation region is covered with a hard mask made of a silicon oxide film, an Al film or an Al ₂ O ₃ film is formed on the entire surface, and then heat treatment is performed to increase the P channel MOSFET Al may be diffused in the dielectric constant film 18. Thus, it goes without saying that the threshold voltage of the P-channel MOSFET can be reliably controlled while preventing an increase in the threshold voltage of the N-channel MOSFET.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor substrate 12 Insulating film (STI) for element isolation
14 P well 15 N well 16 Interfacial insulating film 18 High dielectric constant film 20 Silicon oxide film (hard mask)
22 resist mask 24 La film 25 gate insulating film 26 high dielectric constant film 27 gate insulating film 28 metal gate electrode 30 silicon electrode 32 hard mask 34 resist mask 36 offset spacer 38 resist mask 40 NMOSFET extension region 42 resist mask 44 PMOSFET extension Region 46 Sidewall spacer 48 Resist mask 50 NMOFFET Deep SD region 52 Silicon electrode 54 Resist mask 56 PMOSFET Deep SD region 58 Silicon electrode 60 Silicide layer 62 Silicide layer 63 Gate electrode 64 Silicide layer 66 Silicide layer 67 Gate electrode 68 Contact etching Stopper film 70 Interlayer film 72 Contact

Claims (14)

A method for manufacturing a semiconductor device comprising a first conductivity type channel MOSFET and a second conductivity type channel MOSFET on a semiconductor substrate,
Forming a gate insulating film in a first conductivity type channel MOSFET formation region and a second conductivity type channel MOSFET formation region of the semiconductor substrate;
A mask is formed having an opening on the gate insulating film formed in the first conductivity type channel MOSFET forming region and covering the gate insulating film formed in the second conductivity type channel MOSFET forming region. And a process of
Forming a first metal layer on the gate insulating film located in the first conductivity type channel MOSFET formation region and on the mask formed in the second conductivity type channel MOSFET formation region;
Diffusing a metal for forming the first metal layer in the gate insulating film formed in the first conductivity type channel MOSFET formation region by heat treatment;
Including
The method of manufacturing a semiconductor device, wherein the mask is at least one selected from the group consisting of SiO ₂ and amorphous carbon. In the manufacturing method of the semiconductor device according to claim 1,
The step of forming the gate insulating film includes:
Forming a first insulating film;
Forming a second insulating film having a dielectric constant higher than that of the first insulating film;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 1 or 2,
Removing the excess first metal layer from the first conductivity type channel MOSFET formation region and the second conductivity type channel MOSFET formation region;
Removing the mask from the second conductivity type channel MOSFET formation region;
A method for manufacturing a semiconductor device, further comprising: In the manufacturing method of the semiconductor device according to claim 3,
Forming a second metal layer made of a metal different from the first metal layer on the gate insulating film in the first conductivity type channel MOSFET formation region and the second conductivity type channel MOSFET formation region of the semiconductor substrate; When,
Forming a silicon layer on the second metal layer;
A method for manufacturing a semiconductor device, further comprising: In the manufacturing method of the semiconductor device according to claim 1,
The step of forming the mask includes
Forming a film made of the constituent material of the mask on the entire surface of the gate insulating film in the first conductivity type channel MOSFET formation region and the second conductivity type channel MOSFET formation region;
Forming a resist covering the entire surface of the film;
Forming an opening in the resist in the first conductivity type channel MOSFET formation region and exposing the film;
Removing the film exposed from the opening of the resist and exposing the gate insulating film in the first conductivity type channel MOSFET formation region;
Removing the resist by wet treatment;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 1,
Before the step of forming the gate insulating film,
A method of manufacturing a semiconductor device, comprising: forming a silicon oxynitride film in the first conductivity type channel MOSFET formation region and the second conductivity type channel MOSFET formation region of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 1,
The first conductivity type channel MOSFET is an N-channel MOSFET,
The second conductivity type channel MOSFET is a P-channel MOSFET;
The method of manufacturing a semiconductor device, wherein the first metal film is at least one selected from the group consisting of La, Dy, La ₂ O ₃ , and Dy ₂ O ₃ . In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 7,
The method for manufacturing a semiconductor device, wherein the gate insulating film is HfO ₂ or ZrO ₂ . In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the second metal layer is at least one selected from the group consisting of TiN, W, TaN, TaSiN, Ru, TiAl, and Al. A semiconductor device comprising a first conductivity type channel MOSFET and a second conductivity type channel MOSFET on a semiconductor substrate,
The first conductivity type channel MOSFET is:
A first gate insulating film containing a first metal on the semiconductor substrate;
A metal gate electrode made of a second metal provided on the first gate insulating film,
A concentration of the first metal in the first gate insulating film decreases from an interface between the first gate insulating film and the metal gate electrode made of the second metal toward the semiconductor substrate; and A profile having a maximum value in the first gate insulating film;
The second conductivity type channel MOSFET is:
A second gate insulating film formed on the semiconductor substrate;
A metal gate electrode made of a second metal provided on the gate insulating film,
The semiconductor device, wherein the second metal is at least one selected from the group consisting of TaSiN, Ru, TiAl, and Al. The semiconductor device according to claim 10.
The first gate insulating film in the first conductivity type channel MOSFET is:
A first insulating film provided on the semiconductor substrate;
A second insulating film provided on the first insulating film and having a dielectric constant higher than that of the first insulating film,
The concentration of the first metal decreases in the second insulating film from the interface between the second insulating film and the metal gate electrode toward the first insulating film, and thus the second insulating film. A semiconductor device having a profile that rises and forms a maximum value at an interface between a film and the first insulating film. The semiconductor device according to claim 10 or 11,
The second gate insulating film in the second conductivity type channel MOSFET is:
A first insulating film provided on the semiconductor substrate;
A semiconductor device comprising: a second insulating film provided on the first insulating film and having a dielectric constant higher than that of the first insulating film, and does not include the first metal. The semiconductor device according to claim 10,
The first conductivity type channel MOSFET is an N-channel MOSFET,
The second conductivity type channel MOSFET is a P-channel MOSFET;
The semiconductor device, wherein the first metal is at least one selected from the group consisting of La, Dy, La ₂ O ₃ , and Dy ₂ O ₃ . The semiconductor device according to claim 10,
The semiconductor device in which the first and second gate insulating films are HfO ₂ or ZrO ₂ .

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