JP2013258202A - Solid state imaging device and solid state imaging device driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging device and a solid state imaging device driving method which can prevent electron residual in a storage region while preventing reduction in sensitivity.SOLUTION: A solid state imaging device 1 comprises: a first conductivity type substrate 11; a gate insulation film 12 formed on a top face of the substrate 11; a second conductivity type storage region 13 for storing electric charge generated by photoelectric conversion in the substrate 11; a second conductivity type reading region 15 which is a region in the substrate 11 and to which electric charge stored in the storage region 13 is transferred; and a transfer gate 16 formed on a top face of the gate insulation film 12 between the storage region 13 and the reading region 15. In at least a partial period during a transfer period, the solid state imaging device 1 becomes a first state where a potential bottom of a channel region 161 exceeds a potential bottom of the storage region 13 and further exceeds reset potential which is potential of the reading region 15 just before the transfer period.

Description

  The present invention relates to a solid-state imaging device represented by a complementary metal oxide semiconductor (CMOS) image sensor, a charge-coupled device (CCD) image sensor, and the like, and a driving method of the solid-state imaging device.

  In recent years, solid-state imaging devices such as CCD image sensors and CMOS image sensors have been installed in various electronic devices equipped with imaging functions such as digital video cameras and digital still cameras, and scanners, facsimiles, and camera-equipped mobile phones. Has been. For example, a solid-state imaging device accumulates charges generated by photoelectric conversion of a photodiode formed in a substrate in an accumulation region that forms a part of the photodiode, and transfers it from the accumulation region to a readout region at a predetermined timing. Based on the generated charges, an output signal constituting image data is generated.

  An example of the structure and operation of a conventional solid-state imaging device (CMOS image sensor) will be described with reference to the drawings. FIG. 11 is a schematic cross-sectional view showing the structure of a conventional solid-state imaging device. FIG. 12 is a timing chart showing the operation of the solid-state imaging device shown in FIG.

As shown in FIG. 11, the solid-state imaging device 100 includes a substrate 101 made of a p-type semiconductor (hereinafter referred to as “p-type”), and a gate insulating film 102 made of an insulator formed on the upper surface of the substrate 101. A storage region 103 that is an n-type semiconductor (hereinafter referred to as “n-type”) region in the substrate 101 and stores electrons generated by photoelectric conversion in the substrate 101, and a p-type region in the substrate 101. A surface region 104 formed between the upper surface of the substrate 101 and the storage region 103; a read region 105 in which electrons accumulated in the storage region 103 are n-type regions in the substrate 101; and a conductor an upper surface a and accumulation region 103 and the transfer gate 106 which is given the transfer control signal phi _TX is formed between the read area 105 of the gate insulating film 102 made of, each of the regions 103 to 105 are formed It comprises a p-type isolation region 107 formed around the element region in the plate 101, a. Note that the concentration of the n-type impurity in the readout region 105 is higher than that in the accumulation region 103. Further, the concentration of the p-type impurity in the element isolation region 107 is higher than the concentration of the p-type impurity in the substrate 101.

Furthermore, the solid-state imaging device 100 includes a reset switch 121 supplies the reset potential V _RD to the read area 105 by the reset control signal phi _R by on / off applied is turned on with the switching control, the output control signal phi _An output transistor 122 which is an n-channel transistor whose _S is supplied to the gate and whose drain is electrically connected to the readout region 105, and an amplifier which amplifies the potential of the source of the output transistor 122 and outputs the output signal V _SIG Unit 123.

  In the solid-state imaging device 100, electrons generated by photoelectric conversion of a photodiode composed of the p-type substrate 101 and the surface region 104 and the n-type accumulation region 103 are accumulated in the accumulation region 103. At this time, since the surface region 104 is formed between the upper surface of the substrate 101 and the storage region 103 (becomes a buried photodiode), the upper surface of the substrate 101 and the storage region 103 are separated from each other. Therefore, generation of dark current or the like due to electrons trapped in the surface level of the upper surface of the substrate 101 can be suppressed.

Further, as shown in FIG. 12, the solid-state imaging device 100 is driven by the operation of the output period T _S. The solid-state imaging device 100, in this output period T _S, transfers the stored in the storage area 103 electrons in the read area 105, and outputs an output signal V _SIG corresponding to electrons transferred in the read area 105. As shown in FIG. 12, in the output period T _S , the output transistor 122 is turned on when the output control signal φ _S is at a high level.

In output period T _S, initially, in the reset period T _R, by the reset control signal phi _R goes high, the reset switch 121 is turned on. As a result, the read area 105 becomes the reset potential V _RD . Next, in the first transfer period T _A, by a reset control signal phi _R goes low, the reset switch 121 is turned off. At this time, an output signal V _SIG that can be used as a reference corresponding to the potential (reset potential V _RD ) before the electrons are transferred to the reading region 105 is output.

Next, in the transfer period T _TX , the transfer control signal φ _TX is at a high level, so that an inversion layer is formed in a region (channel region 1061) in the substrate 101 immediately below the transfer gate 106. As a result, electrons are transferred from the storage region 103 to the read region 105 through the inversion layer. Finally, by the second transfer period T _B Oite, transfer control signal phi _TX goes low, the inversion layer in the channel region 1061 disappears. At this time, an output signal V _SIG corresponding to the potential of the readout region 105 to which electrons have been transferred is output.

By the way, in such a solid-state image sensor 100, in order to reduce power consumption, it is required to lower the reset potential _VRD . Further, as described above, for the purpose of suppressing dark current and the like, the embedded photodiode formed by the surface region 104 and the storage region 103 is an n-type in which the storage region 103 is deeply embedded if charges are electrons. , The bottom of the potential (the limit potential at which charges can exist, the upper limit potential for electrons, the lower limit potential for holes, and so on) is deepened. Note that the deep bottom of the potential means that the potential at the bottom of the potential is high, and that the bottom of the potential is low means that the potential at the bottom of the potential is low (the same applies hereinafter).

Then, definitive when transferring electrons to the read area 105 from the storage area 103, a proper range of the bottom of the potential of the channel region 1061, since between the bottom and the reset potential V _RD of the potential of the accumulation region 103 is narrowed, It is necessary to control the bottom of the potential of the channel region 1061 with high accuracy. If the accuracy of the control of the bottom of the potential of the channel region 1061 becomes insufficient, electrons remaining in the storage region 103 without being transferred to the reading region 105 are generated, and an afterimage may be generated in the image data. .

This problem will be described with reference to the drawings. FIG. 13 is a graph showing potential and potential states when the solid-state imaging device shown in FIG. 11 performs the operation shown in FIG. Incidentally, FIG. 13 (a) is a graph showing the state of electric potential and the potential during the reset period T _R. FIG. 13B is a graph showing the potential and the state of the potential during the transfer period _TTX .

As shown in FIG. 13 (a), the reset period _{T R,} since the shallow bottom [psi _OFF of the potential in the channel region 1061, electronic Q1 remains stored in the storage area 103. At this time, the potential V _FD1 of the reading region 105 becomes the reset potential V _RD as described above.

Next, as shown in FIG. 13B, when the transfer period T _TX is reached, the bottom Ψ _ON of the potential of the channel region 1061 becomes deep, and thus the electrons Q2 are transferred to the read region 105. At this time, it is necessary to keep the bottom Ψ _ON of the potential of the channel region 1061 between the bottom Ψ _PD of the potential of the accumulation region 103 and the reset potential V _RD (appropriate range). Since it is narrow, it is difficult to keep the bottom Ψ _ON of the potential of the channel region 1061 within this appropriate range. For example, as shown in FIG. 13B, when the potential bottom Ψ _ON of the channel region 1061 becomes shallower than the potential bottom Ψ _PD of the accumulation region 103, electrons ΔQ corresponding to the difference are accumulated in the accumulation region 103. And an afterimage occurs in the image data.

  With respect to this problem, in Patent Document 1, when electrons are transferred from the storage region 103 to the read region 105, the electrons remain in the storage region 103 by booting up both the transfer gate 106 and the read region 105. There has been proposed a solid-state imaging device that prevents the occurrence of afterimages in image data.

  A solid-state imaging device proposed in Patent Document 1 will be described with reference to the drawings. FIG. 14 is a schematic cross-sectional view showing the structure of a conventional solid-state imaging device proposed in Patent Document 1. In FIG. FIG. 15 is a timing chart showing the operation of the solid-state imaging device of FIG. In addition, about the solid-state image sensor 100a proposed by the patent document 1 demonstrated below, the same code | symbol is attached | subjected about the part similar to the above-mentioned solid-state image sensor 100, and the detailed description is abbreviate | omitted.

As shown in FIG. 14, the solid-state imaging device 100a includes a substrate 101, a gate insulating film 102, a storage region 103, a surface region 104, a readout region 105, a transfer gate 106, an element isolation region 107, and a reset. A switch 121, an output transistor 122, an amplifier 123, and a bootup capacitor 131 having one end electrically connected to the readout region 105 and the other end supplied with a bootup signal _φBU . In the solid-state imaging device 100a, the transfer gate 106 and the readout region 105 are capacitively coupled (having a boosting capacitor 132).

Further, as shown in FIG. 15, the solid-state imaging device 100a repeats the operation of the output period _{T S.} The output period _{T S,} the reset period _{T R,} the first transfer period _{T A,} the transfer period _{T TX,} and the second transfer period _{T B,} but includes, respectively. However, this transfer period T _TX includes a boot-up period T _BU . In the boot-up period T _BU , the boot-up signal φ _BU is at a high level, whereby the potential of the read region 105 is booted up via the boot-up capacitor 131 and the potential of the transfer gate 106 is further increased via the boost capacitor 132. Booted up.

A potential and a potential state when the solid-state imaging device 100a performs the operation of FIG. 15 will be described with reference to the drawings. FIG. 16 is a graph showing potential and potential states when the solid-state imaging device shown in FIG. 14 performs the operation shown in FIG. Incidentally, FIG. 16 (a) is a graph showing the state of electric potential and the potential during the reset period T _R. FIG. 16B is a graph showing the potential and potential states during the transfer period T _TX and before the boot-up period T _BU . FIG. 16C is a graph showing a potential and a potential state during the boot-up period T _BU .

As shown in FIG. 16 (a), the reset period _{T R,} since the shallow bottom [psi _OFF of the potential in the channel region 1061, electronic Q1 remains stored in the storage area 103. At this time, the potential V _FD1 of the reading region 105 becomes the reset potential V _RD as described above.

Next, as shown in FIG. 16B, when the transfer period T _TX is _reached, the potential bottom Ψ _ON1 of the channel region 1061 becomes deep, and thus the electron Q2 is transferred to the read region 105. Note that FIG. _16B illustrates a case where the potential bottom Ψ _ON1 of the channel region 1061 is shallower than the potential bottom Ψ _PD of the accumulation region 103. In this case, electrons ΔQ corresponding to the difference between the potential bottom Ψ _ON1 of the channel region 1061 and the potential bottom Ψ _PD of the accumulation region 103 remain in the accumulation region 103.

However, as shown in FIG. 16C, when the boot-up period T _BU is reached, the potential of the transfer region 106 and the potential of the readout region 105 are booted up, so that the bottom of the potential of the channel region 1061 is deep. becomes (become [psi _ON2 from [psi _ON1), the potential of the read area 105 becomes high _{(becomes V FD3} from _{V FD2).} As a result, the above-described appropriate range (between the bottom Ψ _PD of the potential of the storage region 103 and the reset potential V _RD ) is expanded, and the potential bottom Ψ _ON2 of the potential of the channel region 1061 can be easily kept within this proper range. It becomes possible. Therefore, in the solid-state imaging device 100a, it is possible to prevent an afterimage from being generated in the image data by preventing electrons from remaining in the storage region 103 and transferring the electrons Q3 to the reading region 105.

JP 2006-42120 A

  However, in the solid-state imaging device 100a proposed in Patent Document 1 (see FIG. 14), another problem occurs due to the boot-up capacitor 131 and the boost capacitor 132 connected to the readout region 105. This problem will be specifically described below.

The bootup capacitor 131 and the booster capacitor 132 are connected in parallel to the fixed potential when viewed from the readout region 105. Therefore, when the capacitance value of the readout region 105 in the solid-state imaging device 100 (see FIG. 11) is C ₁ , the capacitance value of the boot-up capacitor 131 is C _BU1 , and the capacitance value of the boosting capacitor 132 is C _BU2 , the solid-state imaging device 100 a ( capacitance value C ₂ of the read area 105 in FIG. 14 reference), as shown in the following formula (1), the ones obtained by summing the respective capacity.

C ₂ = C ₁ + C _BU1 + C _BU2 (1)

C _BU1 and C _BU2 in the above formula (1) need to be sufficiently larger than C _{1 in} order to obtain the above-described boot-up effect. Accordingly, the solid-state imaging device 100a (see FIG. 14) has a significantly larger capacity of the readout region 105 than the solid-state imaging device 100 (see FIG. 11). When the capacitance of the readout region 105 is significantly increased, the voltage (= charge / capacitance) input to the amplifying unit 123 is significantly decreased, the sensitivity of the solid-state imaging device 100a (see FIG. 14) is decreased, and an obtained image is obtained. Since data deteriorates, it becomes a problem.

  Therefore, an object of the present invention is to provide a solid-state imaging device and a driving method of the solid-state imaging device that can prevent the remaining of electrons in the accumulation region while preventing a decrease in sensitivity.

  In order to achieve the above object, the present invention provides a substrate made of a first conductivity type semiconductor, a gate insulating film made of an insulator formed on the upper surface of the substrate, and a second conductivity different from the first conductivity type. A region in the substrate made of a semiconductor of a type, a storage region for storing charges generated by photoelectric conversion in the substrate, and a region in the substrate made of a semiconductor of the second conductivity type, the storage region And a transfer gate formed on the upper surface of the gate insulating film and between the storage region and the read region, and during the transfer period, The charge accumulated in the accumulation region is transferred to the readout region via a channel region that is a region in the substrate that is directly below the transfer gate, and the channel region is in at least a part of the transfer period. The poten Provided is a solid-state imaging device characterized in that the bottom of the signal exceeds the bottom of the potential of the storage region and further exceeds the reset potential that is the potential of the readout region immediately before the transfer period. To do.

  According to this solid-state imaging device, it is possible to transfer the charge in the accumulation region to the channel region and the read region in a period in which the first state during the transfer period is realized. Furthermore, since the difference between the bottom of the potential of the storage region and the bottom of the potential of the channel region can be increased at this time, the charge in the storage region can be transferred to the channel region and the readout region at high speed. Become. Further, since the first state can be realized only by applying a potential exceeding a predetermined magnitude to the transfer gate, it can be easily realized without requiring highly accurate control.

  The “substrate made of the first conductivity type semiconductor” means that the portion of the substrate where the element structure is formed is made of the first conductivity type semiconductor, and the whole is the first conductivity type semiconductor. The substrate is not limited to a substrate composed of a first conductivity type semiconductor (for example, by implanting a first conductivity type impurity into a substrate composed entirely of a second conductivity type semiconductor). Naturally, a substrate on which a well made of a semiconductor is formed is also included.

  Furthermore, in the solid-state imaging device having the characteristics described above, the bottom of the potential of the channel region is different from the bottom of the potential of the accumulation region during at least a part of the transfer period and after the first state. It is preferable that the second state is between the reset potential.

  According to this solid-state imaging device, the charge in the channel region can be transferred to the reading region instead of the accumulation region. Therefore, channel charge injection can be prevented.

  Furthermore, the solid-state imaging device having the above characteristics further includes a transfer control signal generation unit that generates a transfer control signal to be applied to the transfer gate, and the transfer control signal generation unit delays a fluctuation in the level of the transfer control signal. The transfer control signal generation unit includes a delay element, and the transfer control signal generation unit realizes the second state by changing the level of the transfer control signal while delaying using the delay element after entering the first state. May be.

  Specifically, for example, the transfer control signal generation unit includes a first transistor in which a first control signal is supplied to a control electrode, a first potential is supplied to the first electrode, and a second electrode is connected to an output node. The second control signal is supplied to one end, the first capacitor is connected to the output node at the other end, the third control signal is supplied to the control electrode, and the second potential is supplied to the first electrode, A second transistor having a second electrode connected to the output node, a third transistor to which a fourth control signal is supplied to the control electrode and the second potential is supplied to the first electrode, and one end of the third transistor is the third transistor A first load connected to the second electrode of the transistor and having the other end connected to the output node, and the transfer control signal may be output from the output node.

  According to this solid-state imaging device, the second state can be continuously realized in the process of changing the level of the transfer control signal. Therefore, it becomes possible to eliminate the need to strictly select and control the first potential. Further, since the level of the transfer control signal can be generated by combining the first potential and the second control signal, the first state can be realized without unnecessarily increasing (or decreasing) the first potential. Is possible.

  The solid-state imaging device of the above feature further includes a transfer control signal generation unit that generates a transfer control signal to be applied to the transfer gate, wherein the transfer control signal generated by the transfer control signal generation unit is in the first state. It is possible to have at least a period during which the first level that realizes the second state and a period during which the second level that realizes the second state continues.

  Specifically, for example, the transfer control signal generation unit includes a first transistor in which a first control signal is supplied to a control electrode, a first potential is supplied to the first electrode, and a second electrode is connected to an output node. The second control signal is supplied to one end, the first capacitor is connected to the output node at the other end, the third control signal is supplied to the control electrode, and the second potential is supplied to the first electrode, The second electrode is connected to the output node, the fourth control signal is supplied to the control electrode, the first potential is supplied to the first electrode, and the second electrode is connected to the output node. A third transistor, and the transfer control signal may be output from the output node.

  According to this solid-state imaging device, the circuit configuration can be simplified, and the time for which the second state is continued can be determined by the predetermined time duration of the fourth control signal. Therefore, it is possible to accurately transfer the charge in the channel region to the readout region. Further, since the level of the transfer control signal can be generated by combining the first potential and the second control signal, the first state can be realized without unnecessarily increasing (or decreasing) the first potential. Is possible.

  Furthermore, in the solid-state imaging device having the above characteristics, when the first conductivity type is p-type, the second conductivity type is n-type, and the charge is an electron, the first state is that the bottom of the potential of the channel region is The bottom of the potential of the accumulation region and the state deeper than the reset potential are preferable.

  According to this solid-state imaging device, it is possible to transfer all electrons from the accumulation region to the channel region and the readout region.

  Furthermore, the solid-state imaging device having the above characteristics may further include a surface region formed between the upper surface of the substrate and the accumulation region, which is a region in the substrate made of the first conductivity type semiconductor. Good.

  According to this solid-state imaging device, even if the space between the bottom of the potential of the accumulation region and the reset potential (appropriate range) becomes narrow due to the provision of the surface region to suppress dark current and the like, regardless of this By making the bottom of the potential of the channel region exceed the bottom of the potential of the storage region and the reset potential, it is possible to transfer all charges from the storage region to the channel region and the readout region.

  The present invention also includes a substrate made of a first conductivity type semiconductor, a gate insulating film made of an insulator formed on the upper surface of the substrate, and a second conductivity type semiconductor different from the first conductivity type. A region in the substrate, an accumulation region for accumulating charges generated by photoelectric conversion in the substrate, and a region in the substrate composed of the second conductivity type semiconductor, the region accumulated in the accumulation region A method for driving a solid-state imaging device, comprising: a readout region to which charges are transferred; and a transfer gate formed on the upper surface of the gate insulating film and between the accumulation region and the readout region. During the period, the charge accumulated in the accumulation region is transferred to the readout region via a channel region which is a region in the substrate immediately below the transfer gate, and at least a part of the transfer period The channel A first state in which the bottom of the potential of the region exceeds the bottom of the potential of the accumulation region and further exceeds the reset potential that is the potential of the readout region immediately before the transfer period. A driving method is provided.

  According to this method for driving a solid-state imaging device, it is possible to transfer the charge in the accumulation region to the channel region and the readout region in a period in which the first state in the transfer period is realized. Furthermore, since the difference between the bottom of the potential of the storage region and the bottom of the potential of the channel region can be increased at this time, the charge in the storage region can be transferred to the channel region and the readout region at high speed. Become. Further, since the first state can be realized only by applying a potential exceeding a predetermined magnitude to the transfer gate, it can be easily realized without requiring highly accurate control.

  According to the solid-state imaging device and the driving method of the solid-state imaging device having the features described above, it is possible to transfer all charges from the accumulation region to the channel region and the readout region without increasing the capacity of the readout region. Therefore, it is possible to prevent the remaining of electrons in the accumulation region while preventing a decrease in sensitivity.

The typical sectional view shown about an example of the basic structure of the solid-state image sensing device concerning the embodiment of the present invention. The circuit diagram shown about the transfer control signal generation part with which the solid-state image sensing device concerning a 1st embodiment of the present invention is provided. 4 is a timing chart showing the operation of the solid-state imaging device according to the first embodiment of the present invention. 4 is a graph showing a potential and a potential state when the solid-state imaging device according to the first embodiment of the present invention performs the operation shown in FIG. The circuit diagram shown about the transfer control signal generation part with which the solid-state image sensing device concerning a 2nd embodiment of the present invention is provided. The timing chart shown about operation | movement of the solid-state image sensor which concerns on 2nd Embodiment of this invention. FIG. 7 is a graph showing potential and potential states when the solid-state imaging device according to the second embodiment of the present invention performs the operation shown in FIG. 6. The circuit diagram shown about the transfer control signal production | generation part with which the solid-state image sensor which concerns on 3rd Embodiment of this invention is provided. The timing chart shown about operation of the solid-state image sensing device concerning a 3rd embodiment of the present invention. The graph shown about the state of an electric potential and potential in case the solid-state image sensor which concerns on 3rd Embodiment of this invention performs the operation | movement shown in FIG. Schematic sectional view showing the structure of a conventional solid-state imaging device. The timing chart shown about operation | movement of the solid-state image sensor shown in FIG. FIG. 13 is a graph showing potential and potential states when the solid-state imaging device shown in FIG. 11 performs the operation shown in FIG. 12. FIG. 6 is a schematic cross-sectional view showing the structure of a conventional solid-state imaging device proposed in Patent Document 1. The timing chart shown about operation | movement of the solid-state image sensor shown in FIG. FIG. 15 is a graph showing potential and potential states when the solid-state imaging device shown in FIG. 14 performs the operation shown in FIG.

  Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings. In the following, for the sake of concrete explanation, the solid-state imaging device according to the embodiment of the present invention is a CMOS image sensor, and an n-type accumulation region and a readout region are formed in a p-type substrate. It illustrates about.

  The “p-type substrate” refers to a substrate in which the portion where the element structure is formed is p-type, and is not limited to only a substrate that is p-type as a whole, and a substrate in which the well is p-type. (For example, a substrate in which a p-type well is formed by implanting a p-type impurity into a substrate that is entirely n-type) is naturally included. However, in each drawing referred to in the following description, the entire substrate is illustrated as if it is p-type.

  Further, silicon can be used as a material for the substrate. In this case, boron or the like can be used as the p-type impurity. In this case, phosphorus, arsenic, or the like can be used as the n-type impurity. Further, these impurities can be implanted into the substrate by applying a method such as ion implantation.

<Basic structure of solid-state image sensor>
First, an example of a basic structure of a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view illustrating an example of a basic structure of a solid-state imaging device according to an embodiment of the invention.

As shown in FIG. 1, the solid-state imaging device 1 is a p-type substrate 11, a gate insulating film 12 made of an insulator formed on the upper surface of the substrate 11, and an n-type region in the substrate 11. An accumulation region 13 for accumulating electrons generated by photoelectric conversion therein, a p-type region in the substrate 11, a surface region 14 formed between the upper surface of the substrate 11 and the accumulation region 13, A transfer control signal formed between the storage region 13 and the readout region 15, which is an n-type region, which is an upper surface of the gate insulating film 12 made of a conductor, and to which the electrons stored in the storage region 13 are transferred. A transfer gate 16 to which φ _TX is provided, and a p-type element isolation region 17 formed around the element region in the substrate 11 on which the regions 13 to 15 are formed. Note that the concentration of the n-type impurity in the readout region 15 is higher than that in the accumulation region 13. Further, the concentration of the p-type impurity in the element isolation region 17 is higher than the concentration of the p-type impurity in the substrate 11.

Furthermore, the solid-state imaging device 1, the reset transistor 21 resets the control signal phi _R is an n-channel transistor whose source is given reset potential V _RD to the drain is electrically connected to the read area 15 with applied to the gate When the output control signal phi _S is the output transistor 22 is an n-channel transistor whose drain is electrically connected to the read area 15 with applied to the gate, amplifies and outputs the signal to the potential of the source of the output transistor 22 And an amplification unit 23 that outputs V _SIG .

  In the solid-state imaging device 1, electrons generated by photoelectric conversion of a photodiode composed of the p-type substrate 11 and the surface region 14 and the n-type accumulation region 13 are accumulated in the accumulation region 13. At this time, since the surface region 14 is formed between the upper surface of the substrate 11 and the storage region 13 (becomes a buried photodiode), the upper surface of the substrate 11 and the storage region 13 are separated from each other. Therefore, generation of dark current or the like due to electrons trapped in the surface level of the upper surface of the substrate 11 can be suppressed.

  The surface region 14 is not necessarily provided, but is preferably provided from the viewpoint of suppressing generation of dark current and the like. The element isolation region 17 is not limited to a p-type semiconductor, and may be an insulator, for example.

<First Embodiment>
Next, the solid-state imaging device according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram illustrating a transfer control signal generation unit included in the solid-state imaging device according to the first embodiment of the present invention. Note that the solid-state imaging device according to the first embodiment of the present invention has, for example, the basic structure shown in FIG. 1 and includes a transfer control signal generation unit 3a shown in FIG.

As shown in FIG. 2, the transfer control signal generating section 3a, gate connected to a first electric potential V _MID is supplied source is a positive potential to the drain along with the first control signal phi _TX1 is supplied the output node N _TX A first transistor 31 that is an n-channel transistor, a first capacitor 32 having one end 321 supplied with the second control signal _{φTX2 and the} other end 322 connected to the output node N _TX , and a third connected to the gate. comprising a second transistor 33 whose drain is supplied with the ground potential to the source together with a control signal phi _TX3 is applied is connected to the output node N _TX, the. In the transfer control signal generation unit 3a, the transfer control signal _φTX is output from the output node _NTX .

  Next, the operation of the solid-state imaging device according to the first embodiment of the present invention including the transfer control signal generation unit 3a will be described with reference to the drawings. FIG. 3 is a timing chart showing the operation of the solid-state imaging device according to the first embodiment of the present invention.

As shown in FIG. 3, the solid-state imaging device according to a first embodiment of the present invention is driven by operation of the output period T _S. Solid-state imaging device according to a first embodiment of the present invention, in the output period T _S, transfers the electrons accumulated in the accumulation region 13 in the read area 15, corresponding to the electrons transferred to the read area 15 output The signal V _SIG is output. As shown in FIG. 3, in the output period T _S , the output transistor 22 is turned on when the output control signal φ _S is at a high level.

In output period T _S, initially, in the reset period T _R, by the reset control signal phi _R goes high, the reset switch 21 is turned on. As a result, the potential V _FD of the read region 15 becomes the reset potential V _RD . Next, in the first transfer period T _A, by a reset control signal phi _R goes low, the reset switch 21 is turned off. At this time, an output signal V _SIG that can be used as a reference corresponding to the potential (reset potential V _RD ) before the electrons are transferred to the readout region 15 is output.

And before the start of the output period _{T S,} in the first transfer period _{T A} and the reset period _{T R,} the first control signal phi _TX1 low level (first transistor 31 is off), the second control signal phi _TX2 low level The third control signal _φTX3 is at a high level (the second transistor 33 is turned on). Thus, in these periods, the potential of the output node N _TX (level transfer control signal phi _TX) is to become the V _{OFF (ground} potential), the electrons in the read area 15 from the storage area 13 is not transferred.

Next, when the transfer period T _TX is started, the first control signal φ _TX1 is at a high level (the first transistor 31 is on), and the third control signal φ _TX3 is at a low level (the second transistor 33 is off). become. Therefore, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) becomes the first potential V _MID , and an inversion layer is formed in a region (channel region 161) in the substrate 11 immediately below the transfer gate 16. As a result, electrons are transferred from the accumulation region 13 to the read region 15 through the inversion layer, and the potential V _{FD of the} read region 15 is lowered according to the transferred electrons. At this time, the first capacitor 32 is charged by applying the first potential V _MID to the other end 322.

After the start of the transfer period _TTX , at the timing P1, the first control signal _φTX1 becomes low level (the first transistor 31 is off). Thereafter, at timing P2, the second control signal _φTX2 becomes high level. At this time, since the potential of the other end 322 is pushed up through the first capacitor 32, the potential of the output node _{N TX} (level transfer control signal phi _TX) is larger _{V ON} than the first potential _{V MID.}

Finally, the second transfer period _{T B} Oite, the second control signal phi _TX2 goes low, the third control signal phi _TX3 goes high (second transistor 33 is turned on). Thus, the potential of the output node _{N TX} (level transfer control signal phi _TX) becomes _{V OFF,} the inversion layer in the channel region 161 disappears. Then, an output signal V _SIG corresponding to the potential V _FD of the reading region 15 to which electrons are transferred is output.

Further, the state of the potential and the potential when the solid-state imaging device according to the first embodiment of the present invention performs the operation of FIG. 3 will be described with reference to the drawings. FIG. 4 is a graph showing a potential and a potential state when the solid-state imaging device according to the first embodiment of the present invention performs the operation shown in FIG. 4 (a) is a graph showing the state of electric potential and the potential during the reset period T _R. FIG. 4B is a graph showing a potential and a potential state during the transfer period T _TX and after the timing P2. Further, FIG. 4 (c) is a graph showing the state of electric potential and the potential at the time of transition of the transfer period T _TX and second transfer period T _B. Further, FIG. 4 (d) is a graph showing the state of the potential and the potential at the second transfer period T in _B.

As shown in FIG. 4 (a), the reset period _{T R,} since the shallow bottom [psi _OFF of the potential in the channel region 161, electrons Q1 remains stored in the storage area 13. At this time, the potential V _FD1 of the reading region 15 becomes the reset potential V _RD as described above.

Next, as illustrated in FIG. 4B, when the timing P _< b _{> 2} of the transfer period T _TX is reached, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) is V _ON , so that the channel region 161 The bottom Ψ _{ON1 of the} potential is deepened. At this time, the bottom Ψ _ON1 of the potential of the channel region 161 is set deeper than the bottom Ψ _PD of the potential of the accumulation region 13 and further deeper than the reset potential V _RD (first state).

In this state, the electrons Q2 in the storage region 13 can be transferred to the channel region 161 and the reading region 15 without any remaining. Further, in this state, the bottom [psi _ON1 of potential accumulation region 13, it is possible to increase the difference between the bottom [psi _PD of the potential of the channel region 161, the electronic Q2 accumulation region 13, the channel region 161 and a read It becomes possible to transfer to the area 15 at high speed.

Further, the transfer of electrons in the state shown in FIG. 4B can be realized simply by applying a high potential to the transfer gate 16, and therefore can be easily realized without requiring high-precision control. . For this reason, even if the distance (appropriate range) between the bottom Ψ _PD of the potential of the storage region 13 and the reset potential V _RD becomes narrow due to the provision of the surface region 14 to suppress dark current and the like as described above, Regardless of whether the potential bottom Ψ _ON1 of the channel region 161 is deeper than the potential bottom Ψ _PD and the reset potential V _RD of the potential of the storage region 13, the channel region 161 and the readout region from the storage region 13. It is possible to transfer all the electrons Q2 to 15.

Further, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) V _ON necessary for realizing the state shown in FIG. 4B is obtained by using the first potential V _MID and the second control signal φ _TX2 . Can be generated in combination. Therefore, the state shown in FIG. 4B can be realized without unnecessarily increasing the first potential V _MID . Specifically, for example, the first potential V _MID may be lower than the high level of various control signals such as the reset control signal φ _R , the output control signal φ _S , the first control signal φ _TX1 , and the second control signal φ _TX2. .

  As described above, in the solid-state imaging device according to the first embodiment of the present invention, it is possible to transfer all the electrons from the accumulation region 13 to the channel region 161 and the readout region 15 without increasing the capacity of the readout region 15. become. Therefore, the solid-state imaging device according to the first embodiment of the present invention can prevent the remaining of electrons in the accumulation region 13 while preventing a decrease in sensitivity.

By the way, in the solid-state imaging device according to the first embodiment of the present invention, there is a concern that channel charge injection may occur as shown in FIGS. 4C and 4D. Specifically, as shown in FIG. 4 (c), when the transition to the transfer period _{T TX} from the second transfer period _{T B,} the bottom [psi _OFF the potential of the channel region 161, the bottom of the potential of the accumulation region 13 When it suddenly becomes shallower than Ψ _PD , electrons Q41 returned to the storage region 13 may be generated as shown in FIG.

  Therefore, in the following, in the second and third embodiments of the present invention, which not only prevents the remaining of electrons in the storage region 13 while preventing a decrease in sensitivity, but also prevents the channel charge injection. Each of the solid-state imaging devices will be described.

Second Embodiment
Next, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram illustrating a transfer control signal generation unit included in the solid-state imaging device according to the second embodiment of the present invention. Note that the solid-state imaging device according to the second embodiment of the present invention has, for example, the basic structure shown in FIG. 1 and includes a transfer control signal generation unit 3b shown in FIG. In addition, in the solid-state imaging device according to the second embodiment of the present invention described below, the same reference numerals are given to the same parts as those of the above-described solid-state imaging device according to the first embodiment of the present invention, and the details thereof are described. Description is omitted.

As shown in FIG. 5, the transfer control signal generator 3b is provided with the first transistor 31, the first capacitor 32, the second transistor 33, the gate to which the fourth control signal _φTX4 is applied, and the source having the ground potential. It comprises a third transistor 34 to be supplied, the first load 35 (delay element) and the other end 352 is connected to the output node _{N TX} one end 351 is connected to the drain of the third transistor 34. In the transfer control signal generation unit 3b, the transfer control signal _φTX is output from the output node _NTX .

  Next, the operation of the solid-state imaging device according to the second embodiment of the present invention including the transfer control signal generation unit 3b will be described with reference to the drawings. FIG. 6 is a timing chart showing the operation of the solid-state imaging device according to the second embodiment of the present invention.

As shown in FIG. 6, the solid-state imaging device according to a second embodiment of the present invention is driven by operation of the output period T _S. Solid-state imaging device according to a second embodiment of the present invention, in the output period T _S, transfers the electrons accumulated in the accumulation region 13 in the read area 15, corresponding to the electrons transferred to the read area 15 output The signal V _SIG is output. As shown in FIG. 6, in the output period T _S , the output control signal φ _S becomes a high level, so that the output transistor 22 is turned on.

In output period T _S, initially, in the reset period T _R, by the reset control signal phi _R goes high, the reset switch 21 is turned on. As a result, the potential V _FD of the read region 15 becomes the reset potential V _RD . Next, in the first transfer period T _A, by a reset control signal phi _R goes low, the reset switch 21 is turned off. At this time, an output signal V _SIG that can be used as a reference corresponding to the potential (reset potential V _RD ) before the electrons are transferred to the readout region 15 is output.

And before the start of the output period _{T S,} in the first transfer period _{T A} and the reset period _{T R,} the first control signal phi _TX1 low level (first transistor 31 is off), the second control signal phi _TX2 low level The third control signal _φTX3 is at a high level (second transistor 33 is on), and the fourth control signal _φTX4 is at a low level (third transistor 34 is off). Thus, in these periods, the potential of the output node N _TX (level transfer control signal phi _TX) is to become the V _{OFF (ground} potential), the electrons in the read area 15 from the storage area 13 is not transferred.

Next, when the transfer period T _TX is started, the first control signal φ _TX1 is at a high level (the first transistor 31 is on), and the third control signal φ _TX3 is at a low level (the second transistor 33 is off). become. Therefore, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) becomes the first potential V _MID , and an inversion layer is formed in a region (channel region 161) in the substrate 11 immediately below the transfer gate 16. As a result, electrons are transferred from the accumulation region 13 to the read region 15 through the inversion layer, and the potential V _{FD of the} read region 15 is lowered according to the transferred electrons. At this time, the first capacitor 32 is charged by applying the first potential V _MID to the other end 322.

After the start of the transfer period _TTX , at the timing P1, the first control signal _φTX1 becomes low level (the first transistor 31 is off). Thereafter, at timing P2, the second control signal _φTX2 becomes high level. At this time, since the potential of the other end 322 is pushed up through the first capacitor 32, the potential of the output node _{N TX} (level transfer control signal phi _TX) is larger _{V ON} than the first potential _{V MID.}

Thereafter, at timing P3, the fourth control signal _φTX4 becomes high level (the third transistor 34 is turned on). Then, current flows out from the output node N _TX through the first load 35 and the third transistor 34 until the potential of the output node N _TX becomes the ground potential.

At this time, assuming that the resistance value of the first load 35 is R _TX and the capacitance value of the first capacitor 32 is C _TX , the potential of the output node N _TX changes with a slope determined by a time constant τ _TX = R _TX × C _TX. To do. That is, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) gradually decreases from V _ON to V _OFF . In other words, the potential of the output node _{N TX} (level transfer control signal phi _TX) is a period of _time, a level between _{V ON} and _{V OFF.} As a result, the inversion layer of the channel region 161 disappears.

Finally, the second transfer period _{T B} Oite, the second control signal phi _TX2 goes low, the third control signal phi _TX3 goes high (second transistor 33 is turned on), the fourth control signal phi _TX4 is at a low level (third transistor 34 is on). Thus, the potential of the output node _{N TX} (level transfer control signal phi _TX) is _{V OFF.} Then, an output signal V _SIG corresponding to the potential V _FD of the reading region 15 to which electrons are transferred is output.

Further, the potential and the state of potential when the solid-state imaging device according to the second embodiment of the present invention performs the operation of FIG. 6 will be described with reference to the drawings. FIG. 7 is a graph showing potential and potential states when the solid-state imaging device according to the second embodiment of the present invention performs the operation shown in FIG. Incidentally, FIG. 7 (a) is a graph showing the state of electric potential and the potential during the reset period T _R. FIG. 7B is a graph showing the potential and potential state during the transfer period _TTX and after the timing P2. FIG. 7C is a graph showing a potential and a potential state during the transfer period T _TX and after the timing P3. Further, FIG. 7 (d) is a graph showing the state of the potential and the potential at the second transfer period T in _B.

As shown in FIG. 7 (a), the reset period _{T R,} since the shallow bottom [psi _OFF of the potential in the channel region 161, electrons Q1 remains stored in the storage area 13. At this time, the potential V _FD1 of the reading region 15 becomes the reset potential V _RD as described above.

Next, as shown in FIG. 7B, when the timing P2 of the transfer period T _TX is reached, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) becomes V _ON , so that the channel region 161 The bottom Ψ _{ON1 of the} potential is deepened. At this time, the bottom Ψ _ON1 of the potential of the channel region 161 is set deeper than the bottom Ψ _PD of the potential of the accumulation region 13 and further deeper than the reset potential V _RD (first state). In this state, as in the solid-state imaging device according to the first embodiment of the present invention, the electrons Q2 in the storage region 13 can be transferred to the channel region 161 and the readout region 15 at high speed without remaining. become.

Furthermore, in the solid-state imaging device according to the second embodiment of the present invention, as described above, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) gradually decreases from V _ON to V _OFF. . Therefore, as shown in FIG. 7C, a state (second state) in which the bottom Ψ _ON2 of the potential of the channel region 161 is deeper than the bottom Ψ _PD of the potential of the accumulation region 13 and shallower than the reset potential V _RD. Will be realized continuously. In this state, the electrons Q31 in the channel region 161 are transferred not to the storage region 13 but to the reading region 15. Therefore, channel charge injection can be prevented.

Since the solid-state imaging device according to the second embodiment of the present invention passes through the state (second state) shown in FIG. 7C, as shown in FIG. 7D, the transfer period T _TX ends. Later, it is possible to transfer all the electrons Q4 to the reading area 15.

<Third Embodiment>
Next, a solid-state imaging device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram illustrating a transfer control signal generation unit included in the solid-state imaging device according to the third embodiment of the present invention. Note that the solid-state imaging device according to the third embodiment of the present invention has, for example, the basic structure shown in FIG. 1 and includes a transfer control signal generator 3c shown in FIG. Further, in the solid-state imaging device according to the third embodiment of the present invention described below, the same reference numerals are given to the same parts as those of the above-described solid-state imaging device according to the first embodiment of the present invention, and the detailed description thereof is omitted. Description is omitted.

As shown in FIG. 8, the transfer control signal generation unit 3c is provided with the first transistor 31, the first capacitor 32, the second transistor 33, the fourth control signal _φTX4 at the gate, and the first potential at the drain. A third transistor 341 to which V _MID is supplied and whose source is connected to the output node N _TX . In the transfer control signal generation unit 3c, the transfer control signal _φTX is output from the output node _NTX .

  Next, the operation of the solid-state imaging device according to the third embodiment of the present invention including the transfer control signal generation unit 3c will be described with reference to the drawings. FIG. 9 is a timing chart showing the operation of the solid-state imaging device according to the third embodiment of the present invention.

As shown in FIG. 9, the solid-state imaging device according to a third embodiment of the present invention is driven by operation of the output period T _S. A solid-state imaging device according to a third embodiment of the present invention, in the output period T _S, transfers the electrons accumulated in the accumulation region 13 in the read area 15, corresponding to the electrons transferred to the read area 15 output The signal V _SIG is output. As shown in FIG. 9, in the output period T _S , the output transistor 22 is turned on when the output control signal φ _S becomes high level.

In output period T _S, initially, in the reset period T _R, by the reset control signal phi _R goes high, the reset switch 21 is turned on. As a result, the potential V _FD of the read region 15 becomes the reset potential V _RD . Next, in the first transfer period T _A, by a reset control signal phi _R goes low, the reset switch 21 is turned off. At this time, an output signal V _SIG that can be used as a reference corresponding to the potential (reset potential V _RD ) before the electrons are transferred to the readout region 15 is output.

And before the start of the output period _{T S,} in the first transfer period _{T A} and the reset period _{T R,} the first control signal phi _TX1 low level (first transistor 31 is off), the second control signal phi _TX2 low level The third control signal _φTX3 is at a high level (the second transistor 33 is on), and the fourth control signal _φTX4 is at a low level (the third transistor 341 is off). Thus, in these periods, the potential of the output node N _TX (level transfer control signal phi _TX) is to become the V _{OFF (ground} potential), the electrons in the read area 15 from the storage area 13 is not transferred.

Next, when the transfer period T _TX is started, the first control signal φ _TX1 is at a high level (the first transistor 31 is on), and the third control signal φ _TX3 is at a low level (the second transistor 33 is off). become. Therefore, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) becomes the first potential V _MID , and an inversion layer is formed in a region (channel region 161) in the substrate 11 immediately below the transfer gate 16. As a result, electrons are transferred from the accumulation region 13 to the read region 15 through the inversion layer, and the potential V _{FD of the} read region 15 is lowered according to the transferred electrons. At this time, the first capacitor 32 is charged by applying the first potential V _MID to the other end 322.

After the start of the transfer period _TTX , at the timing P1, the first control signal _φTX1 becomes low level (the first transistor 31 is off). Thereafter, at timing P2, the second control signal _φTX2 becomes high level. At this time, since the potential of the other end 322 is pushed up through the first capacitor 32, the potential of the output node _{N TX} (level transfer control signal phi _TX) is larger _{V ON} than the first potential _{V MID.}

Thereafter, at timing P3, the fourth control signal _φTX4 becomes high level (the third transistor 341 is turned on). Then, since the first electric potential _{V MID} is applied to the output node _{N TX} via the third transistor 341, the potential of the output node _{N TX} (level transfer control signal phi _TX) is the first potential _{V MID.}

Finally, the second transfer period _{T B} Oite, the second control signal phi _TX2 goes low, the third control signal phi _TX3 goes high (second transistor 33 is turned on), the fourth control signal phi _TX4 becomes a low level (the third transistor 341 is turned on). Thus, the potential of the output node _{N TX} (level transfer control signal phi _TX) becomes _{V OFF,} the inversion layer in the channel region 161 disappears. Then, an output signal V _SIG corresponding to the potential V _FD of the reading region 15 to which electrons are transferred is output.

In addition, a potential and a potential state when the solid-state imaging device according to the third embodiment of the present invention performs the operation of FIG. 9 will be described with reference to the drawings. FIG. 10 is a graph showing potential and potential states when the solid-state imaging device according to the third embodiment of the present invention performs the operation shown in FIG. Incidentally, FIG. 10 (a) is a graph showing the state of electric potential and the potential during the reset period T _R. FIG. 10B is a graph showing the potential and potential state during the transfer period _TTX and after the timing P2. FIG. 10C is a graph showing the potential and the potential state during the transfer period T _TX and after the timing P3. Further, FIG. 10 (d) is a graph showing the state of the potential and the potential in the second transfer period T in _B.

As shown in FIG. 10 (a), the reset period _{T R,} since the shallow bottom [psi _OFF of the potential in the channel region 161, electrons Q1 remains stored in the storage area 13. At this time, the potential V _FD1 of the reading region 15 becomes the reset potential V _RD as described above.

Next, as illustrated in FIG. 10B, when the timing P _< b _{> 2} of the transfer period T _TX is reached, the potential of the output node N _TX (the level of the transfer control signal φ _TX ) becomes V _ON , so that the channel region 161 The bottom Ψ _{ON1 of the} potential is deepened. At this time, the bottom Ψ _ON1 of the potential of the channel region 161 is set deeper than the bottom Ψ _PD of the potential of the accumulation region 13 and further deeper than the reset potential V _RD (first state). In this state, as in the solid-state imaging device according to the first embodiment of the present invention, the electrons Q2 in the storage region 13 can be transferred to the channel region 161 and the readout region 15 at high speed without remaining. become.

Furthermore, the solid-state imaging device according to a third embodiment of the present invention, as described above, the potential of the output node N _TX (level transfer control signal phi _TX) becomes the first potential V _MID. At this time, as shown in FIG. 10C, the first potential is set such that the potential bottom ψ _ON2 of the channel region 161 is deeper than the potential bottom ψ _PD of the accumulation region 13 and shallower than the reset potential V _RD. by selecting the V _MID, it is possible to transfer the electrons Q31 of the channel region 161 to the storage area 13, rather than the read area 15 (second state). Therefore, channel charge injection can be prevented.

In the solid-state imaging device according to the third embodiment of the present invention, although it is necessary to select an appropriate first potential V _MID as compared with the solid-state imaging device according to the second embodiment of the present invention, the first load 35 is required. (Refer to FIG. 5) is unnecessary, and the circuit configuration can be simplified. Furthermore, in the solid-state imaging device according to the third embodiment of the present invention, the time for continuing the state (second state) shown in FIG. 10C is set to the high-level continuation time (third timing P3) of the fourth control signal. To the end of the transfer period _TTX ). Therefore, transfer of electrons Q31 in channel region 161 to readout region 15 can be realized with high accuracy.

Since the solid-state imaging device according to the third embodiment of the present invention passes through the state (second state) shown in FIG. 10C, the transfer period T _TX ends as shown in FIG. Later, it is possible to transfer all the electrons Q4 to the reading area 15.

<Deformation, etc.>
In each of the above-described embodiments, the reset transistor 21, the output transistor 22, the first transistor 31, the second transistor 33, and the third transistors 34 and 341 are illustrated as being n-channel transistors. A part or all of them may be p-channel transistors or elements having a switching function other than transistors. In addition, as long as the potential and the potential state shown in FIG. 4, FIG. 7, or FIG. 10 can be realized, the structures and operations of the solid-state imaging device and the transfer control signal generation unit described above can be changed as appropriate.

  Further, as each embodiment of the present invention, the solid-state imaging device 1 (see FIG. 1) in which the n-type accumulation region 13 and the n-type readout region 15 are respectively formed in the p-type substrate 11 is illustrated. Even if these p-type and n-type are reversed, the same effects as those of the solid-state imaging device 1 can be obtained. In this case, a p-type accumulation region and a p-type readout region are formed in the n-type substrate, respectively, and holes are accumulated in the accumulation region and the readout region. The relationship between the depth of the bottom of the potential of the storage region, the channel region, and the readout region and the level of the potential in the graphs shown in FIGS. 4, 7, and 10 are opposite to those of the solid-state imaging device 1 described above. Be controlled.

  In any of the above cases, when transferring charge from the accumulation region to the channel region and the readout region, the bottom of the potential of the channel region exceeds the bottom of the potential of the accumulation region, and the reset potential is further increased. Exceeded (first state). In any of the above cases, the potential bottom of the channel region is between the potential bottom of the accumulation region and the reset potential (second state) before shifting to a state where no charge is transferred. .

  Moreover, although the case where the solid-state imaging device 1 according to each embodiment of the present invention is a CMOS image sensor has been illustrated, the present invention is not limited to a CMOS image sensor, and other solid-state imaging devices such as a CCD image sensor. However, it is applicable.

  The solid-state imaging device and the driving method of the solid-state imaging device according to the present invention can be suitably used for, for example, a CMOS image sensor or a CCD image sensor mounted on various electronic devices having an imaging function.

1: Solid-state image pickup devices 3a, 3b, 3c: Transfer control signal generation unit 11: Substrate 12: Gate insulating film 13: Storage region 14: Surface region 15: Read region 16: Transfer gate 161: Channel region 17: Device isolation unit 21 : Reset transistor 22: Output transistor 23: Amplifying section 31: First transistor 32: First capacitor 321: One end 322: Other end 33: Second transistors 34 and 341: Third transistor 35: First load (delay element)
351: one end 352: the other end N _TX: output node phi _R: reset control signal phi _S: output control signal phi _TX: transfer control signal phi _TX1: first control signal phi _TX2: second control signal phi _TX3: third control Signal φ _TX4 : Fourth control signal V _MID : First potential V _SIG : Output signal V _RD : Reset potential V _{FD1 to} V _FD4 : Reading region potentials ψ _OFF , ψ _ON1 , ψ _ON1 : Bottom of channel region potential ψ _PD : Bottom of accumulation region potential

Claims (9)

A substrate made of a first conductivity type semiconductor;
A gate insulating film made of an insulator formed on the upper surface of the substrate;
A region in the substrate made of a semiconductor of a second conductivity type different from the first conductivity type, and an accumulation region for accumulating charges generated by photoelectric conversion in the substrate;
A region in the substrate made of the semiconductor of the second conductivity type, a readout region to which the charge accumulated in the accumulation region is transferred;
A transfer gate formed on the upper surface of the gate insulating film and between the accumulation region and the read region;
During the transfer period, the charge accumulated in the accumulation region is transferred to the readout region via a channel region which is a region in the substrate that is directly below the transfer gate,
During at least part of the transfer period,
Solid-state imaging characterized in that the bottom of the potential of the channel region exceeds the bottom of the potential of the storage region, and further enters a first state that also exceeds a reset potential that is the potential of the readout region immediately before the transfer period. element. During the transfer period and at least part of the period after entering the first state,
2. The solid-state imaging device according to claim 1, wherein the bottom of the potential of the channel region is in a second state between the bottom of the potential of the accumulation region and the reset potential. A transfer control signal generator for generating a transfer control signal to be given to the transfer gate;
The transfer control signal generation unit includes a delay element that delays fluctuations in the level of the transfer control signal,
The transfer control signal generation unit realizes the second state by changing the level of the transfer control signal while delaying it using the delay element after entering the first state. The solid-state imaging device according to claim 2. The transfer control signal generator is
A first transistor having a first control signal applied to the control electrode, a first potential supplied to the first electrode, and a second electrode connected to the output node;
A first capacitor having one end provided with a second control signal and the other end connected to the output node;
A second transistor in which a third control signal is applied to the control electrode, a second potential is supplied to the first electrode, and the second electrode is connected to the output node;
A third transistor in which a fourth control signal is supplied to the control electrode and the second potential is supplied to the first electrode;
A first load having one end connected to the second electrode of the third transistor and the other end connected to the output node;
The solid-state imaging device according to claim 3, wherein the transfer control signal is output from the output node. A transfer control signal generator for generating a transfer control signal to be given to the transfer gate;
The transfer control signal generated by the transfer control signal generation unit has at least a period in which the first level for realizing the first state continues and a period in which the second level for realizing the second state continues. The solid-state imaging device according to claim 2. The transfer control signal generator is
A first transistor having a first control signal applied to the control electrode, a first potential supplied to the first electrode, and a second electrode connected to the output node;
A first capacitor having one end provided with a second control signal and the other end connected to the output node;
A second transistor in which a third control signal is applied to the control electrode, a second potential is supplied to the first electrode, and the second electrode is connected to the output node;
A third transistor in which a fourth control signal is supplied to the control electrode, the first potential is supplied to the first electrode, and a second electrode is connected to the output node;
The solid-state imaging device according to claim 5, wherein the transfer control signal is output from the output node. When the first conductivity type is p-type, the second conductivity type is n-type, and the charge is an electron,
7. The first state according to claim 1, wherein the bottom of the potential of the channel region is deeper than the bottom of the potential of the accumulation region and the reset potential. Solid-state image sensor. A region in the substrate made of the semiconductor of the first conductivity type, and a surface region formed between the upper surface of the substrate and the accumulation region;
The solid-state imaging device according to claim 1, further comprising: A substrate made of a first conductivity type semiconductor;
A gate insulating film made of an insulator formed on the upper surface of the substrate;
A region in the substrate made of a semiconductor of a second conductivity type different from the first conductivity type, and an accumulation region for accumulating charges generated by photoelectric conversion in the substrate;
A region in the substrate made of the semiconductor of the second conductivity type, a readout region to which the charge accumulated in the accumulation region is transferred;
A method for driving a solid-state imaging device, comprising a transfer gate formed on the upper surface of the gate insulating film and between the accumulation region and the readout region,
During the transfer period, the charge accumulated in the accumulation region is transferred to the readout region via a channel region that is a region in the substrate that is directly below the transfer gate,
During at least part of the transfer period,
Solid-state imaging characterized in that the bottom of the potential of the channel region exceeds the bottom of the potential of the accumulation region, and further enters a first state that exceeds the reset potential that is the potential of the readout region immediately before the transfer period. Device driving method.

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