JP2013258179A - Silicon carbide substrate, silicon carbide substrate manufacturing method, semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide substrate which can effectively inhibit detachment of a silicon carbide single crystal substrate from a support substrate, and provide a manufacturing method of the silicon carbide substrate and a manufacturing method of a semiconductor device using the silicon carbide substrate.SOLUTION: A silicon carbide substrate 100 comprises a plurality of silicon crystal substrates 1-3, a support substrate 10 and a connection layer 11. The plurality of single crystal substrates 1-3 are composed of silicon carbide and include first surfaces 1a-3a and first rear faces 1b-3b which are opposite to each other, respectively. The support substrate 10 is composed of silicon carbide and includes a second surface 10a and a second rear face 10b which are opposite to each other. The connection layer 11 is sandwiched between the plurality of single crystal substrates 1-3 and the support substrate 10 and connects each of the first rear faces 1b-3b and the second surface 10a such that the first rear faces 1b-3b and the second surface 10a are opposite to each other. A tension strength of each of the single crystal substrates 1-3 and the support substrate 10 is 0.6 Mpa and over.

Description

  The present invention relates to a silicon carbide substrate, a method for manufacturing a silicon carbide crystal, a semiconductor device, and a method for manufacturing a semiconductor device.

  In recent years, silicon carbide substrates have begun to be used for manufacturing semiconductor devices. Silicon carbide has a larger band gap than silicon. Therefore, a semiconductor device using a silicon carbide substrate has advantages such as high breakdown voltage, low on-resistance, and small deterioration in characteristics under a high temperature environment.

  Japanese Patent Application Laid-Open No. 2011-071196 (Patent Document 1) describes a method of obtaining a large-diameter semiconductor substrate by connecting a plurality of silicon carbide single crystal substrates to a support substrate by a connection layer made of silicon. Has been.

JP 2011-071196 A

  However, when a silicon carbide single crystal substrate manufactured by the method described in JP2011-071196 A is polished, the silicon carbide single crystal sometimes peels from the support substrate.

  This invention is made | formed in view of the said situation, The objective is the silicon carbide substrate which can suppress effectively that a silicon carbide single crystal substrate peels from a support substrate, its manufacturing method, and And providing a semiconductor device using the same and a method of manufacturing the semiconductor device.

  The silicon carbide substrate according to the present invention includes a plurality of single crystal substrates, a support substrate, and a connection layer. The plurality of single crystal substrates are made of silicon carbide, and each have a first front surface and a first back surface facing each other. The support substrate is made of silicon carbide and has a second surface and a second back surface that face each other. The connection layer is interposed between the plurality of single crystal substrates and the support substrate, and connects each of the first back surface and the second surface so that each of the first back surface and the second surface face each other. Connecting. The tensile strength between the single crystal substrate and the support substrate is 0.6 MPa or more.

  According to the silicon carbide substrate according to the present invention, the tensile strength between the single crystal substrate and the support substrate is 0.6 MPa or more. Therefore, the single crystal substrate can be effectively prevented from peeling from the support substrate.

  In the above silicon carbide substrate, the tensile strength is preferably 2 MPa or more and 20 MPa or less. Therefore, the single crystal substrate can be further suppressed from peeling from the support substrate.

  In the above silicon carbide substrate, the main component of the material constituting the connection layer is preferably silicon carbide. When the connection layer is made of a material different from silicon carbide, the support substrate and the single crystal substrate may be separated from the connection layer due to a difference in thermal expansion coefficient. In the silicon carbide substrate, since the connection layer, the support substrate, and the single crystal substrate have the same material, it is possible to effectively suppress the support substrate and the single crystal substrate from being separated from the connection layer.

  In the silicon carbide substrate, preferably, the ten-point average roughness of each of the first back surface and at least one of the second surface is 2 μm or more and 20 μm or less.

  If the ten-point average roughness is 2 μm or more, the bonding area between the single crystal substrate and the supporting substrate and the connection layer can be secured, so that the bonding strength is increased. Further, if the ten-point average roughness is 20 μm or less, the distance between the single crystal substrate and the support substrate is short, so that the bonding strength is increased.

  In the silicon carbide substrate described above, the arithmetic average roughness of each of the first back surface and the second surface is preferably 0.16 μm or more and 0.95 μm or less.

  If the arithmetic average roughness is 0.16 μm or more, the bonding area between the single crystal substrate and the supporting substrate and the connection layer can be secured, so that the bonding strength is increased. In addition, when the arithmetic average roughness is 0.95 μm or less, since the distance between the single crystal substrate and the support substrate is short, the bonding strength is increased.

  The silicon carbide substrate preferably has a diameter of 110 mm or more. Thereby, a silicon carbide substrate having a large diameter can be provided.

  In the silicon carbide substrate, preferably, each of the plurality of single crystal substrates has a hexagonal crystal structure and a polytype of 4H. The first surface is a plane whose plane orientation is turned off by 5 ° or less from the {0-11-2} plane. Thereby, when manufacturing a device using the single crystal substrate, the surface of the epitaxial layer formed on the first main surface can be brought close to the {0-11-2} plane. Therefore, it becomes easy to make the surface of the epitaxial layer a special surface described later.

  The method for manufacturing a silicon carbide substrate according to the present invention includes the following steps. A plurality of single crystal substrates each made of silicon carbide and having a first surface and a first back surface facing each other, and a support substrate made of silicon carbide and having a second surface and a second back surface facing each other And are prepared. Surface treatment is performed so that the ten-point average roughness of each of the first back surface and at least one of the second surface is 2 μm or more and 20 μm or less. The support substrate and each of the plurality of single crystal substrates are arranged via the fluid layer such that each of the first back surfaces of the plurality of single crystal substrates faces the second surface of the support substrate. By converting the fluid layer, a connection layer connecting each of the first back surface and the second surface is formed. According to the method for manufacturing a silicon carbide substrate according to the present invention, the surface treatment is performed so that the ten-point average roughness of each of the first back surface and the second surface is 2 μm or more and 20 μm or less. Thereby, the silicon carbide substrate which can suppress effectively that a single crystal substrate peels from a support substrate can be manufactured.

  The method for manufacturing a silicon carbide substrate according to the present invention includes the following steps. A plurality of single crystal substrates each made of silicon carbide and having a first surface and a first back surface facing each other, and a support substrate made of silicon carbide and having a second surface and a second back surface facing each other And are prepared. Surface treatment is performed so that the arithmetic average roughness of each of the first back surface and at least one of the second surface is 0.16 μm or more and 0.95 μm or less. The support substrate and each of the plurality of single crystal substrates are arranged via the fluid layer such that each of the first back surfaces of the plurality of single crystal substrates faces the second surface of the support substrate. By converting the fluid layer, a connection layer connecting each of the first back surface and the second surface is formed. Thereby, the silicon carbide substrate which can suppress effectively that a single crystal substrate peels from a support substrate can be manufactured.

  Preferably, in the above method for manufacturing a silicon carbide substrate, the fluid layer is made of a polymer whose main component is a substance that becomes silicon carbide when heated. In the step of forming the connection layer, polycrystalline silicon carbide, amorphous silicon carbide, and single crystal silicon carbide having voids are formed by thermally decomposing the fluid layer.

  According to the above method for manufacturing a silicon carbide substrate, the fluid layer is made of a polymer whose main component is a substance that becomes silicon carbide by heating, and the single crystal substrate and the support substrate are also made of silicon carbide. Therefore, the thermal expansion coefficient of the fluid layer is close to the thermal expansion coefficients of the single crystal substrate and the support substrate. This maintains the connection strength between the connection layer, the single crystal substrate, and the support substrate even in an environment having a temperature change, so that the single crystal substrate can be effectively prevented from peeling from the support substrate. .

  Preferably, in the above method for manufacturing a silicon carbide substrate, the fluid layer is heated at 1000 ° C. or higher and 2100 ° C. or lower. At temperatures lower than 1000 ° C., the fluidized layer, which is a polymer, is insufficiently siliconized, resulting in a decrease in bonding strength. On the other hand, at a temperature higher than 2100 ° C., the single crystal substrate and the support substrate are sublimated. Therefore, it is preferable to heat the fluid layer at 1000 ° C. or higher and 2100 ° C. or lower.

  Preferably, in the above method for manufacturing a silicon carbide substrate, the fluid layer includes a filler made of silicon carbide. Thereby, when heat-decomposing a fluid layer, it can suppress that a fluid layer shrink | contracts excessively.

  In the above method for manufacturing a silicon carbide substrate, preferably, the fluid layer includes a silicon compound. When the fluid layer contains more carbon than silicon, silicon carbide approaches stoichiometry by adding silicon. Thereby, the connection strength between the connection layer, the single crystal substrate and the support substrate can be increased.

  Preferably, in the method for manufacturing the silicon carbide substrate, the surface treatment includes a step of polishing each of the first back surface and at least one of the second surface. Thereby, the surface roughness of each of the first back surface and the second surface can be adjusted to a desired range.

  Preferably, in the above method for manufacturing a silicon carbide substrate, the surface treatment step includes a step of etching each of the first back surface and at least one of the second surface after the polishing step. Thereby, the surface roughness of at least one of each of the first back surface and the second surface can be effectively adjusted to a desired range.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention includes the following steps. A single crystal substrate made of silicon carbide and having a first surface and a first back surface facing each other, and a support substrate made of silicon carbide and having a second surface and a second back surface facing each other are prepared Is done. Surface treatment is performed so that the ten-point average roughness of each of the first back surface and at least one of the second surface is 2 μm or more and 20 μm or less. A silicon carbide substrate having a connection layer that joins the first back surface and the second surface so that the first back surface and the second surface face each other, interposed between the single crystal substrate and the support substrate Is prepared. An epitaxial growth layer is formed on the single crystal substrate. An electrode is formed on the epitaxial growth layer.

  According to the semiconductor device manufacturing method of the present invention, the surface treatment is performed so that the ten-point average roughness of each of the first back surface and the second surface is 2 μm or more and 20 μm or less. Thereby, the single crystal substrate and the support substrate are firmly connected via the connection layer. Therefore, the single crystal substrate can be effectively prevented from peeling from the support substrate.

  The semiconductor device according to the present invention includes a plurality of single crystal substrates, a support substrate, a connection layer, an epitaxial growth layer, and an electrode. The plurality of single crystal substrates are made of silicon carbide, and each have a first front surface and a first back surface facing each other. The support substrate is made of silicon carbide and has a second surface and a second back surface that face each other. The connection layer is interposed between the plurality of single crystal substrates and the support substrate, and connects each of the first back surface and the second surface so that each of the first back surface and the second surface face each other. Connecting. The epitaxial layer is provided on the single crystal substrate. The electrode is provided on the epitaxial growth layer. The tensile strength between the single crystal substrate and the support substrate is 0.6 MPa or more.

  According to the semiconductor device of the present invention, the tensile strength between the single crystal substrate and the support substrate is 0.6 MPa or more. Thereby, the single crystal substrate and the support substrate are firmly connected via the connection layer. Therefore, the single crystal substrate can be effectively prevented from peeling from the support substrate.

  In the above semiconductor device, preferably, the crystal structure of silicon carbide forming the epitaxial layer is hexagonal, the polytype is 4H, and the surface of the epitaxial layer has a plane orientation of {0-33-8}. Including the first surface. Thereby, the channel resistance on the surface of the epitaxial layer can be reduced. Therefore, the on-resistance can be reduced.

  In the semiconductor device described above, the surface of the epitaxial layer preferably includes the first surface microscopically, and the first surface further microscopically displays the second surface having the plane orientation {0-11-1}. Including. Thereby, the channel resistance on the surface of the epitaxial layer can be further reduced. Therefore, the on-resistance can be further reduced.

  In the semiconductor device described above, the first surface and the second surface of the surface of the epitaxial layer preferably include a composite surface having a plane orientation {0-11-2}. Thereby, the channel resistance on the surface of the epitaxial layer can be further reduced. Therefore, the on-resistance can be further reduced.

  In the above semiconductor device, the surface of the epitaxial layer preferably has an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} plane. Thereby, the channel resistance on the surface of the epitaxial layer can be further reduced. Therefore, the on-resistance can be further reduced.

  According to the present invention, a silicon carbide substrate, a manufacturing method thereof, a semiconductor device using the silicon carbide substrate, and a manufacturing method of the semiconductor device, which can effectively prevent the silicon carbide single crystal substrate from being separated from the support substrate. And can be provided.

1 is a plan view schematically showing a structure of a silicon carbide substrate in a first embodiment of the present invention. It is a schematic sectional drawing in alignment with line II-II of FIG. FIG. 3 is a schematic flow diagram of a method for manufacturing a silicon carbide substrate in the first embodiment. FIG. 3 is a cross sectional view schematically showing one step of a method for manufacturing a silicon carbide substrate in the first embodiment. FIG. 6 is a cross sectional view schematically showing another step of the method for manufacturing the silicon carbide substrate in the first embodiment. It is sectional drawing which shows roughly the structure of the silicon carbide substrate in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 3 of this invention. FIG. 10 is a schematic flow diagram of a method for manufacturing a semiconductor device in a third embodiment. FIG. 10 is a cross sectional view schematically showing a first step of the method for manufacturing the semiconductor device in the third embodiment. FIG. 10 is a cross sectional view schematically showing a second step of the method for manufacturing the semiconductor device in the third embodiment. FIG. 11 is a cross sectional view schematically showing a third step of the method for manufacturing the semiconductor device in the third embodiment. FIG. 10 is a cross sectional view schematically showing a fourth step of the method for manufacturing the semiconductor device in the third embodiment. FIG. 3 is a cross sectional view schematically showing a lapping device used in a surface treatment process for a silicon carbide substrate in the first embodiment. FIG. 3 is a cross sectional view schematically showing a reactive ion etching apparatus used for a surface treatment process for a silicon carbide substrate in the first embodiment. 1 is a cross sectional view schematically showing a CMP apparatus used for a surface treatment process for a silicon carbide substrate in a first embodiment. FIG. 10 is a partial cross sectional view schematically showing a fine structure of a surface of an epitaxial layer in a third embodiment. It is a figure which shows the crystal structure of the (000-1) plane in the hexagonal crystal of polytype 4H. It is a figure which shows the crystal structure of the (11-20) plane which follows the line XVIII-XVIII of FIG. It is a figure which shows the crystal structure in the surface vicinity of the composite surface of FIG. 16 in (11-20) plane. It is the figure which looked at the compound surface of Drawing 16 from the (01-10) plane. FIG. 5 is a graph showing an example of the relationship between the angle between the channel plane and the (000-1) plane viewed macroscopically and the channel mobility when thermal etching is performed and when it is not performed. It is. It is a graph which shows an example of the relationship between the angle between a channel direction and the <0-11-2> direction, and channel mobility. It is a figure which shows the modification of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the present specification, individual planes are indicated by (), aggregate planes are indicated by {}, and aggregate orientations are indicated by <>. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number.

(Embodiment 1)
Referring to FIGS. 1 and 2, silicon carbide substrate 100 of the present embodiment has single crystal substrates 1 to 9, support substrate 10, and connection layer 11.

  Each of single crystal substrates 1 to 9 has a first surface (a surface exposed in FIGS. 1 and 2) and a first back surface (a surface in contact with connection layer 11 in FIG. 2) facing each other. For example, referring to FIG. 2, single crystal substrate 1 has a first surface 1a and a first back surface 1b facing each other, and single crystal substrate 2 has a first surface 2a and a first surface facing each other. The single crystal substrate 3 has a first surface 3a and a first back surface 3b facing each other. Single crystal substrates 1 to 9 are each made of a single crystal of silicon carbide. In order to simplify the description below, among the single crystal substrates 1 to 9 (FIG. 1), at least one of the single crystal substrates 1 to 9 may be referred to. Each of is treated similarly.

  Single crystal substrates 1 to 9 are made of silicon carbide having a hexagonal single crystal structure of polytype 4H. The plane orientation of the first surface 1a of the single crystal substrates 1 to 9 is preferably a {0-11-2} plane or a plane whose inclination from this plane is within 5 °. The first surface 1a can be formed by mechanical polishing or slicing. Thereby, when manufacturing a device using the single crystal substrate, the surface of the epitaxial layer formed on the first main surface can be brought close to the {0-11-2} plane. Therefore, it becomes easy to make the surface of the epitaxial layer a special surface described later.

  The support substrate 10 has a second front surface 10a (a surface in contact with the connection layer 11 in FIG. 2) and a second rear surface 10b (a surface exposed in FIG. 2) facing each other. Support substrate 10 is larger than each of single crystal substrates 1-9. In FIG. 2, the area of the second surface 10 a of the support substrate 10 is substantially equal to the area of the surface 100 a configured by the first surfaces of the single crystal substrates 1 to 9.

  In the present embodiment, the 10-point average roughness of each of the first back surfaces of single crystal substrates 1 to 9 and the second surface of support substrate 10 is not less than 2 μm and not more than 20 μm. The arithmetic average roughness of each of the first back surfaces of single crystal substrates 1 to 9 and the second surface of support substrate 10 is not less than 0.16 μm and not more than 0.95 μm. When the surface roughness is too small, the bonding area between the single crystal substrates 1 to 9 and the support substrate 10 and the connection layer 11 cannot be sufficiently secured, and the bonding strength between the single crystal substrates 1 to 9 and the support substrate 10 is lowered. On the other hand, when the surface roughness is too large, the distance between the single crystal substrates 1 to 9 and the support substrate 10 is increased, so that the bonding strength decreases. Therefore, the bonding strength between the single crystal substrates 1 to 9 and the support substrate 10 can be improved by adjusting the ten-point average roughness and the arithmetic average roughness to the above ranges.

  Support substrate 10 is made of silicon carbide. Support substrate 10 is, for example, a silicon carbide single crystal. Connection layer 11 is interposed between each of single crystal substrates 1 to 9 and support substrate 10. More specifically, referring to FIG. 2, the first back surface 1 b so that each of the first back surfaces 1 b to 3 b of the single crystal substrates 1 to 3 faces the second surface 10 a of the support substrate 10. To 3b and the second surface 10a are connected to each other through the connection layer 11.

  The thickness of the connection layer 11 is preferably 2 μm or more and 15 μm or less, and more preferably 4 μm or more and 12 μm or less. When the average thickness of the connection layer 11 is thin, the connection strength is lowered because a portion where the connection layer 11 does not exist is generated. On the other hand, when the average thickness of connection layer 11 is large, since the inclination of single crystal substrates 1 to 9 with respect to support substrate 10 increases, the plane orientation distribution of single crystal substrates 1 to 9 increases. Therefore, the thickness of the connection layer 11 is preferably in the above range.

  In the present embodiment, connection layer 11 is mainly composed of silicon carbide. More specifically, the connection layer 11 is formed by converting polycarbosilane which is a polymer having a bond of carbon and silicon (hereinafter also referred to as “Si—C bond”) in the main chain. And a compound mainly composed of silicon carbide. Here, the main component refers to a component that occupies 50% or more of the atoms constituting the compound. That is, in the connection layer 11, 50% or more of the atoms are made of silicon carbide constituting the Si—C bond.

  Therefore, in silicon carbide substrate 100, single crystal substrates 1-9 are made of silicon carbide, and connection layer 11 is mainly composed of silicon carbide. Therefore, the thermal expansion coefficient of single crystal substrates 1-9 and the heat of connection layer 11 are reduced. The expansion coefficient approximates. Thereby, since the adhesive strength between the single crystal substrates 1 to 9 and the connection layer 11 is increased, peeling between the single crystal substrates 1 to 9 and the connection layer 11 is suppressed.

  In addition, since the connection layer 11 is formed by converting polycarbosilane as described above, the connection layer can be adjusted by appropriately adjusting the heating temperature when converting polycarbosilane and the structure of polycarbosilane used. 11 can easily be a compound composed of at least one of polycrystalline silicon carbide, amorphous, and single crystal having voids. Preferably, connection layer 11 includes polycrystalline silicon carbide, amorphous silicon carbide, and single crystal silicon carbide having voids.

  In silicon carbide substrate 100 of the present embodiment, tensile strength between single crystal substrates 1 to 9 and support substrate 10 is 0.6 MPa or more. Preferably, the tensile strength between the single crystal substrates 1 to 9 and the support substrate 10 is 2 MPa or more and 20 MPa or less. Thereby, it can suppress that the single crystal substrates 1-9 peel from the support substrate 10. FIG. Note that the tensile strength between the single crystal substrate and the support substrate means that when the single crystal substrate and the support substrate are connected via the connection layer, one of the single crystal substrate and the support substrate is fixed and the other is the support substrate. It is the strength when the single crystal substrate peels from the support substrate when pulled in a direction perpendicular to the surface of the substrate.

  In the present embodiment, silicon carbide substrate 100 preferably has a diameter of 110 mm or more. That is, it is preferable that the diameter in the surface 100a comprised by each 1st surface of the single crystal substrates 1-9 is 110 mm or more. As described above, the size of the single crystal substrate is industrially limited to about 100 mm (4 inches). However, according to the present embodiment, the diameter of 110 mm or more, which has been difficult to manufacture industrially in the past, is used. Silicon carbide substrate 100 having the surface of the single crystal substrate can be obtained. For example, by manufacturing a semiconductor device using such a large-diameter silicon carbide substrate, the semiconductor device can be manufactured more efficiently, and the manufacturing cost can be reduced.

  Next, a method for manufacturing silicon carbide substrate 100 of the present embodiment will be described using FIGS. 1 to 5 and FIGS. 13 to 15. 3 is a schematic flow diagram of the method for manufacturing the silicon carbide substrate in the first embodiment, and FIGS. 4 and 5 schematically show the respective steps of the method for manufacturing the silicon carbide substrate in the first embodiment. It is sectional drawing.

  First, as shown in FIG. 4, a substrate preparation process is performed (FIG. 3: step S10). Specifically, a plurality of single crystal substrates 1 to 9 and a support substrate 10 having the following characteristics are prepared.

  As described above, the plane orientation of the first surface 1a of the single crystal substrates 1 to 9 is preferably the {0-11-2} plane or a plane whose inclination from this plane is within 5 °. The first surface 1a can be formed by mechanical polishing or slicing.

  Support substrate 10 is made of silicon carbide. Specifically, a substrate made of polycrystalline silicon carbide, amorphous, or a mixture of polycrystalline and amorphous can be preferably used. Moreover, low quality single crystal silicon carbide having many dislocations and stacking faults can also be used.

  From the viewpoint of manufacturing a silicon carbide substrate having a diameter of 110 mm or more, when the first surfaces of the plurality of single crystal substrates 1 to 9 are arranged as shown in FIG. It is preferable to select the sizes of the single crystal substrates 1 to 9 and the support substrate 10 so that the diameter of the surface 100a (see FIG. 2) formed by the above becomes 110 mm or more.

  Next, referring to FIG. 13 to FIG. 15, a step of surface-treating the second surface of support substrate 10 and the first back surface of each of the plurality of single crystal substrates 1 to 9 (FIG. 3: step S20). ) Is implemented.

  Specifically, first, grinding and polishing are performed on the second surface of the support substrate 10. In the grinding process, for example, a vitrified grindstone is used, the second surface of the support substrate 10 is rotated opposite to the grindstone, and the substrate surface is removed by cutting at a constant speed. Thereby, the thickness of the support substrate 10 can be adjusted.

  Polishing of the support substrate 10 can be performed by a lapping apparatus 170 shown in FIG. The lapping device 170 has a base surface plate 172, a surface plate 174, a crystal holder 176, a weight 178, and a slurry liquid supply port 180.

  The surface plate 174 is placed on the base surface plate 172. The base surface plate 172 and the surface plate 174 are rotatable about the central axis X1 of the base surface plate 172. The crystal holder 176 is a component for supporting the support substrate 10 on its lower surface. The support substrate 10 is held by the crystal holder 176 so that the second surface 10a of the support substrate 10 and the surface plate 174 face each other. A load is applied to the support substrate 10 by a weight 178 placed on the upper surface of the crystal holder 176. The crystal holder 176 is substantially parallel to the axis X1 and has a center axis X2 at a position displaced from the axis X1, and is rotatable about the center axis X2. The slurry liquid supply port 180 supplies the slurry S onto the surface plate 174.

  According to the lapping apparatus 170, the base surface plate 172, the surface plate 174, and the crystal holder 176 are rotated to supply the slurry S onto the surface plate 174, and the second surface 10a of the support substrate is applied to the surface plate 174. By contacting, the second surface 10a can be polished.

  The slurry S contains diamond abrasive grains. A desired surface roughness can be obtained by adjusting the particle diameter of abrasive grains such as diamond. As the surface plate, a metal surface plate such as iron, copper, tin, or a tin alloy, a composite surface plate of metal and resin, or an abrasive cloth can be used. By using a hard metal surface plate, the rate can be improved.

  In addition, the first back surface of each of the plurality of single crystal substrates 1 to 9 is also ground and polished in the same manner as the support substrate 10. In the present embodiment, each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of support substrate 10 are polished and ground. Only one of the first back surface of each of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 may be ground and polished.

  Next, the surface finishing process of the 2nd surface of the support substrate 10 is implemented. Specifically, dry etching, CMP (Chemical Mechanical Polishing), or the like is performed on the second surface of the support substrate 10.

  The surface finishing process of the 2nd surface of the support substrate 10 is performed by the reactive ion etching apparatus shown, for example in FIG. The reactive ion etching apparatus 50 has a chamber 52. In the chamber 52, parallel plate type upper electrode 54 and lower electrode 56, and a substrate support 58 disposed on the lower electrode 56 so as to face the upper electrode 54 are provided. A gas supply port 60 connected to a gas source and a gas exhaust port 62 connected to a vacuum pump are provided in the chamber 52. A high frequency power source 64 connected to the lower electrode 56 is disposed outside the chamber 52.

  In the dry etching apparatus 16, plasma can be generated in the chamber 52 by supplying gas from the gas supply port 60 into the chamber 52 and supplying high frequency power from the high frequency power supply 64 to the lower electrode 56. By disposing the support substrate 10 on the substrate support table 58, the second surface of the support substrate 10 can be dry-etched.

  Further, the surface finishing process of the second surface of the support substrate 10 may be performed by, for example, a CMP apparatus shown in FIG. The CMP apparatus 270 includes a surface plate 272, a polishing pad 274, a crystal holder 276, a weight 278, and a slurry liquid supply port 280.

  The polishing pad 274 is placed on the surface plate 272. The surface plate 272 and the polishing pad 274 are rotatable about the central axis X1 of the surface plate 272. The crystal holder 276 is a component for supporting the support substrate 10 on its lower surface. The support substrate 10 is held by the crystal holder 276 so that the second surface 10 a of the support substrate 10 and the polishing pad 274 face each other. A load is applied to the support substrate 10 by a weight 278 placed on the upper surface of the crystal holder 276. The crystal holder 276 is substantially parallel to the axis line X1 and has a center axis line X2 at a position displaced from the axis line X1, and is rotatable around the center axis line X2. The slurry liquid supply port 280 supplies the slurry S onto the polishing pad 274.

  According to the CMP apparatus 270, the surface plate 272, the polishing pad 274, and the crystal holder 276 are rotated, the slurry S is supplied onto the polishing pad 274, and the second surface 10a of the support substrate is brought into contact with the polishing pad 274. By doing so, the second surface 10a can be polished.

  The CMP abrasive grains need to be softer than silicon carbide in order to reduce the surface roughness and the work-affected layer, and colloidal silica and fumed silica are preferable. The CMP solution preferably has a pH of 4 or less or a pH of 9.5 or more, more preferably a pH of 2 or less and a pH of 10.5 or more in order to increase chemical action. The pH of the CMP solution can be controlled by adding an inorganic acid, an organic acid, an inorganic alkali, an organic alkali, and a salt thereof. Moreover, it is preferable to add an oxidizing agent. As the oxidizing agent, chlorine-based oxidizing agents such as trichloroisocyanuric acid and dichloroisocyanuric salt, sulfuric acid, nitric acid, hydrogen peroxide water, and the like can be used. The pH can also be controlled by adding an oxidizing agent.

  Further, the first back surface of each of the plurality of single crystal substrates is also subjected to a surface finishing process in the same manner as the support substrate 10. In the present embodiment, both the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of support substrate 10 are subjected to surface finishing treatment. Only one of the first back surface of each of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 may be subjected to a surface finishing process.

  As described above, in the surface treatment process of the present embodiment, after finishing grinding and polishing, surface finishing treatment such as ion etching treatment and CMP treatment is performed.

  In the surface treatment step, the surface treatment is performed so that the ten-point average roughness of each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 is 2 μm or more and 20 μm or less. Is done. Preferably, the surface treatment is performed so that the ten-point average roughness of each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 is 2 μm or more and 20 μm or less.

  Preferably, in the surface treatment step, the ten-point average roughness of each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 is 3.3 μm or more and 16 μm or less. Surface treatment is performed so that More preferably, the surface treatment is performed so that the ten-point average roughness of each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 is 3.3 μm or more and 16 μm or less. Done.

  In the surface treatment step, the arithmetic average roughness of each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 is 0.16 μm or more and 0.95 μm or less. Surface treatment is performed so that Preferably, the surface treatment is performed so that the arithmetic average roughness of each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 is 0.16 μm or more and 0.95 μm or less. Done.

  Preferably, in the surface treatment step, the arithmetic average roughness of each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 is 0.23 μm or more and 0.8 μm. Surface treatment is performed so as to be as follows. More preferably, the surface treatment is performed so that the arithmetic average roughness of each of the first back surfaces of the plurality of single crystal substrates 1 to 9 and the second surface of the support substrate 10 is 0.23 μm or more and 0.8 μm or less. Is done.

  Next, as shown in FIG. 5, silicon carbide is the main component so that each of first back surfaces 1 b to 3 b of single crystal substrates 1 to 3 faces second surface 10 a of support substrate 10. Each of single crystal substrates 1 to 3 is arranged on support substrate 10 through fluid layer 41 that is a polymer. The polymer mainly composed of silicon carbide is, for example, polycarbosilane.

  At this time, similarly to the single crystal substrates 1 to 3, the single crystal substrates 4 to 9 (not shown in FIG. 5) are also arranged on the fluid layer 41, and thus the single crystal substrates 1 to 9 and the fluid layer 41. A plan view of the laminated body made of the supporting substrate 10 as viewed from the first surface side of the single crystal substrates 1 to 9 has the same configuration as FIG. Thereby, the laminated body 101 which consists of the single crystal substrates 1-9, the fluid layer 41, and the support substrate 10 is produced. Specifically, the laminate 101 is manufactured as follows.

  First, a fluid layer 41 containing polycarbosilane is formed on the second surface 10 a by applying or spraying a fluid containing polycarbosilane on the second surface 10 a of the support substrate 10. . The fluid layer 41 may be formed by heating and dissolving solid polycarbosilane. Next, the first back surfaces 1 b to 3 b of the single crystal substrates 1 to 3 are arranged on the fluid layer 41. Instead of this, the fluid layer 41 is formed on each of the first back surfaces 1 b to 3 b of the single crystal substrates 1 to 3, and the second surface 10 a of the support substrate 10 is disposed on the fluid layer 41. May be.

  In the step of forming a connection layer 11 (see FIG. 2) described later, the fluid layer 41 is provided between the support substrate 10 and the single crystal substrates 1 to 3 so that the thickness of the connection layer 11 is uniform. It is preferable to form with uniform thickness.

  The polycarbosilane contained in the fluid layer 41 is a polymer having a Si—C bond in the main chain as described above, and the number average molecular weight is preferably 600 to 4000. Further, the fluid containing polycarbosilane may be one obtained by dispersing or dissolving polycarbosilane in a solvent, and when the polycarbosilane itself is a fluid, it may be polycarbosilane itself. . As the solvent, an organic solvent having a low polarity such as xylene, hexane, or toluene can be suitably used.

  Here, polycarbosilane has a Si—C bond in the main chain, a bond between silicon and silicon (hereinafter also referred to as “Si—Si bond”), a bond between carbon and carbon (hereinafter referred to as “C—C”). It may also be referred to as a “bond”. For example, as an example of polycarbosilane, the main chain of polycarbosilane may have a repeating unit represented by the following chemical formula (1), and each represented by the following chemical formulas (2) and (3): You may have a repeating unit. Moreover, you may have the repeating unit with which following Chemical formula (1)-(3) was combined. However, in order for the connection layer 11 formed by converting polycarbosilane to be composed of a compound containing silicon carbide as a main component, at least 50% or more of the atoms constituting the main chain are Si—C bonds. It is preferable that Further, 70% or more is more preferably a Si—C bond, and more preferably 90% or more is a Si—C bond.

In the chemical formula (1), R _{1 to} R ₄ are each composed of a hydrogen group, an alkyl group having 1 to 5 carbon atoms, an alkenyl group, or an alkynyl group, and may be different from each other. In addition, R _{1 to} R ₄ contained in the repeating unit structure may be the same or different.

In chemical formula (2), R _{5 to} R ₁₀ are each composed of a hydrogen group, an alkyl group having 1 to 5 carbon atoms, an alkenyl group, or an alkynyl group, and may be different from each other. Further, R _{5 to} R ₁₀ contained in the repeating unit structure may be the same or different.

In the chemical formula (3), R _{11 to} R ₁₆ each consist of a hydrogen group, an alkyl group having 1 to 5 carbon atoms, an alkenyl group, or an alkynyl group, and may be different from each other. The plurality of R _{11 to} R ₁₆ contained in the main chain structure may be the same or different.

  Next, as shown in FIG. 2, the connection layer that connects the first back surface of each of the plurality of single crystal substrates 1 to 3 and the second surface of the support substrate 10 by converting the fluid layer 41. 11 is formed. Specifically, the polycarbosilane contained in the fluid layer 41 is converted to form the connection layer 11 mainly composed of silicon carbide (FIG. 3: step S30).

  For example, when the fluid layer 41 is heat-treated in an inert atmosphere, polycarbosilane is converted, and the solvent is volatilized and removed. Thereby, the fluid layer 41 is converted into the connection layer 11 containing silicon carbide as a main component.

  In the heat treatment, the fluid layer 41 is preferably heated at 1000 ° C. or higher and 2100 ° C. or lower. If the temperature is lower than 1000 ° C., silicon carbide of the fluid layer 41, which is a polymer, is insufficient and the bonding strength is lowered. On the other hand, at a temperature higher than 2100 ° C., the single crystal substrate and the support substrate 10 are sublimated. Therefore, it is preferable to heat the fluid layer 41 at 1000 ° C. or higher and 2100 ° C. or lower.

  By heating the fluid layer 41 at 1000 ° C. or more and 2100 ° C. or less, the fluid layer 41 changes to the connection layer 11 including at least one of amorphous, polycrystalline, and single crystal with voids. Preferably, the fluid layer 41 is thermally decomposed to form polycrystalline silicon carbide, amorphous silicon carbide, and single crystal silicon carbide having voids.

  Preferably, the step of disposing the support substrate 10 and each of the plurality of single crystal substrates via the fluid layer 41 includes a step of adding a silicon compound to the fluid layer 41. When fluid layer 41 contains more carbon than silicon, silicon carbide approaches stoichiometry by adding silicon. Thereby, the joining strength of the connection layer 11 can be increased.

  Preferably, the step of disposing the support substrate 10 and each of the plurality of single crystal substrates via the fluid layer 41 includes a step of adding a filler to the fluid layer 41. Thereby, when the fluid layer 41 is thermally decomposed, the fluid layer 41 can be prevented from shrinking excessively. Details of the connection layer 11 including the filler will be described later.

  As described above in detail, according to the silicon carbide substrate and the manufacturing method thereof of the present embodiment, a silicon carbide substrate having high connection strength between single crystal substrates 1 to 9 and support substrate 10 can be provided. Therefore, it is possible to effectively suppress the single crystal substrates 1 to 9 from being separated from the support substrate 10 in the manufacturing process of the semiconductor device such as a polishing process.

(Embodiment 2)
The present embodiment is different from the first embodiment in that the connection layer 11 contains a filler 71 made of silicon carbide. Hereinafter, differences from the first embodiment will be described.

  FIG. 6 is a cross sectional view schematically showing a structure of the silicon carbide substrate in the second embodiment of the present invention. Referring to FIG. 6, connection layer 11 contains filler 71 made of silicon carbide. Thereby, the shrinkage | contraction of the volume at the time of converting polycarbosilane and changing from the fluid layer 41 to the connection layer 11 can be suppressed.

  For example, as the filler 71, polycrystalline silicon carbide can be used. The content per volume of the filler 71 in the fluid layer 41 is preferably 10% by volume or more and 70% by volume or less. By setting it as 10 volume% or more, shrinkage | contraction can fully be suppressed, and the intensity | strength of the connection layer 11 can be hold | maintained by setting it as 70 volume% or less. The content of the filler 71 per volume is more preferably 20% by volume or more and 60% by volume or less. The connection layer 11 containing the filler 71 can be formed by the following method, for example.

  That is, in the above-described step S20, the single crystal substrates 1 to 3 are formed on the support substrate 10 through the fluid layer 41 in a state where the filler layer 71 is further contained in the fluid layer 41 containing polycarbosilane. Each is arranged to produce a laminate. Then, through the same process as in the first embodiment, silicon carbide substrate 200 having connection layer 11 shown in FIG. 6 can be created.

(Embodiment 3)
Referring to FIG. 7, semiconductor device 300 according to the third embodiment is a vertical DiMOSFET (Double Implanted Metal Oxide Semiconductor Field Effect Transistor), and includes silicon carbide substrate 100, epitaxial layer 20, oxide film 126, and source electrode 111. , Upper source electrode 127, gate electrode 110, and drain electrode 112. Epitaxial layer 20 includes a buffer layer 121, a breakdown voltage holding layer 122, a p region 123, an n + region 124, and a p + region 125.

  Silicon carbide substrate 100 has n-type conductivity in the present embodiment, and includes support substrate 10, connection layer 11, and single crystal substrate 1. Drain electrode 112 is provided on support substrate 10 of silicon carbide substrate 100.

Buffer layer 121 is provided on single crystal substrate 1 of silicon carbide substrate 100. Buffer layer 121 has n-type conductivity and has a thickness of 0.5 μm, for example. The concentration of the n-type conductive impurity in the buffer layer 121 is, for example, 5 × 10 ¹⁷ cm ⁻³ .

The breakdown voltage holding layer 122 is formed on the buffer layer 121 and is made of silicon carbide having an n-type conductivity. For example, the thickness of the breakdown voltage holding layer 122 is 10 μm, and the concentration of the n-type conductive impurity is 5 × 10 ¹⁵ cm ⁻³ .

  On the surface of the breakdown voltage holding layer 122, a plurality of p regions 123 having a p-type conductivity are formed at intervals. An n + region 124 is formed in the surface layer of the p region 123 inside the p region 123. A p + region 125 is formed at a position adjacent to the n + region 124. On the n + region 124 in one p region 123, from the p region 123, the breakdown voltage holding layer 122 exposed between the two p regions 123, the other p region 123, and the n + region 124 in the other p region 123 An oxide film 126 is formed so as to extend to. A gate electrode 110 is formed on the oxide film 126. A source electrode 111 is formed on the n + region 124 and the p + region 125. An upper source electrode 127 is formed on the source electrode 111.

The maximum value of the nitrogen atom concentration in the region within 10 nm from the interface between the oxide film 126 and the n + region 124, p + region 125, p region 123 and the breakdown voltage holding layer 122 as the semiconductor layer is 1 × 10 ²¹ cm ^−3. That's it. As a result, the mobility of the channel region under the oxide film 126 (the portion in contact with the oxide film 126 and the p region 123 between the n + region 124 and the breakdown voltage holding layer 122) can be improved. .

  Preferably, the surface 20a of the epitaxial layer 20 may have a special surface described below. Since the surface 20a of the epitaxial layer 20 has a special surface, the channel surface CH of the epitaxial layer 20 formed on the surface 20a of the epitaxial layer 20 can also have a special surface. As shown in FIG. 16, the surface 20a of the epitaxial layer 20 having a special surface includes a surface S1 (first surface). The plane S1 has a plane orientation {0-33-8}, and preferably has a plane orientation (0-33-8). Preferably, surface 20a of epitaxial layer 20 includes surface S1 microscopically. Preferably, surface 20a of epitaxial layer 20 further includes a surface S2 (second surface) microscopically. The plane S2 has a plane orientation {0-11-1}, and preferably has a plane orientation (0-11-1). Here, “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As a microscopic structure observation method, for example, a TEM (Transmission Electron Microscope) can be used.

  Preferably, surface 20a of epitaxial layer 20 has composite surface SR. The composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). Composite surface SR has a plane orientation {0-11-2}, preferably a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the {000-1} plane. Here, “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used. Preferably, the channel direction CD, which is the direction in which carriers flow on the channel surface CH, is along the direction in which the above-described periodic repetition is performed.

Next, the detailed structure of the composite surface SR will be described.
Generally, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, as shown in FIG. 17, Si atoms (or C atoms) are atoms of A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.

  As shown in FIG. 18, in the (11-20) plane (cross section taken along line XVIII-XVIII in FIG. 17), the atoms in each of the four layers ABCB constituting one cycle described above are (0-11-2). It is not arranged to be completely along the plane. In FIG. 18, the (0-11-2) plane is shown so as to pass through the position of the atoms in the B layer. In this case, the atoms in the A layer and the B layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when the atomic level structure is ignored is limited to (0-11-2), this surface is microscopic. Can take various structures.

  As shown in FIG. 19, in the composite surface SR, a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface on which the surface S1 and the surface S2 are averaged corresponds to the (0-11-2) surface (FIG. 18).

  As shown in FIG. 20, the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (part of the surface S1) equivalent to a cubic crystal when viewed partially. Specifically, in the composite surface SR, a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in. Thus, a plane having a plane orientation (001) in the structure equivalent to a cubic crystal (plane S1 in FIG. 20) and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 20). It is also possible for polytypes other than 4H to constitute the surface according to S2). The polytype may be 6H or 15R, for example.

  Next, the relationship between the crystal plane of the surface 20a of the epitaxial layer 20 and the mobility MB of the channel plane CH will be described with reference to FIG. In the graph of FIG. 21, the horizontal axis indicates the angle D1 formed by the macroscopic plane orientation of the surface 20a of the epitaxial layer 20 having the channel plane CH and the (000-1) plane, and the vertical axis indicates the mobility MB. . The plot group CM corresponds to the case where the surface 20a of the epitaxial layer 20 is finished as a special surface by thermal etching, and the plot group MC corresponds to the case where such thermal etching is not performed.

  The mobility MB in the plot group MC was maximized when the macroscopic plane orientation of the surface of the channel plane CH was (0-33-8). This is because when the thermal etching is not performed, that is, when the microscopic structure of the channel surface is not particularly controlled, the microscopic plane orientation is set to (0-33-8). This is probably because the ratio of the formation of the visual plane orientation (0-33-8), that is, the plane orientation (0-33-8) when considering even the atomic level is stochastically increased.

  On the other hand, the mobility MB in the plot group CM is maximized when the macroscopic surface orientation of the surface of the channel surface CH is (0-11-2) (arrow EX). The reason for this is that, as shown in FIGS. 19 and 20, a large number of surfaces S1 having a plane orientation (0-33-8) are regularly and densely arranged via the surface S2, so that the surface of the channel surface CH This is probably because the proportion of the microscopic plane orientation (0-33-8) has increased.

  The mobility MB has orientation dependency on the composite surface SR. In the graph shown in FIG. 22, the horizontal axis indicates the angle D2 between the channel direction and the <0-11-2> direction, and the vertical axis indicates the mobility MB (arbitrary unit) of the channel surface CH. A broken line is added to make the graph easier to see. From this graph, in order to increase the channel mobility MB, the angle D2 of the channel direction CD (FIG. 16) is preferably 0 ° or more and 60 ° or less, and more preferably approximately 0 °. all right.

  As shown in FIG. 23, the surface 20a of the epitaxial layer 20 may further include a surface S3 (third surface) in addition to the composite surface SR. In this case, the off angle of the surface 20a of the epitaxial layer 20 with respect to the {000-1} plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a {0-33-8} plane. More preferably, the off angle of the surface 20a of the epitaxial layer 20 with respect to the (000-1) plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.

  More specifically, the surface 20a of the epitaxial layer 20 may include a composite surface SQ formed by periodically repeating the surface S3 and the composite surface SR. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy).

  Next, a method for manufacturing the semiconductor device 300 will be described with reference to FIGS. FIG. 8 is a schematic flow diagram of the method for manufacturing a semiconductor device in the third embodiment, and FIGS. 9 to 12 are cross-sectional views schematically showing each step of the method for manufacturing the semiconductor device in the third embodiment. It is. 9 to 12 show only steps in the vicinity of the single crystal substrate 1 among the single crystal substrates 1 to 9 (see FIG. 1), but also in the vicinity of each of the single crystal substrates 2 to 9, Similar steps are performed.

  First, in the substrate preparing step (step S110) in FIG. 8, silicon carbide substrate 100 is prepared (see FIGS. 1 and 2).

  That is, silicon carbide substrate 100 is manufactured through steps S10 to S30 (FIG. 3) described in the first embodiment. In the present embodiment, for example, silicon carbide substrate 100 is introduced by introducing an n-type impurity such as nitrogen or phosphorus into silicon carbide constituting single crystal substrates 1 to 9, support substrate 10, and connection layer 11. The conductivity type can be n-type.

  Next, in the epitaxial layer forming step (step S120) of FIG. 8, the epitaxial layer 20 including the buffer layer 121 and the breakdown voltage holding layer 122 is formed as follows (see FIG. 9).

First, buffer layer 121 is formed on the surface of silicon carbide substrate 100. Buffer layer 121 is made of silicon carbide of n-type conductivity, and is an epitaxial layer having a thickness of 0.5 μm, for example. Further, the concentration of the conductive impurity in the buffer layer 121 is set to 5 × 10 ¹⁷ cm ⁻³ , for example.

Next, the breakdown voltage holding layer 122 is formed on the buffer layer 121. Specifically, a layer made of silicon carbide of n-type conductivity is formed by an epitaxial growth method. The thickness of the breakdown voltage holding layer 122 is, for example, 10 μm. The concentration of the n-type conductive impurity in the breakdown voltage holding layer 122 is, for example, 5 × 10 ¹⁵ cm ⁻³ .

Next, for example, the surface 20 a of the epitaxial layer 20 may be made the above-described special surface by thermally etching the epitaxial layer 20. Specifically, for example, it can be performed by heating the epitaxial layer 20 in an atmosphere containing at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ . By this thermal etching, a surface having a special surface is formed on the surface 20a of the epitaxial layer 20 by itself. Surface 20a of epitaxial layer 20 includes a first surface having a plane orientation {0-33-8}. The surface 20a of the epitaxial layer 20 may include the first surface microscopically and may further include a second surface having a plane orientation {0-11-1}. Further, the first surface and the second surface of the surface 20a of the epitaxial layer 20 may include a composite surface having a plane orientation {0-11-2}. Furthermore, the surface 20a of the epitaxial layer 20 may have an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} plane.

  Note that the step of thermally etching the epitaxial layer 20 may be performed after an implantation step and an activation annealing step described later. In this case, it is possible to prevent the atomic arrangement on the surface 20a of the epitaxial layer 20 from being disturbed by the implantation process or the activation annealing process.

  Next, in the implantation step of FIG. 8 (step S130), the p region 123, the n + region 124, and the p + region 125 are formed as follows (see FIG. 10).

  First, an impurity having a p-type conductivity is selectively implanted into a part of the breakdown voltage holding layer 122, whereby the p region 123 is formed. Next, n + region 124 is formed by selectively injecting n-type conductive impurities into a predetermined region, and p-type conductive impurities are selectively injected into the predetermined region. As a result, ap + region 125 is formed. The impurity is selectively implanted using a mask made of an oxide film, for example. After such an implantation step, an activation annealing process is performed. For example, annealing is performed in an argon atmosphere at a heating temperature of 1700 ° C. for 30 minutes.

  Next, in the gate insulating film forming step (step S140) in FIG. 8, an oxide film 126 as a gate insulating film is formed (see FIG. 11).

  Specifically, oxide film 126 is formed so as to cover the breakdown voltage holding layer 122, p region 123, n + region 124, and p + region 125. This formation may be performed by dry oxidation (thermal oxidation). The dry oxidation conditions are, for example, a heating temperature of 1200 ° C. and a heating time of 30 minutes.

  Next, annealing is performed in the nitrogen annealing step (step S150) of FIG.

  Specifically, an annealing process is performed in a nitrogen monoxide (NO) atmosphere. For example, the heating temperature is 1100 ° C. and the heating time is 120 minutes. As a result, nitrogen atoms are introduced near the interface between oxide film 126 and each of breakdown voltage holding layer 122, p region 123, n + region 124, and p + region 125. Note that an annealing process using an argon (Ar) gas that is an inert gas may be performed after the annealing process using nitrogen monoxide. The conditions for this treatment are, for example, a heating temperature of 1100 ° C. and a heating time of 60 minutes.

  Next, in the electrode formation step (step S160) of FIG. 8, the source electrode 111 and the drain electrode 112 are formed as follows (see FIG. 12).

  First, a resist film having a pattern is formed on the oxide film 126 by using a photolithography method. Using this resist film as a mask, portions of oxide film 126 located on n + region 124 and p + region 125 are removed by etching. As a result, an opening is formed in the oxide film 126. Next, a conductor film is formed in contact with each of n + region 124 and p + region 125 in this opening. Next, by removing the resist film, the portion of the conductor film located on the resist film is removed (lifted off). The conductor film may be a metal film, and is made of nickel (Ni), for example. As a result of this lift-off, the source electrode 111 is formed. In addition, it is preferable that the heat processing for alloying is performed here. For example, heat treatment is performed for 2 minutes at a heating temperature of 950 ° C. in an atmosphere of argon (Ar) gas that is an inert gas.

  Further, upper source electrode 127 is formed on source electrode 111, and drain electrode 112 is formed on the back surface of silicon carbide substrate 100 (see FIG. 7). Then, the stacked body is divided for each semiconductor device by dicing. Thereby, semiconductor device 300 including silicon carbide substrate 100 having first surface 1a of single crystal substrate 1 is obtained.

  Further, after the upper source electrode 127 is formed on the source electrode 111, the supporting substrate 10 and the connection layer 11 can be removed by back surface grinding to leave only the single crystal substrate 1. This single crystal substrate 1 A drain electrode 112 may be formed on the back surface of the electrode. For example, when the high-resistance support substrate 10 is used, the resistance of the semiconductor device can be reduced by removing the support substrate 10 in this way. Moreover, the thickness of the single crystal substrate 1 can also be reduced by back surface grinding. By reducing the thickness of the single crystal substrate 1, the resistance of the semiconductor device can be further reduced.

  Note that a configuration in which the conductivity types in this embodiment are interchanged, that is, a configuration in which p-type and n-type are interchanged can also be used.

  In addition, the semiconductor substrate for manufacturing semiconductor device 300 is not limited to silicon carbide substrate 100 of the first embodiment, and may be, for example, silicon carbide substrate 200 obtained by the second embodiment.

  In the present embodiment, the vertical DiMOSFET is exemplified. However, other semiconductor devices may be manufactured using the silicon carbide substrate of the present invention. For example, RESURF-JFET (Reduced Surface Field-Junction Field Effect Transistor). Alternatively, a Schottky diode may be manufactured.

  According to the method for manufacturing semiconductor device 300 of the present embodiment, the bonding strength between each of the plurality of single crystal substrates 1 to 9 and support substrate 10 is increased. Therefore, the single crystal substrates 1 to 9 can be prevented from peeling from the support substrate 10 in the manufacturing process of the semiconductor device such as a polishing process. As a result, the yield of the semiconductor device 300 can be improved.

  In this example, the influence of the surface roughness of the bonding surface between the single crystal substrate (tile substrate) and the support substrate 10 on the tensile strength and the fracture yield of the single crystal substrate and the support substrate 10 was investigated.

  Samples (Sample 1 to Sample 15) of 15 kinds of bonded substrates (silicon carbide substrate 100) having different surface roughnesses of the bonding surfaces of the single crystal substrate and the support substrate 10 were manufactured. The 15 types of bonded substrates were manufactured by the manufacturing method described in the first embodiment. Specifically, first, 15 types of single crystal substrates and support substrates 10 having different surface roughnesses were prepared. The surface roughness was controlled by the abrasive grain size, surface plate material, load and etching method. The production conditions of each sample are shown in Table 1.

As shown in Table 1, the size of the abrasive grains was controlled in the range of 3 μm to 15 μm. The load applied to the substrate to be polished was controlled in the range of 250 g / cm ^{2 to} 400 g / cm ² . In Table 1, Sn means a surface plate of Sn (tin), Cu means a surface plate using a mixture of Cu (copper) and resin, and Fe is a mixture of Fe (iron) and resin. It means a surface plate using. In Table 1, KOH means molten KOH (potassium hydroxide) etching, and DE means reactive ion etching using CF ₄ . After the surface treatment was performed on the single crystal substrate and the support substrate 10, the single crystal substrate and the support substrate 10 were connected via the connection layer 11. In this way, 15 types of bonded substrate samples (Sample 1 to Sample 15) having different surface roughnesses of the bonding surfaces of the single crystal substrate and the support substrate 10 were manufactured. The tensile strength of the single crystal substrate and the support substrate 10 was measured using the 15 types of bonded substrates.

Table 10 shows the ten-point average roughness (R _z ) and arithmetic average roughness (R _a ) of the single crystal substrate and the support substrate 10 that were surface-treated under the conditions described in Table 1. Table 2 also shows the tensile strength of the single crystal substrate and the support substrate 10. In addition, the measurement of tensile strength was implemented with the following method. First, the single crystal substrate and the support substrate 10 were connected via the connection layer 11. When one of the support substrate 10 and the single crystal substrate was fixed and the other was pulled in a direction perpendicular to the surface of the support substrate 10, the strength at which the single crystal substrate peeled off from the support substrate was taken as the tensile strength.

  As shown in Table 2, when the ten-point average roughness of the single crystal substrate and the support substrate 10 is 2 μm or more and 20 μm or less, the tensile strength of the single crystal substrate and the support substrate 10 may be 0.6 MPa or more and 28 MPa or less. confirmed. In addition, when the arithmetic average roughness of the single crystal substrate and the support substrate 10 is 0.16 μm or more and 0.95 μm or less, it is confirmed that the tensile strength of the single crystal substrate and the support substrate 10 is 0.6 MPa or more and 28 MPa or less. It was.

  Next, bonded substrates having different tensile strengths were prepared, and the first surface of the single crystal substrate was ground and polished under the following conditions to investigate the fracture yield of the single crystal substrate. The fracture yield is a numerical value indicating the ratio of the number of samples in which the single crystal substrate did not peel from the support substrate 10 among all the samples subjected to grinding and polishing.

Here, the grinding and polishing conditions of the single crystal substrate will be described. Grinding was performed using a vitrified wheel. Mechanical polishing (MP) was performed using diamond abrasive grains. CMP was performed using the CMP apparatus described in the first embodiment. Colloidal silica was used as an abrasive. The load applied to the bonded substrate was 250 g / cm ² . A suede polishing cloth was used.

  Next, the relationship between the tensile strength of the single crystal substrate and the support substrate 10 and the fracture yield will be described with reference to Table 3.

  Sample 16 is a sample in which the tensile strength between the single crystal substrate and the support substrate 10 is 0.3 MPa, and Samples 17 to 23 are samples in which the tensile strength between the single crystal substrate and the support substrate 10 is 0.6 MPa or more. is there. As shown in Table 3, it was confirmed that when the tensile strength was 0.6 MPa or more, the fracture yield was rapidly improved. It was also confirmed that the fracture yield was further improved when the tensile strength between the single crystal substrate and the support substrate 10 was 2 MPa or more.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1-9 single crystal substrate, 1a-3a first surface, 1b-3b first back surface, 10 support substrate, 10a second surface, 10b second back surface, 11 connection layer, 20 epitaxial layer, 20a surface, 41 fluid layer, 50 reactive ion etching apparatus, 52 chamber, 54 upper electrode, 56 lower electrode, 58 substrate support, 60 gas supply port, 62 gas exhaust port, 64 high frequency power supply, 71 filler, 100, 200 silicon carbide Substrate, 101 stack, 110 gate electrode, 111 source electrode, 112 drain electrode, 121 buffer layer, 122 breakdown voltage holding layer, 123 p region, 124 n + region, 125 p + region, 126 oxide film, 127 upper source electrode, 170 lapping Equipment, 172 Base surface plate, 174 Surface plate, 176,276 Crystal holder, 1 78,278 Weight, 180,280 Slurry supply port, 270 CMP apparatus, 300 semiconductor device.

Claims (21)

A plurality of single crystal substrates each made of silicon carbide and having a first surface and a first back surface facing each other;
A support substrate made of silicon carbide and having a second surface and a second back surface facing each other;
Each of the first back surface and the second surface are interposed between the plurality of single crystal substrates and the support substrate so that each of the first back surface and the second surface oppose each other. And a connection layer for connecting
A silicon carbide substrate in which a tensile strength between the single crystal substrate and the support substrate is 0.6 MPa or more.   The silicon carbide substrate according to claim 1, wherein the tensile strength is 2 MPa or more and 20 MPa or less.   The silicon carbide substrate according to claim 1 or 2, wherein a main component of a material constituting the connection layer is silicon carbide.   4. The silicon carbide substrate according to claim 1, wherein a ten-point average roughness of each of the first back surface and at least one of the second surface is 2 μm or more and 20 μm or less. 5.   5. The silicon carbide substrate according to claim 1, wherein an arithmetic average roughness of at least one of each of the first back surface and the second surface is 0.16 μm or more and 0.95 μm or less.   The silicon carbide substrate according to claim 1, wherein the diameter is 110 mm or more. Each of the plurality of single crystal substrates has a hexagonal crystal structure and a polytype of 4H,
The silicon carbide substrate according to any one of claims 1 to 6, wherein the first surface is a surface whose plane orientation is turned off by 5 ° or less from a {0-11-2} plane. A plurality of single crystal substrates each made of silicon carbide and having a first surface and a first back surface facing each other, and a support substrate made of silicon carbide and having a second surface and a second back surface facing each other And a step of preparing
Surface treatment so that the ten-point average roughness of each of the first back surface and at least one of the second surface is 2 μm or more and 20 μm or less;
The support substrate and each of the plurality of single crystal substrates via a fluid layer such that each of the first back surfaces of the plurality of single crystal substrates faces the second surface of the support substrate. A step of arranging
A method of manufacturing a silicon carbide substrate, comprising: converting the fluid layer to form a connection layer that connects each of the first back surface and the second surface. A plurality of single crystal substrates each made of silicon carbide and having a first surface and a first back surface facing each other, and a support substrate made of silicon carbide and having a second surface and a second back surface facing each other And a step of preparing
Surface treatment so that the arithmetic average roughness of each of the first back surface and at least one of the second surface is 0.16 μm or more and 0.95 μm or less;
The support substrate and each of the plurality of single crystal substrates via a fluid layer such that each of the first back surfaces of the plurality of single crystal substrates faces the second surface of the support substrate. A step of arranging
A method of manufacturing a silicon carbide substrate, comprising: converting the fluid layer to form a connection layer that connects each of the first back surface and the second surface. The fluid layer is composed of a polymer mainly composed of a substance that becomes silicon carbide by heating,
In the step of forming the connection layer, polycrystalline silicon carbide, amorphous silicon carbide, and single crystal silicon carbide having voids are formed by thermally decomposing the fluid layer. A method for manufacturing a silicon carbide substrate.   The method for producing a silicon carbide substrate according to claim 10, wherein the step of forming the connection layer is performed by heating the fluid layer at 1000 ° C. or higher and 2100 ° C. or lower.   The method for manufacturing a silicon carbide substrate according to any one of claims 8 to 11, wherein the fluid layer includes a filler made of silicon carbide.   The method for manufacturing a silicon carbide substrate according to claim 8, wherein the fluid layer includes a silicon compound.   The method for manufacturing a silicon carbide substrate according to claim 8, wherein the surface treatment includes a step of polishing each of the first back surface and at least one of the second surface.   The silicon carbide substrate according to claim 14, wherein the surface treatment includes a step of etching at least one of each of the first back surface and the second surface after the polishing treatment. Method. A single crystal substrate made of silicon carbide and having a first surface and a first back surface facing each other, and a support substrate made of silicon carbide and having a second surface and a second back surface facing each other are prepared. And a process of
Surface treatment so that the ten-point average roughness of each of the first back surface and at least one of the second surface is 2 μm or more and 20 μm or less;
A connection layer that is interposed between the single crystal substrate and the support substrate and joins the first back surface and the second surface so that the first back surface and the second surface face each other. Preparing a silicon carbide substrate having:
Forming an epitaxial growth layer on the single crystal substrate;
And a step of forming an electrode on the epitaxial growth layer. A plurality of single crystal substrates each made of silicon carbide and having a first surface and a first back surface facing each other;
A support substrate made of silicon carbide and having a second surface and a second back surface facing each other;
Each of the first back surface and the second surface are interposed between the plurality of single crystal substrates and the support substrate so that each of the first back surface and the second surface oppose each other. A connection layer for connecting
An epitaxial growth layer provided on the single crystal substrate;
An electrode provided on the epitaxial growth layer,
A semiconductor device, wherein a tensile strength between the single crystal substrate and the support substrate is 0.6 MPa or more. The silicon carbide forming the epitaxial layer has a hexagonal crystal structure and a polytype of 4H,
The surface of the said epitaxial layer is a semiconductor device of Claim 17 containing the 1st surface which has a surface orientation {0-33-8}.   The surface of the epitaxial layer microscopically includes the first surface, and the first surface further microscopically includes a second surface having a plane orientation {0-11-1}. Item 19. A semiconductor device according to Item 18.   The semiconductor device according to claim 19, wherein the first surface and the second surface of the surface of the epitaxial layer include a composite surface having a plane orientation {0-11-2}.   21. The semiconductor device according to claim 20, wherein the surface of the epitaxial layer has an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} plane.

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