JP2013250616A - Method for stopping electric power for auxiliary storage device and computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect writing data to an HDD, when a computer is shut down in a state where a system does not recognize it.SOLUTION: An HDD 121 includes two interfaces, which are SATA and DEVSLP. When a system 101 cannot transmit a command showing being shut down through a SATA interface, an EC 115 generates a shut down event and asserts the DEVSLP. When the DEVSLP is asserted, the HDD is shifted to a power saving mode. The HDD writes data stored in a cache to a magnetic disk before being shifted to the power saving mode. The EC shuts down a computer 100, when a predetermined time elapses from generation of the shut down event.

Description

  The present invention relates to a technology for protecting an auxiliary storage device whose power is stopped at an unexpected timing, and more particularly to a technology for preventing loss of write data and physical damage to the auxiliary storage device.

  In addition to the main storage device (main memory), the computer is equipped with an auxiliary storage device such as a hard disk drive (HDD) using a magnetic disk or a solid state drive (SSD) using a flash memory. The computer writes the data that needs to be saved in the volatile main memory (RAM) and various caches to the auxiliary storage before shutting down.

  Software such as an operating system (OS), BIOS, and utility programs, and CPU, RAM, and chipsets that execute the software constitute a computer system. When the user performs a shutdown operation through the mouse or the keyboard, the system writes data stored in the RAM, cache, etc. to the auxiliary storage device, and then stops the DC / DC converter. At this time, the system sends a power stop command to the auxiliary storage device in advance. The auxiliary storage device that has received the command writes necessary data to the nonvolatile storage medium and notifies the system when the power can be stopped.

  By the way, the computer may shut down in a state where the system does not recognize or in a state where the system cannot send a power stop command to the auxiliary storage device. Hereinafter, stopping the power supply in such a state is referred to as a surprise shutdown. For example, computer systems may hang due to hardware or software malfunctions.

  Depending on the severity of the hang, it may be necessary to force the computer to shut down to recover. Since a hung system cannot be shut down, the user performs a so-called power button override that continuously presses the power button for more than 4 seconds, or removes the power plug to remove the computer. Force shutdown. The computer may also shut down automatically when it hangs up. Such a shutdown is a surprise shutdown.

  Furthermore, in notebook personal computers (notebook PCs), in order to ensure physical safety, such as system devices and power supply devices, a controller composed of firmware and hardware that operates in an environment independent of the system is installed. Mount. Such a controller suddenly shuts off the computer where the system does not recognize when safety needs to be a priority. In this case also, a surprise shutdown occurs.

  Patent Document 1 describes a power button override mechanism for avoiding a shutdown accompanied by user's carelessness or file loss. The mechanism unconditionally shuts down a locked computer by pressing the power button for more than 4 seconds.

  Patent Document 2 discloses an invention in which data stored in a main memory when a computer hangs up is stored and protected in an HDD before shutdown. Japanese Patent Application Laid-Open No. 2004-228561 discloses an invention in which a magnetic head is urgently retracted using a back electromotive force of a spindle motor when the HDD power is stopped. Patent Document 4 discloses an invention in which the flexure is retracted to the loading position using the power stored in the capacitor when the power of the HDD is stopped.

  Non-Patent Document 1 describes device sleep (DevSleep) defined by SATA (Serial ATA). Device sleep achieves a further reduction in power consumption compared to conventional SATA devices. A conventional SATA device shifts to a power saving mode when a command is received from a host through a SATA interface to reduce physical layer power. A SATA device having a device sleep function includes an interface for receiving a DEVSLP signal from a host apparatus in addition to the SATA interface.

When the DEVSLP signal is asserted, the SATA device transitions to a power saving mode (deep sleep state) that consumes less power than a power saving mode that receives and transitions to a command as in the prior art. The transition between the deep sleep state and the power-on state is controlled by the host device by the DEVSLP signal. Since the rotation of the magnetic disk stops in the deep sleep state, the HDD retracts (unloads) the head / slider to the ramp before transitioning to the deep sleep state. In the deep sleep state, the power of the cache is stopped, so the SSD writes the data stored in the cache to the flash memory before transitioning to the deep sleep state. Non-Patent Document 1 can be obtained from the Internet at the following URL.
http://www.sata-io.org/documents/SATA-DevSleep-and-RTD3-WP.pdf

US Pat. No. 6,587,951 JP 2012-8672 A JP 2001-307408 A Japanese Patent Laid-Open No. 5-205386

Serial ATA Device Sleep (DevSleep) and Runtime D3 (RTD3), December 2011, AWHIPAPER BY: Intel Corporation, SanDisk Corporation

  When a surprise shutdown occurs, the system cannot send a command to stop power to the auxiliary storage device in advance. In the HDD, the airflow generated on the surface due to the rotation of the magnetic disk gives buoyancy to the head / slider attached to the suspension, thereby maintaining a minute gap between the head / slider and the magnetic disk. If the rotation of the magnetic disk stops while the head / slider is flying over the magnetic disk, the head / slider contacts the surface of the disk.

  If the magnetic disk is rotated by supplying electric power in the next contact state, the magnetic disk or the head / slider may be damaged. Therefore, before the HDD stops rotating, the HDD moves the suspension to a predetermined parking position. Evacuate. When the HDD receives a command in advance, it can retract the suspension before the rotation of the magnetic disk stops, but it cannot do it during a surprise shutdown. If the technique of Patent Document 3 or Patent Document 4 is adopted, physical damage to the HDD due to a surprise shutdown can be prevented.

  However, since an HDD having such a mechanism increases costs, it is advantageous if the same can be realized on the host side. Some HDDs employ a so-called write-back method in which the host device recognizes the completion of writing when writing data is written to the cache in order to shorten the writing time. In the write back method, it is necessary to write the write data stored in the cache to the magnetic disk before stopping the power of the HDD.

  In addition, the SSD includes a cache therein in order to reduce the frequency of writing to the NAND type cell and extend the life. When the SSD receives a command in advance from the host device, the cache data can be written to the cell before the power is stopped, but the cache data is lost in a surprise shutdown. In addition, the NAND type cell has a limitation in the number of times of rewriting, overwriting cannot be performed, and writing is performed in units of pages and erasing is performed in units of blocks in which a plurality of pages are combined.

  The SSD performs an operation called wear leveling for leveling the cells to be written when there is no access from the system in order to extend the life of the cells. If a surprise shutdown occurs during wear leveling, the stored data will be lost. Therefore, the SSD receives a power stop command from the host device and stops wear leveling before the power stops. It is necessary to do. In the SSD and the write-back type HDD, the host device recognizes that the writing is completed when the data is written to the cache. Therefore, when a surprise shutdown occurs thereafter, the data recognized by the host device and the auxiliary storage device A wrinkle occurs between the data that is actually stored.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for preventing an auxiliary storage device from being damaged by a surprise shutdown. It is a further object of the present invention to provide a method for preventing write data from being lost from an auxiliary storage device due to a surprise shutdown. It is a further object of the present invention to provide a computer and a host device that implement such a method.

  The present invention provides a method for preventing a trouble that occurs in an auxiliary storage device when the power of the auxiliary storage device is suddenly stopped. In the present invention, in addition to the first interface for transferring commands and data to the auxiliary storage device, the second interface can know the timing at which the auxiliary storage device performs a preparatory operation for stopping at least part of the power. Is provided. When an event indicating a surprise shutdown is generated, the host device temporarily suspends the process of stopping the power of the auxiliary storage device, asserts the second interface, and supplies power when the preparation operation in the auxiliary storage device is completed. Stop.

  In the first aspect of the present invention, the host device first writes data to the auxiliary storage device through the first interface. Next, the host device generates an event for stopping the power of the auxiliary storage device. Next, in response to the event, the host device asserts the second interface. Next, in response to the assertion of the second interface, the auxiliary storage device performs a preparation operation for stopping the power. Next, when a predetermined time elapses after the second interface is asserted, the host device stops the power of the auxiliary storage device.

  In the above configuration, even if the host device hangs up or a device operating in an environment different from the system generates an event and the command cannot be sent in advance through the first interface, the host device is in the second state. Is asserted to cause the auxiliary storage device to perform a preparatory operation for stopping power. The host device can prevent physical damage or data loss of the auxiliary storage device by stopping the power when a predetermined time elapses after the second interface is asserted until the preparation operation is completed. .

  The auxiliary storage device can be an HDD or an SSD. In the case of the HDD, the preparation operation can be either a head / slider retraction operation or a cache flush operation. In the case of SSD, the preparatory operation can be a cache flush operation. Note that the preparation operation need not be limited to such an example, and can be any processing necessary to prevent a trouble when power is suddenly stopped without receiving a command.

  A second aspect of the present invention provides a method for shutting down a computer to which an auxiliary storage device having a first interface and a second interface is connected. First, data is written to the auxiliary storage device via the first interface. Next, a shutdown event is generated in an environment that the system does not recognize. Next, the computer asserts the second interface in response to the shutdown event. Next, in response to the assertion of the second interface, the auxiliary storage device performs a preparation operation for stopping power. Next, the computer shuts down when a predetermined time elapses after the second interface is asserted. The power state of the computer when the computer is shut down can be the S5 state defined in ACPI.

  In the preparatory operation, cache write data can be written to a nonvolatile storage medium. A shutdown event can be generated when the system is unable to send a command indicating shutdown to the auxiliary storage device through the first interface. Specifically, it can be generated when the power button is pressed for a certain time or when the system hangs up. The shutdown event may be generated when an abnormality occurs in the temperature of the device or the state of the device that supplies power. The second interface may be a device sleep (DevSleep) for shifting to a power saving mode defined by SATA.

  According to the present invention, it is possible to provide a method for preventing the auxiliary storage device from being damaged by the surprise shutdown. Furthermore, according to the present invention, it is possible to provide a method for preventing the loss of data written to the auxiliary storage device due to a surprise shutdown. Further, according to the present invention, it is possible to provide a computer and a host device that realize such a method.

It is a functional block diagram which shows the structure of the notebook PC provided with the protection function of HDD. 10 is a flowchart illustrating a procedure for protecting the HDD when a surprise shutdown occurs.

  FIG. 1 is a functional block diagram showing a configuration of a notebook PC having an HDD protection function. The notebook PC 100 conforms to the ACPI standard and transitions to one of the power states of working state (G0 / S0), sleeping state (G1 / S3 / S4), and soft off state (G2 / S5) can do. However, whether or not the notebook PC 100 transitions to the sleeping state does not directly affect the application of the present invention.

  The S0 state is a state in which the system including the CPU operates and is also called power-on. The S3 state is a power saving state in which the storage of the main memory is held, and is also called suspend. The S4 state is a power saving state in which the OS saves the context in the nonvolatile memory and is also called hibernation. The S5 state has the least power consumption and is also called power-off. In the S5 state, power is supplied only to the minimum devices necessary to start up the power supply of the notebook PC 100.

  The notebook PC transitions to the S5 state when a surprise shutdown occurs in the S0 state. In the present embodiment, when a surprise shutdown occurs, the state shifts to the S5 state. However, the power state at the time of the surprise shutdown does not need to exactly match the S5 state and is separate from the S5 state. It may be defined. In the power state other than the S0 state, the power of the HDD 121 is stopped.

  The system 101 includes hardware 103 and software 105. The hardware 103 includes a CPU, a RAM, a chip set, a bus that connects them, and the like. The software 105 includes an OS, a BIOS, a device driver, an application program, and the like. The user can set a power management policy for controlling the power of the notebook PC 100 in the OS.

  The hardware logic circuit 107 is configured as a part of a chip set included in the hardware 103 as an example, and includes a logic circuit, a register, and a timer. The hardware logic circuit 107 is connected to the embedded controller (EC) 115 via four signal lines PWRBTN, SLP_S3, SLP_S4, and SLP_S5, and functions as an interface related to power management of the system 101 and the EC 115. The system 101 can instruct the hardware logic circuit 107 according to the power management policy to cause the notebook PC 100 to transition from the S0 state to the S3 state, the S4 state, or the S5 state.

  When the system 101 asserts one of the SLP_S5 signal, the SLP_S4 signal, and the SLP_S3 signal, the notebook PC 10 transitions to any one of the S5 state, the S4 state, and the S3 state. For example, the system 101 automatically asserts the SLP_S3 signal when the remaining capacity of the battery pack is low in the S0 state and makes a transition to the S3 state, and further sends the SLP_S4 signal when the remaining capacity is low. It can be asserted to transition to the S4 state. Alternatively, the system 101 can automatically transition to the S3 state or the S4 state when the idle time continues for a certain time or longer. Furthermore, when the user performs a shutdown operation through the screen, the system 101 can transition to the S5 state by asserting the SLP_S5 signal through the hardware logic circuit 107.

  As an example, the EC 115 is connected to the system 101 by an SCI (Serial Communication Interface) bus. The system 101 and the EC 115 transfer data and commands through the SCI bus. The EC 115 includes a CPU, a RAM, a ROM, a timer, and the like, and executes firmware stored in the ROM in an environment independent of the system 101 to control the power supply and temperature of the notebook PC 100. Further, the EC 115 performs an operation for executing the firmware to protect the HDD 115 when a surprise shutdown occurs.

  A power button 109, a thermal sensor 111, and a heat exhaust fan 113 are connected to the EC 115. The power button 109 shifts the power state of the notebook PC 100 when the system 101 is in a normal state, or performs a power button override when the system 101 hangs up to perform a surprise shutdown. The power button 109 is attached to the casing of the notebook PC 100 so that the user can press it.

  The user can set the power state of the transition destination when the power button 109 is pressed in the S0 state in the register of the hardware logic circuit 107 through the OS. The EC 115 outputs a PWRBTN signal to the hardware logic circuit 107 while the power button 109 is pressed. The hardware logic circuit 107 sends the received PWRBTN signal to the system 101. Receiving the PWRBTN signal, the system 101 instructs the hardware logic circuit 107 to output either the SLP_S3 signal or the SLP_S4 signal based on the power management policy.

  The hardware logic circuit 107 measures the time during which the power button 109 is continuously pressed, that is, the time during which the PWRBTN signal is continuously received. When the hardware logic circuit 107 continuously receives the PWRBTN signal for about 4 seconds, the hardware logic circuit 107 determines that a power button override has occurred and asserts all of the SLP_S3 to SLP_S5 signals. Even when the system 101 hangs up, the hardware logic circuit 107 can measure the time during which the PWRBTN signal is received and assert all the SLP_S3 to SLP_S5 signals.

  The hardware logic circuit 107 can monitor the operation of the CPU and assert all the SLP_S3 to SLP_S5 signals when determining that the system 101 has hung up. When all of the SLP_S3 to SLP_S5 signals are asserted, the EC 115 generates a surprise shutdown event to cause the notebook PC 100 to perform a surprise shutdown regardless of whether the system 101 is hung up or not.

  The thermal sensor 111 includes a plurality of thermistors, and measures the temperature inside the casing of the notebook PC 100 and the temperature of the device. The exhaust heat fan 113 suppresses the temperature rise of the device and the surface of the casing by exhausting high temperature air inside the casing via the heat sink. When the temperature detected by the thermal sensor 111 rises, the EC 115 increases the rotational speed of the exhaust heat fan 113 or performs throttling control of the CPU. Instructed to transition to the S4 state. The EC 115 operates independently from the transition operation to the S3 state or the S4 state by the system 101, generates a surprise shutdown event when the detected temperature of the thermal sensor 111 exceeds a predetermined value, and sets the notebook PC 100 to the surprise Shut down.

  The power source 117 includes an AC / DC adapter and a battery pack, and supplies power to the DC / DC converter 119. The DC / DC converter 119 converts the voltage supplied from the power source 117 into a plurality of predetermined voltages used by the notebook PC 100. The DC / DC converter 119 is divided into an S5 system, an S4 system, an S3 system, and an S0 system so that power can be supplied to a device that operates according to the power state.

  Devices that operate in the S5 state are connected to the S5 system, devices that operate in the S4 state are connected to the S4 system, devices that operate in the S3 state are connected to the S3 system, and other devices are connected to the S0 state. It is connected. The system corresponding to the lower power state operates even in the upper power state. For example, in the S3 state, not only the S3 system but also the S5 system and the S4 system operate.

  The DC / DC converter 119 of the S5 system is configured with a series regulator having excellent efficiency at light load, and the DC / DC converter 119 of the other system is configured with a switching regulator having excellent efficiency at heavy load. Has been. When a surprise shutdown occurs, the DC / DC converter 119 operates only the S5 system and stops the operation of other systems.

  The EC 115 controls the DC / DC converter 119 so as to supply power only to a device corresponding to the power state. The EC 115 monitors the state of the voltage and current of the DC / DC converter 119. When the EC 115 detects an abnormality, the EC 115 generates a surprise shutdown event to cause the notebook PC 100 to perform a surprise shutdown. The EC 115 generates a surprise shutdown event when the temperature of the battery cell housed in the battery pack of the power source 117 reaches a predetermined value, and causes the notebook PC 100 to surprise shutdown. The HDD 121 conforms to the SATA standard, is connected to the chip set of the system 101 through the SATA interface, and is further connected to the output of the OR logic element 123 through the DEVSLP line. The hardware 103, the hardware logic circuit 107, and the EC 115 are connected to the input of the OR logic element 123.

  When the hardware 103, the hardware logic circuit 107, or the EC 115 asserts the DEVSLP signal through the DEVSLP line, the HDD 121 shifts to the deep sleep state and the power consumption is minimized. According to the SATA standard, the manufacturer may decide what operation the HDD will perform when the DEVSLP signal is asserted. In the deep sleep state, the rotation of the magnetic disk of the HDD 121 is stopped and the power of the cache is also stopped. Therefore, when DEVSLP is asserted, the HDD 121 retracts the head / slider to the ramp mechanism arranged around the magnetic disk and then stops the rotation of the magnetic disk.

  Further, when the HDD 121 adopts the write back method, the write data stored in the cache is written to the magnetic disk before the cache power is stopped in the deep sleep state. The HDD 121 is supplied with power from the S0 system of the DC / DC converter 119. Alternatively, the DC / DC converter 119 may supply power to the HDD 121 from a dedicated system.

  Note that FIG. 1 is merely a simplified description of the main configuration and connection relations related to the present embodiment in order to describe the present embodiment. A person skilled in the art also arbitrarily selects a plurality of blocks described in the figure as one integrated circuit or device, or conversely, a block is divided into a plurality of integrated circuits or devices. Is included in the scope of the present invention.

  In particular, the roles of the hardware logic circuit 107 and the EC 115 in this embodiment are described as an example, and can be realized by other devices that can operate in an environment independent of the system 101. In addition, the types of buses and interfaces connecting the devices are merely examples, and other connections are included in the scope of the present invention as long as those skilled in the art can arbitrarily select them. It is.

  Next, a procedure for protecting the HDD when a surprise shutdown occurs will be described with reference to the flowchart of FIG. In block 201, the notebook PC 100 transitions to the S0 state and operates normally. During this time, the system 101 writes data to the HDD 121. When the user performs a shutdown operation through the screen, the system 101 stores necessary data in the HDD 121 in the data stored in the main memory or the cache.

  The OS stops notification from the S0 system to the S4 system of the DC / DC converter 119 through the EC 115 after receiving a notification that the preparation for shutdown has been completed from an application or a device driver. In this way, when a series of sequences processed by the system 101 is executed and shutdown is performed, no trouble occurs in the HDD 121. In the following procedure, a surprise shutdown executed in a state that the system 101 does not recognize is processed. At block 203, the user can press the power button 109 to transition the notebook PC 100 to a sleeping state or a soft-off state. When the power button 109 is pressed, the process moves to block 221.

  In block 221, the EC 115 sends a PWRBTN signal to the hardware logic circuit 107. The hardware logic circuit 107 sends a PWRBTN signal to the system 101. Receiving the PWRBTN signal, the system 101 starts processing for shifting to the sleeping state based on a preset power management policy. In addition, the hardware logic circuit 107 that has received the PWRBTN signal measures the time during which the PWRBTN signal continues.

  When the duration of the PWRBTN signal is less than 4 seconds as an example, the system 101 causes the notebook PC to transition to the S4 state or the S3 state in block 225. When the duration of the PWRBTN signal is 4 seconds or more, the hardware logic circuit 107 asserts all the SLP_S3 to SLP_5 signals. The system 101 also starts the procedure of block 225 when the duration of the PWRTN signal is 4 seconds or more, but cannot complete because a surprise shutdown occurs as described below. In block 223, the EC 115 generates a surprise shutdown event when the signals SLP_S3 to SLP_5 are all asserted, and proceeds to block 231.

  In block 231, the EC 115 or the hardware logic circuit 107 asserts the DEVSLP signal in response to a surprise shutdown event being generated. The HDD 121 to which the DEVSLP signal is asserted retracts the head / slider to the parking position in block 232, and further writes the write data stored in the cache to the magnetic disk and flushes it. When the head / slider evacuation and cache flushing are completed, the HDD 121 leaves only the power necessary for returning when the DEVSLP signal is negated, and the spindle motor, interface, cache, etc. that rotate the magnetic disk The power of the physical layer composed of the semiconductor circuit is stopped and the state transits to the deep sleep state. For example, the HDD 121 is configured to be able to shift to the deep sleep state within 10 milliseconds after the DEVSLP signal is asserted.

  In block 233, the EC 115 causes the S0 system of the DC / DC converter 119 in block 235 when the elapsed time from asserting the DEVSLP signal or the elapsed time since generating the surprise shutdown event reaches 10 milliseconds. To the S4 system, the notebook PC 100 is shifted to the S5 state. The power button override procedure of blocks 223, 231, 233, and 235 is processed by the hardware logic circuit 107 and the EC 115 independent of the system 101, and can be executed even when the system 101 is hung up.

  However, the power button override can also be executed by pressing the power button 109 for 4 seconds or longer when the system 101 is operating normally. In that case, since the system 101 shuts down before completing the process for shifting to the S4 state or the S3 state in block 225, the data in the main memory is lost. Only the stored data is not lost by the procedure of block 232.

  When the power button 109 is not pressed in block 203, the EC 115 compares the detected temperature of each of the plurality of temperature sensors 111 with a reference value in block 205 and controls the rotational speed of the exhaust heat fan 113. If the temperature rises even when the rotational speed of the exhaust heat fan 113 is maximized, the EC 115 performs throttling control to lower the operating frequency of the CPU. If the temperature rises even after throttling control, the EC 115 requests the system 101 to shift to the S3 state. If the notebook PC 100 shifts to the S3 state, the temperature usually decreases. However, the notebook PC 100 may reach the limit temperature before the transition to the S3 state and the temperature decreases. At this time, the EC 115 generates a surprise shutdown event and moves to block 231.

  If a surprise shutdown event is not generated in block 205, the process moves to block 207. In block 207, the EC 115 monitors the voltage, current, temperature, and the like of the power source 117 and the DC / DC converter 117. The EC 115 generates a surprise shutdown event when an abnormality occurs in a predetermined monitoring item, and proceeds to block 231. If a surprise shutdown event is not generated in block 207, the process moves to block 209. In block 209, the hardware logic circuit 107 monitors the state of the system 101. When a hang-up that requires shutdown occurs in the system 101, the hardware logic circuit 107 generates a surprise shutdown event and moves to block 231, and returns to block 203 if it does not occur.

  In the procedure so far, there is a delay of about 10 milliseconds in the block 233 between the generation of the surprise shutdown event and the stop of the operation of the DC / DC converter 119 from the S0 system to the S4 system. This time delay may be undesirable when a surprise shutdown event is generated due to temperature or power failure. This time delay is for the HDD 121 to use for head / slider evacuation and cache flushing, and is not necessary for devices other than the HDD 121.

  When the DC / DC converter 119 supplies power to the HDD 121 through a dedicated system, when a surprise shutdown event occurs, only the system of the HDD 121 is processed through the paths of the blocks 231 to 235, and the other system. Immediately shutting down can reduce the possibility of failure due to the shutdown delay time. Note that this embodiment can also be applied to an SSD having a SATA interface instead of the HDD.

  According to the present embodiment, since the DEVSLP provided for the purpose of power saving can be used for protection of the auxiliary storage device against the surprise shutdown only by rewriting the firmware of the EC 115, there is an advantage that no additional cost is generated. is there. Further, the present invention can be extended to an auxiliary storage device other than SATA provided with an interface for recognizing the start of a preparatory operation for a power stop in addition to an interface for transferring data and commands.

  Although the present invention has been described with the specific embodiments shown in the drawings, the present invention is not limited to the embodiments shown in the drawings, and is known so far as long as the effects of the present invention are achieved. It goes without saying that any configuration can be adopted.

100 notebook PC
109 Power Button 111 Thermal Sensor 113 Exhaust Heat Fan 115 Embedded Controller 119 DC / DC Converter

Claims (18)

A method in which a host device stops the power of an auxiliary storage device including a first interface and a second interface,
The host device writing data to the auxiliary storage device through the first interface;
Generating an event for the host device to stop powering the auxiliary storage device;
Asserting the second interface by the host device in response to the event;
Performing a preparatory operation for the auxiliary storage device to stop power in response to the second interface being asserted;
And a method in which the host device stops the power of the auxiliary storage device when a predetermined time has elapsed since the second interface was asserted.   The method according to claim 1, wherein the preparing operation includes a power saving operation of the auxiliary storage device.   3. The method according to claim 1, wherein the auxiliary storage device is a hard disk drive, and the step of performing the preparing operation includes a step of retracting a head / slider.   The method according to claim 3, wherein the auxiliary storage device adopts a write-back method, and the step of performing the preparatory operation includes a step of writing data stored in a cache to a magnetic disk.   3. The method according to claim 1, wherein the auxiliary storage device is a solid state drive and the preparing operation includes writing data stored in a cache into a nonvolatile storage cell. A method of shutting down a computer to which an auxiliary storage device having a first interface and a second interface is connected, comprising:
Writing data to the auxiliary storage device via the first interface;
Generating a shutdown event in an environment that the system does not recognize;
The computer asserts the second interface in response to the shutdown event;
Performing a preparatory operation for the auxiliary storage device to stop power in response to the second interface being asserted;
Shutting down the computer when a predetermined time has elapsed since asserting the second interface.   The method according to claim 6, wherein the preparatory step includes writing data stored in a cache to a non-volatile storage medium.   The method according to claim 6 or 7, wherein the shutdown event is generated when a system cannot send a command indicating shutdown to the auxiliary storage device through the first interface.   The method of claim 8, wherein the shutdown event is generated when a power button is continuously pressed for a predetermined time or more.   The method according to claim 6, wherein the shutdown event is generated by a device operating in an environment that is not recognized by the central processing unit of the computer.   The method of claim 10, wherein the shutdown event is generated when a device temperature indicates anomalies.   The method of claim 10, wherein the shutdown event is generated when a device supplying power to the computer indicates an abnormality.   The method of claim 10, wherein the shutdown event is generated when a system hangs up. A computer capable of shutting down by a system including a processor executing a predetermined sequence;
A control circuit capable of operating independently of the system and generating a shutdown event;
A first interface for receiving a command from the system and a second interface for receiving a signal indicating to stop at least part of power from the control circuit, and receiving a signal indicating to stop the power An auxiliary storage device capable of performing a preparatory operation for stopping power,
The control circuit outputs a signal indicating that the power is stopped to the second interface when the shutdown event is generated, and outputs a signal indicating that the power is stopped for a predetermined time. A computer that shuts down the computer when it has elapsed.   The control circuit stops the power of the auxiliary storage device when a predetermined time has elapsed since outputting a signal indicating that the power is stopped, and shuts down when the shutdown event is generated. The computer according to claim 14, wherein power of devices other than the auxiliary storage device whose power is stopped is stopped.   The computer according to claim 14 or 15, wherein the computer shifts to a power saving mode when receiving a signal indicating that the auxiliary storage device stops the power.   The signal indicating that the auxiliary storage device conforms to the SATA standard and the power is stopped is a DEVSLP signal for causing the auxiliary storage device to shift to a power saving mode. The listed computer. A host device capable of stopping the power of the auxiliary storage device,
A processor;
A control circuit capable of operating independently of the processor and outputting a signal indicating that power of at least a part of the auxiliary storage device is stopped, and a first interface for transferring data between the processor And a second interface for receiving a signal indicating that the power is to be stopped from the control circuit, a cache, and a non-volatile storage medium, and the cache stores the signal indicating that the power is to be stopped. An auxiliary storage device capable of recording data to be stored in the nonvolatile storage medium,
A host device that stops the power of the auxiliary storage device when a predetermined time has elapsed after the control circuit outputs a signal indicating that the power is stopped to the second interface.

Images