JP2013247419A - Amplifier, transmitter/receiver and communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplifier that can match a circuit impedance to signals in opposite directions in a simple circuit.SOLUTION: The amplifier comprises: a plurality of first transistors arranged in series between a first terminal and a second terminal and grounded at gates; a first inductor connected between the first terminal and a second transistor, which is one of the plurality of first transistors arranged at one end; a first switch connected between the first terminal and the second transistor so as to short during a first mode of outputting a signal received at the first terminal to the second terminal and open during a second mode of outputting a signal received at the second terminal to the first terminal; a second inductor connected between the second terminal and a third transistor, which is one of the plurality of first transistors arranged at the other end; and a second switch connected between the second terminal and the third transistor so as to open during the first mode and short during the second mode.

Description

  The present invention relates to an amplifier, a transceiver having an amplifier, and a communication apparatus.

  The field effect transistor has a symmetrical structure, and the symmetry can be utilized by grounding the gate. For example, a gate-grounded transistor is used in an amplifier such as a wireless communication device that transmits and receives high-frequency signals. This type of amplifier includes a plurality of common-gate transistors connected in series between an input terminal and an output terminal (see, for example, Patent Document 1). Further, this type of amplifier has a plurality of grounded gate transistors connected in series between a pair of input / output terminals, and a matching circuit including a diode connected to each input / output terminal. (For example, refer to Patent Document 2).

JP 2011-82617 A JP-T 9-505450

  In general, an amplifier that transmits a signal in a single direction does not operate as a bidirectional amplifier because the impedance of the circuit is not correctly matched when a signal in the reverse direction is transmitted. For this reason, a transceiver for receiving and transmitting a signal is realized using two amplifiers. Further, the conventional bidirectional amplifier uses a matching circuit including a diode, for example, to match the impedance of the circuit with respect to the bidirectional signal, and the circuit is complicated.

  In one aspect, an object of the present invention is to realize an amplifier capable of matching the impedance of a circuit with respect to a bidirectional signal by a simple circuit.

  In one embodiment of the present invention, the amplifier is arranged in series between the first terminal and the second terminal, and has a plurality of gate-grounded first transistors, a first terminal, and one end of the plurality of first transistors. A first inductor connected between the second transistor disposed on the side and a first terminal connected between the first terminal and the second transistor and outputting a signal received at the first terminal to the second terminal; The first switch that is short-circuited during the mode and that is output during the second mode that outputs the signal received at the second terminal to the first terminal, the second terminal, and the plurality of first transistors are arranged on the other end side. A second inductor connected between the third transistor and a second switch connected between the second terminal and the third transistor, open during the first mode and short-circuited during the second mode And.

  By short-circuiting one of the first switch and the second switch, it becomes possible to hide the impedance of the inductor connected in parallel to the switch from the terminal to which a signal is input, and the first switch and the second switch are opened. An amplifier capable of receiving signals from both directions can be realized by a short circuit.

2 illustrates an example of an amplifier in one embodiment. 3 shows an example of an amplifier in another embodiment. 3 illustrates an example of a voltage generation circuit that generates a bias voltage supplied to the amplifier illustrated in FIG. 2. 3 shows an example of an amplifier in another embodiment. 5 illustrates an example of a voltage generation circuit that generates a bias voltage supplied to the amplifier illustrated in FIG. 4. 5 shows an example of a bias voltage supplied to the amplifier shown in FIG. An example of the layout of the matching circuits IM3 and IM4 shown in FIG. 4 is shown. An example of the layout of the matching circuits IM1 and IM2 shown in FIG. 4 is shown. 5 shows an example of the operation of the amplifier shown in FIG. 4 in the first mode. 5 shows an example of the operation of the amplifier shown in FIG. 4 in the second mode. An example of another amplifier is shown. 12 shows an example of operation of the amplifier shown in FIG. 11 in the first mode. 12 shows an example of operation of the amplifier shown in FIG. 11 in the second mode. 5 shows an embodiment of a transceiver and a communication device including the amplifier shown in FIGS. 1, 2, and 4. 4 shows another example of a communication device. 3 shows another example of a voltage generation circuit that generates a bias voltage supplied to the amplifier shown in FIG. An example of the operation of the voltage generation circuit shown in FIG. 16 is shown.

  Hereinafter, embodiments will be described with reference to the drawings. A signal line through which a signal or voltage is transmitted uses the same symbol as the signal name or voltage name.

  For high frequency applications, an amplifier that amplifies the signal is essential. Usually, the signal amplified by the amplifier is determined in a single direction. However, if a bi-directional amplifier that can switch the direction of signal amplification while using the same circuit is used, the device can be simplified and miniaturized, and loss at the carrier frequency can be reduced. (I.e., improved transmission power, reduced received signal noise).

  FIG. 1 shows an example of an amplifier AMP1 in one embodiment. For example, the amplifier AMP1 is made on a semiconductor substrate using semiconductor manufacturing technology. The amplifier AMP1 includes a matching circuit IM1, a transistor T1, a matching circuit IM3, a transistor T2, and a matching circuit IM2 connected in series between the input / output ports P1 and P2. For example, the input / output ports P1 and P2 are terminals of the amplifier AMP1. Matching circuit IM1 and transistor T1 are connected to each other via node ND1. Matching circuit IM2 and transistor T2 are connected to each other via node ND2.

  The matching circuit IM1 includes an inductor L1 and a switch S1 connected in parallel between the input / output port P1 and the node ND1. The matching circuit IM2 includes an inductor L2 and a switch S2 connected in parallel between the input / output port P2 and the node ND2. The matching circuit IM3 has an inductor L3 connected between the transistors T1 and T2. Note that the matching circuit IM3 may have a wiring resistance or a wiring load capacitance connecting the transistors T1 and T2 to each other instead of the inductor L3.

  For example, each of the switches S1 and S2 includes a field effect transistor such as a high electron mobility transistor (HEMT). In this case, the transistor operating as the switch S1 has one of the source and the drain connected to the input / output port P1, the other of the source and the drain connected to the node ND1, and a control signal for controlling the short circuit or opening of the switch S1 is gated. Receive at. The transistor operating as the switch S2 has one of the source and the drain connected to the node ND2, the other of the source and the drain connected to the input / output port P2, and receives a control signal at the gate for controlling a short circuit or opening of the switch S2.

  A field effect transistor has a large ratio of resistance between a source and a drain in an on state and a resistance between a source and a drain in an off state. In the on state and the off state, a binary signal is sent from the logic circuit to the gate of the transistor It can be controlled by outputting. Therefore, the operations of the switches S1 and S2 can be easily controlled, and the amplifier AMP1 can be operated as a bidirectional amplifier as will be described later.

  The switches S1 and S2 may include InP-based or GaAs-based HEMTs and may include MOS (Metal Oxide Semiconductor) transistors. The switches S1 and S2 may include a CMOS transmission gate in which the source and drain of an n-type channel type transistor are connected to the source and drain of a p-type channel type transistor, respectively. Furthermore, the switches S1 and S2 may include a diode switch or an RF-MEMS (Radio Frequency-Micro Electro Mechanical System) switch.

  The gate of the transistor T1 is connected to the ground line VSS via a capacitor C1 that cuts an AC component. The gate of the transistor T2 is connected to the ground line VSS via a capacitor C2 that cuts an AC component. That is, the amplifier AMP1 includes transistors T1 and T2 that are grounded. A node ND3 connecting the gate of the transistor T1 and the capacitor C1 receives the bias voltage VG1 when the amplifier AMP1 operates. A node ND4 connecting the gate of the transistor T2 and the capacitor C2 receives the bias voltage VG2 when the amplifier AMP1 operates.

  For example, the bias voltages VG1 and VG2 are generated by a voltage generation circuit provided outside the amplifier AMP1. The operations of the switches S1 and S2 are controlled by a control circuit provided outside the amplifier AMP1. The control circuit outputs a switch control signal (DC bias) for short-circuiting or opening the switches S1 and S2 to the switches S1 and S2. Note that the voltage generation circuit and the control circuit may be provided in the amplifier AMP1.

  The amplifier AMP1 amplifies the signal received at the input / output port P1, and receives the bias voltage VG1 at the node ND3 during the first mode in which the amplified signal is output from the input / output port P2, and is higher than the bias voltage VG1 at the node ND4. A high bias voltage VG2 is received.

  In the first mode, the amplifier AMP1 receives the switch control signal, shorts the switch S1 as shown in FIG. 1, and connects the input / output port P1 and the node ND1. As a result, the impedance of the inductor L1 becomes invisible from the input / output port P1 side, and the impedance of the transistor T1 becomes visible from the input / output port P1 side. The impedance of the transistor T1 is set according to the input impedance of the input / output port P1 by adjusting the gate size of the transistor T1.

  Further, the amplifier AMP1 receives the switch control signal during the first mode, opens the switch S2 as shown in FIG. 1, and cuts off the connection between the input / output port P2 and the node ND2 by the switch S2. As a result, the impedance of the inductor L2 becomes visible from the input / output port P2 side. As described above, the switches S1 and S2 illustrated in FIG. 1 indicate the state in the first mode.

The matching circuit IM2 functions as a parallel LC circuit in which the inductor L2 and the parasitic capacitance due to the opened switch S2 are connected in parallel. For this reason, the impedance Z of the matching circuit IM2 is expressed by Expression (1). Here, symbol j is the angular frequency of the signal received at the input / output port P1, symbol ω is the frequency of the signal received at the input / output port P1, symbol L is the inductance of the inductor L2, and symbol Csw is when the switch S2 is open. Of parasitic capacitance.
Z = j · ω · L / (1-ω ² · L · Csw) (1)
Further, the voltage gain of the amplifier AMP1 in the first mode is expressed by Expression (2). Here, the symbol Cgd indicates the capacitance between the gate and drain of each of the transistors T1 and T2, and the symbol L is the inductance of the inductor L2. When the voltage gain becomes infinite, the amplifier AMP1 oscillates. In order to prevent the voltage gain from becoming infinite, the inductance L is set to a value smaller than 1 / ω ² · (Csw + Cgd).
Voltage gain = 1 / (1-ω ² · (Csw + Cgd) · L) (2)
When the matching circuit IM2 does not include the switch S2 and includes only the inductor, the impedance Z0 of the matching circuit IM2 is expressed by Expression (3), where the inductance of the inductor is L0.
Z0 = j · ω · L0 (3)
When the impedances Z0 and Z are equal to each other, the right side of the equation (1) and the right side of the equation (3) are equal to each other. Therefore, the inductance L of the inductor L2 is expressed by the equation (4).
L = L0 / (1 + ω ² · L0 · Csw) (4)
Since “ω ² · L0 · Csw” in the equation (4) is a positive value, the inductance L of the inductor L2 can be made smaller than the inductance L0. That is, by including the switch S2 in the matching circuit IM2 shown in FIG. 1, the inductance L of the inductor L2 can be made smaller than the inductance L0 of the inductor of the matching circuit that does not include the switch S2.

  On the other hand, the amplifier AMP1 amplifies the signal received at the input / output port P2, and receives the bias voltage VG2 at the node ND4 and the bias voltage VG2 at the node ND3 during the second mode in which the amplified signal is output from the input / output port P1. Higher bias voltage VG1.

  In the second mode, the amplifier AMP1 receives the switch control signal, shorts the switch S2, and connects the input / output port P2 and the node ND2. As a result, the impedance of the inductor L2 becomes invisible from the input / output port P2 side, and the impedance of the transistor T2 becomes visible from the input / output port P2 side. The impedance of the transistor T2 is set according to the input impedance of the input / output port P2 by adjusting the gate size of the transistor T2.

  The amplifier AMP1 receives the switch control signal during the second mode, opens the switch S1, and cuts off the connection between the input / output port P1 and the node ND1 by the switch S1. Thereby, the impedance of the inductor L1 becomes visible from the input / output port P1 side.

  The matching circuit IM1 functions as a parallel LC circuit in which the inductor L1 and the parasitic capacitance due to the opened switch S1 are connected in parallel. Therefore, the impedance Z of the matching circuit IM1 is expressed by the above equation (1). The operation of the matching circuit IM2 in the second mode is the same as the operation of the matching circuit IM1 in the first mode, and the operation of the matching circuit IM1 in the second mode is the same as the operation of the matching circuit IM2 in the first mode. It is the same. Therefore, the voltage gain of the amplifier AMP1 in the second mode is expressed by Expression (2), as in the first mode. That is, the amplifier AMP1 can switch the direction of amplification by switching the switches S1 and S2.

  The amplifier AMP1 has a symmetric structure except for the short-circuit and open states of the switches S1 and S2 in the first mode and the second mode. For this reason, said Formula (4) is materialized also in 2nd mode. In this case, the symbol L in Expression (4) indicates the inductance of the inductor L1 of the matching circuit IM1. Therefore, also in the second mode, the inductance L of the inductor L1 can be made smaller than the inductance L0 of the inductor of the matching circuit IM1 when the switch S1 is not included.

  In general, the layout area of an inductor mounted on a semiconductor integrated circuit is larger than the layout area of other elements as shown in FIG. For this reason, the layout size of the amplifier AMP1 can be reduced by reducing the inductance L of the inductors L1 and L2. As will be described later, the layout size of each inductor L1, L2 (FIG. 8) can be about 57% of the inductor layout size (FIG. 7) of each matching circuit IM1, IM2 when each switch S1, S2 is not included. . In other words, the addition of the switches S1 and S2 does not increase the circuit scale of the matching circuits IM1 and IM2.

  As described above, in this embodiment, the impedance of the inductor L1 connected in parallel to the switch S1 can be made invisible from the input / output port P1 to which a signal is input by short-circuiting the switch S1, and matching is achieved by the impedance of the transistor T1. Can do. Similarly, due to the short circuit of the switch S2, the impedance of the inductor L2 connected in parallel to the switch S2 can be made invisible from the input / output port P2 to which a signal is input, and matching can be achieved by the impedance of the transistor T2.

  Further, by opening the switch S2 during the first mode, impedance matching can be achieved by the LC circuit including the inductor L2 and the parasitic capacitance of the switch S2. Similarly, when the switch S1 is opened during the second mode, impedance matching can be achieved by the LC circuit including the inductor L1 and the parasitic capacitance of the switch S1.

  For this reason, the impedance of the circuit can be matched to a bidirectional signal with a simple circuit. That is, by switching between the short-circuit and open-circuit of the switches S1 and S2, the input impedance and output impedance of the amplifier AMP1 can be matched, and good signal characteristics can be obtained over a wide frequency band. In other words, the amplifier AMP1 can amplify the signal in both the first mode for receiving a signal from the input / output port P1 and the second mode for receiving a signal from the input / output port P2.

  In addition, the matching circuits IM1 and IM2 including the switches S1 and S2 include inductors, and the sizes of the inductors L1 and L2 can be reduced as compared with the matching circuit including no switches. Therefore, the circuit scale of the amplifier AMP1 can be reduced as compared with an amplifier including a conventional matching circuit that does not include a switch.

  FIG. 2 shows an example of an amplifier AMP2 in another embodiment. Elements that are the same as or the same as those in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted.

  For example, the amplifier AMP2 is made on a semiconductor substrate using semiconductor manufacturing technology. The amplifier AMP2 has a capacitor C5 between the input / output port P1 and the matching circuit IM1, and has a capacitor C6 between the input / output port P2 and the matching circuit IM2. The amplifier AMP2 includes an inductor L5 connected between the node ND5 that connects the capacitor C5 to the matching circuit IM1 and the terminal V1. The amplifier AMP2 has an inductor L6 connected between a node ND6 connecting the capacitor C6 to the matching circuit IM2 and the terminal V2. Terminals V1 and V2 are examples of voltage terminals that receive a bias voltage.

  The other configuration of the amplifier AMP2 is the same as that of the amplifier AMP1 shown in FIG. That is, the amplifier AMP2 includes a matching circuit IM1, a transistor T1, a matching circuit IM3, a transistor T2, a matching circuit IM2, and capacitors C1 and C2 having the same connection relationship as that in FIG.

  Capacitor C5 cuts the DC component of the signal received at input / output port P1. Inductor L5 cuts the AC component received at terminal V1. Capacitor C6 cuts the DC component of the signal received at input / output port P2. Inductor L6 cuts the AC component received at terminal V2. The operation of the amplifier AMP2 will be described with reference to FIG.

  FIG. 3 shows an example of the voltage generation circuit VGEN that generates the bias voltages VG1 and VG2 supplied to the amplifier AMP2 shown in FIG. The voltage generation circuit VGEN may be provided outside the amplifier AMP2, or may be provided in the amplifier AMP2. The bias voltages V1 and V2 are generated from outside the voltage generation circuit VGEN, and are used to generate the bias voltages VG1 and VG2.

  The voltage generation circuit VGEN includes a resistor R1 and a diode D1 connected in series between the terminals V1 and VG1, and a diode D2 and a resistor R2 connected in series between the terminals V1 and VG1. The voltage generation circuit VGEN includes a resistor R3 connected between the terminals VG1 and VG2. Further, the voltage generation circuit VGEN includes a resistor R4 and a diode D4 connected in series between the terminals VG2 and V2, and a diode D5 and a resistor R5 connected in series between the terminals VG2 and V2. The anode of the diode D1 is connected to the terminal VG1, and the anode of the diode D2 is connected to the terminal V1. The anode of the diode D4 is connected to the terminal V2, and the anode of the diode D5 is connected to the terminal VG2.

  During the first mode in which the bias voltage V2 is set higher than the bias voltage V1, forward current flows from the anode to the cathode of the diodes D4 and D1, respectively, and the bias voltages VG1 and VG2 have the resistance ratio of the resistors R1, R3, and R4. The value is set accordingly. That is, the relationship between the bias voltages V1, VG1, VG2, and V2 is “V1 <VG1 <VG2 <V2”. In the first mode, no current flows through the diodes D2 and D5 to which reverse bias is applied. When a bias voltage is supplied to the terminals V1, V2, VG1, and VG2 of the amplifier AMP2 illustrated in FIG. 2, drain currents flow through the transistors T1 and T2 from the terminal V2 toward the terminal V1. The signal supplied to the input / output port P1 is sequentially amplified by the transistors T1 and T2 and output from the input / output port P2.

  On the other hand, in the second mode in which the bias voltage V1 is set higher than the bias voltage V2, forward currents flow from the anodes to the cathodes of the diodes D2 and D5, respectively. The bias voltages VG1 and VG2 are the resistances of the resistors R2, R3, and R5. The value is set according to the ratio. That is, the relationship between the bias voltages V1, VG1, VG2, and V2 is “V1> VG1> VG2> V2.” In the second mode, no current flows through the diodes D1 and D4 that are reversely biased. By supplying a bias voltage to the terminals V1, V2, VG1, and VG2 of the amplifier AMP2 illustrated in FIG. 2, drain currents flow from the terminal V1 to the terminal V2 through the transistors T1 and T2. The signal supplied to the input / output port P2 is sequentially amplified by the transistors T2 and T1 and output from the input / output port P1.

  As described above, also in this embodiment, as in the embodiment shown in FIG. 1, a bidirectional amplifier can be realized by switching between short-circuiting and opening of the switches S1 and S2. In addition, the sizes of the inductors L1 and L2 can be reduced as compared with the conventional case, and the circuit scale of the amplifier AMP2 can be reduced as compared with the conventional case.

  Further, a bias voltage is applied to the node ND5 on the input / output port P1 side, the node ND6 on the input / output port P2 side, and the gates of the transistors T1 and T2 according to the first mode and the second mode, thereby supplying the amplifier AMP2. Can be sequentially amplified by the transistors T1 and T2.

  FIG. 4 shows an example of an amplifier AMP3 in another embodiment. Elements that are the same as or the same as those in FIGS. 1 and 2 are given the same reference numerals, and detailed descriptions thereof are omitted.

  For example, the amplifier AMP3 is made on a semiconductor substrate using semiconductor manufacturing technology. In the amplifier AMP3, a matching circuit IM4 and a transistor T3 are added between the transistor T2 and the matching circuit IM2 of the amplifier circuit AMP2 illustrated in FIG. The other configuration of the amplifier AMP3 is the same as that of the amplifier AMP2 shown in FIG.

  The matching circuit IM4 has an inductor L4 connected between the transistors T2 and T3. The gate of the transistor T3 is connected to the ground line VSS via a capacitor C3 that cuts an AC component. A node ND7 that connects the gate of the transistor T3 and the capacitor C3 receives the bias voltage VG1 when the amplifier AMP3 operates.

  For example, the bias voltages VG1, VG2, and VG3 are generated by a voltage generation circuit provided outside the amplifier AMP3. The operations of the switches S1 and S2 are controlled by a control circuit provided outside the amplifier AMP3. Note that the voltage generation circuit and the control circuit may be provided in the amplifier AMP3.

  FIG. 5 shows an example of a voltage generation circuit VGEN that generates the bias voltages VG1, VG2, and VG3 supplied to the amplifier AMP3 shown in FIG. Elements that are the same as or the same as those of the voltage generation circuit VGEN illustrated in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted. The voltage generation circuit VGEN may be provided outside the amplifier AMP3 or may be provided in the amplifier AMP3. The bias voltages V1 and V2 are generated from the outside of the voltage generation circuit VGEN. The bias voltages VG1 and VG2 and the bias voltages V1 and V2 are generated from the outside of the voltage generation circuit VGEN to generate the bias voltages VG1, VG2, and VG3. Used for. Used to generate

  The voltage generation circuit VGEN includes a resistor R6 between the resistors R3 and R4 illustrated in FIG. The connection node of the resistors R6 and R4 is connected to the terminal VG3. The other configuration of the voltage generation circuit VGEN is the same as that in FIG. For example, the ratio of the resistors R1, R2, R3, R4, R5, R6 is set to 1: 9: 10: 9: 1: 10. Thereby, during the first mode in which the bias voltage V2 is set higher than the bias voltage V1, the voltage corresponding to the resistance ratio 1: 10: 10: 9 of the resistors R1, R3, R6, R4 is changed to the terminals VG1, VG2, VG3. Is generated. During the second mode in which the bias voltage V1 is set higher than the bias voltage V2, a voltage corresponding to the resistance ratio 1: 10: 10: 9 of the resistors R2, R3, R6, and R5 is generated at the terminals VG3, VG2, and VG1. The

  FIG. 6 shows an example of the bias voltages V1, V2, VG1, VG2, and VG3 supplied to the amplifier AMP3 shown in FIG. During the first mode in which the signal received at the input / output port P1 is amplified and the amplified signal is output from the input / output port P2, the switch S1 is short-circuited (ON) and the switch S2 is opened (OFF). In the first mode, the terminal V1 is set to the ground voltage VSS, the VG1 terminal is set to the ground voltage VSS or higher, the terminal VG2 is set to the bias voltage VO1, the terminal VG3 is set to the bias voltage VO2, and the terminal V2 is biased. The voltage is set to VO3. For example, the bias voltage VO1 is higher than the bias voltage VG1, the bias voltage VO2 is higher than the bias voltage VO1, and the bias voltage VO3 is higher than the bias voltage VO2.

  During the second mode in which the signal received at the input / output port P2 is amplified and the amplified signal is output from the input / output port P1, the switch S1 is opened (OFF) and the switch S2 is short-circuited (ON). In the second mode, the terminal V2 is set to the ground voltage VSS, VG3 is set to the ground voltage VSS or higher, the terminal VG2 is set to the bias voltage VO1, the terminal VG1 is set to the bias voltage VO2, and the terminal V1 is set to the bias voltage. Set to VO3. For example, the bias voltage VO1 is higher than the bias voltage VG3, the bias voltage VO2 is higher than the bias voltage VO1, and the bias voltage VO3 is higher than the bias voltage VO2.

  FIG. 7 shows an example of the layout of the matching circuits IM3 and IM4 shown in FIG. In FIG. 7, the broken line pattern indicates the metal wirings M11 and M12, and the solid line pattern indicated by shading indicates the metal wiring M21. The metal wirings M11 and M12 are wired using the first metal wiring layer, and the metal wirings M21 and M22 are wired using the second metal wiring layer. For example, the first metal wiring layer is located closer to the semiconductor substrate than the second metal wiring layer. In FIG. 7, rectangles marked with X indicate contacts that connect the first metal wiring layer and the second metal wiring layer.

  For example, in the matching circuit IM3, the metal wiring M11 is connected to the transistor T1, the metal wiring M22 is connected to the transistor T2, and the metal wiring M21 functions as the inductor L3. For example, the inductance of the inductor L3 is 160 pH. Similarly, in the matching circuit IM4, the metal wiring M11 is connected to the transistor T2, the metal wiring M12 is connected to the transistor T3, and the metal wiring M21 functions as the inductor L4.

  When the length of one unit is “L”, the layout sizes of the inductors L3 and L4 of the matching circuits IM3 and IM4 are, for example, a width of 7L and a height of 5L. Note that the layout shown in FIG. 7 may be used for matching circuit IM3 shown in FIGS. 7 shows a layout of the inductor included in the matching circuit IM1 when the matching circuit IM1 does not include the switch S1, and FIG. 7 shows the layout of the inductor included in the matching circuit IM2 when the matching circuit IM2 does not include the switch S2. The layout is shown.

  FIG. 8 shows an example of the layout of the matching circuits IM1 and IM2 shown in FIG. As in FIG. 7, the broken line pattern indicates the metal wirings M13, M14, M15, and M16, the solid line pattern indicated by shading indicates the metal wirings M23 and M24, and the rectangle marked with X is the first metal wiring. The contact which connects a layer and a 2nd metal wiring layer is shown. The metal wirings M13, M14, M15, and M16 are wired using the first metal wiring layer, and the metal wirings M23 and M24 are wired using the second metal wiring layer.

  In FIG. 8, a rectangle marked with a broken line X indicates a contact connecting the semiconductor substrate and the first metal wiring layer, or a contact connecting the semiconductor substrate and the second metal wiring layer. The hatched pattern indicates the gate wiring GT, and the alternate long and short dash line pattern indicates the source and drain of the transistor TR. The gate wiring GT is connected to the metal wiring M14 through a contact. For example, the transistor TR is an InP-based n-type channel type HEMT that operates as the switch S1 or S2 shown in FIG.

  For example, in the matching circuit IM1, the metal wiring M13 is connected to the node ND5, the metal wiring M24 is connected to the node ND1, and the metal wiring M23 functions as the inductor L1. For example, the inductance of the inductor L1 is 70 pH, which is less than half of the inductance of the inductor L3 shown in FIG.

  The transistor TR of the matching circuit IM1 receives a high level at the gate GT during the first mode, and short-circuits between the source and the drain. As a result, the impedance of the inductor L1 becomes invisible from the input / output port P1 side. The transistor TR of the matching circuit IM1 receives the low level at the gate GT during the second mode and cuts off the connection between the source and the drain. As a result, the impedance of the inductor L1 becomes visible from the input / output port P1 side. The transistor TR of the matching circuit IM1 functions as a capacitor while the low level is supplied to the gate GT, and the matching circuit IM1 functions as a parallel LC circuit.

  Similarly, in the matching circuit IM2, the metal wiring M13 is connected to the node ND6, the metal wiring M24 is connected to the node ND2, and the metal wiring M23 functions as the inductor L2. For example, the inductance of the inductor L2 is 70 pH, which is less than half the inductance of the inductor L3 shown in FIG.

  The transistor TR of the matching circuit IM2 receives a high level at the gate GT during the second mode and shorts between the source and the drain. As a result, the impedance of the inductor L2 becomes invisible from the input / output port P2 side. The transistor TR of the matching circuit IM2 receives the low level at the gate GT during the first mode, and cuts off the connection between the source and the drain. As a result, the impedance of the inductor L2 becomes visible from the input / output port P2 side. The transistor TR of the matching circuit IM2 functions as a capacitor while the low level is supplied to the gate GT, and the matching circuit IM2 functions as a parallel LC circuit.

  For example, the parasitic capacitance when the transistor TR is cut off is 10 fF. The layout shown in FIG. 8 may be used for matching circuits IM1 and IM2 shown in FIGS.

  The size of each inductor L1 and L2 can be reduced by making the inductor L1 or L2 invisible and including the transistor TR functioning as a capacitor in each matching circuit IM1 and IM2. For example, when the length of one unit is “L”, the layout sizes of the matching circuits IM1 and IM2 are 4L in width and 5L in height. As described above, FIG. 7 shows the layout of the inductor included in the matching circuit IM1 when the matching circuit IM1 does not include the switch S1, and is included in the matching circuit IM2 when the matching circuit IM2 does not include the switch S2. Shows the inductor layout. Therefore, the layout size of each matching circuit IM1 and IM2 can be about 57% of the layout size when the switches S1 and S2 are not included.

  FIG. 9 shows an example of the operation in the first mode of the amplifier AMP3 shown in FIG. FIG. 9 shows the S parameter obtained by the circuit simulation, the vertical axis shows the gain, and the horizontal axis shows the frequency of the signal received by the amplifier AMP3. In the first mode, the amplifier AMP3 amplifies the signal received at the input / output port P1, and outputs the amplified signal from the input / output port P2.

  The parameter S (2, 1) indicates the characteristic (that is, gain) of the signal that passes through the input / output port P2 when the signal is input from the input / output port P1. The parameter S (1, 1) indicates the characteristic of the signal reflected to the input / output port P1 when the signal is input from the input / output port P1 (that is, the input reflection characteristic). The parameter S (2, 2) indicates the characteristic of the signal reflected to the input / output port P2 when the signal is input from the input / output port P2 (that is, the output reflection characteristic).

  For example, when the frequency band 3 dB lower than the maximum gain is used as the operation region of the amplifier AMP3, a sufficient gain can be obtained for a signal of approximately 100 GHz to 155 GHz. The reflection characteristics in the operating region are lower than -5 dB and are good.

  FIG. 10 shows an example of the operation in the second mode of the amplifier AMP3 shown in FIG. Detailed description of elements similar to those in FIG. 9 is omitted. FIG. 10 shows S parameters obtained by circuit simulation, as in FIG. In the second mode, the amplifier AMP3 amplifies the signal received at the input / output port P2, and outputs the amplified signal from the input / output port P1.

  The parameter S (2, 1) indicates the characteristic (that is, gain) of the signal that passes through the input / output port P1 when the signal is input from the input / output port P2. The parameter S (1, 1) indicates the characteristic of the signal reflected to the input / output port P2 when the signal is input from the input / output port P2 (that is, the input reflection characteristic). The parameter S (2, 2) indicates the characteristic of the signal reflected to the input / output port P1 when the signal is input from the input / output port P1 (that is, the output reflection characteristic).

  For example, when the frequency band 3 dB lower than the maximum gain is used as the operating region of the amplifier AMP3, a sufficient gain can be obtained for a signal of approximately 95 GHz to 150 GHz, and the reflection characteristics are also good.

  FIG. 11 shows an example of another amplifier. The amplifier AMP4 deletes the matching circuit IM1 from the amplifier AMP2 shown in FIG. 4, and has a matching circuit IM5 instead of the matching circuit IM2 shown in FIG. That is, the amplifier AMP4 has an input / output port P1 connected to the transistor T1 via the capacitor C3. The matching circuit IM5 has an inductor L5 connected between the transistor T3 and the capacitor C4. The other configuration of the amplifier AMP4 is the same as that of the amplifier AMP3 shown in FIG.

  FIG. 12 shows an example of the operation in the first mode of the amplifier AMP4 shown in FIG. Detailed description of elements similar to those in FIG. 9 is omitted. FIG. 12 shows S parameters obtained by circuit simulation. The meanings of the parameter S (2, 1), the parameter S (1, 1), and the parameter S (2, 2) are the same as those in FIG.

  In FIG. 12, when the frequency band 3 dB lower than the maximum gain is used as the operation region of the amplifier AMP4, a sufficient gain can be obtained for a signal of approximately 105 GHz to 155 GHz, and the reflection characteristics are also good.

  FIG. 13 shows an example of the operation in the second mode of the amplifier AMP4 shown in FIG. Detailed description of the same elements as those in FIG. 10 is omitted. FIG. 13 shows S parameters obtained by circuit simulation. The meanings of the parameter S (2, 1), the parameter S (1, 1), and the parameter S (2, 2) are the same as those in FIG.

  In FIG. 13, the maximum gain is about 13 dB, which is about 8 dB lower than the first mode shown in FIG. Further, the maximum gain is lower than the maximum gain of the amplifier AMP3 shown in FIGS. Further, in the frequency band 3 dB lower than the maximum gain (approximately 95 GHz to 150 GHz), the parameters S (1,1) and S (2,2) are both higher than −3 dB and the reflection characteristics are poor.

  As described above, also in this embodiment, as in the embodiment shown in FIGS. 1 to 4, a bidirectional amplifier can be realized by switching between the short-circuit and the open-circuit of the switches S <b> 1 and S <b> 2. Further, the sizes of the inductors L1 and L2 can be reduced to about 57% of the conventional size, and the circuit scale of the amplifier AMP2 can be reduced as compared with the conventional size. Also, by applying a bias voltage to the node ND5 on the input / output port P1 side, the node ND6 on the input / output port P2 side, and the gates of the transistors T1, T2, and T3 according to the first mode and the second mode, the amplifier AMP3 Can be sequentially amplified by the transistors T1 and T2.

  In FIG. 4, the amplifier AMP3 includes three gate-grounded transistors T1, T2, and T3. However, the amplifier AMP3 may include four or more gate-grounded transistors. Also in this case, the matching circuit IM1 (or IM2) including the switch S1 (or S2) may be disposed in the input / output port P1 and the input / output port P2. Further, a bias voltage is applied to the terminal V1 connected to the input / output port P1 and a terminal V2 connected to the input / output port P2, and bias voltages having different values are sequentially applied to the gates of the transistors, so that the bias voltage is set. Accordingly, the operation in the first mode or the second mode described above can be realized.

  FIG. 14 shows an embodiment of the transceiver TRSV and the communication device CD including the amplifiers AMP1, AMP2, and AMP3 shown in FIGS. For example, the communication device CD is a wireless communication device such as a mobile phone, a wireless local area network (LAN), or a radar.

  The transceiver TRSV has amplifiers AMPa and AMPb, a mixer MIX, a local oscillator LO, and a switch circuit SW1. Each amplifier AMPa, AMPb is one of the amplifiers AMP1, AMP2 or AMP3 shown in FIGS. The communication device CD includes a transceiver TRSV, a voltage generation circuit VGEN, a control circuit CTRL, a reception circuit RSV, a transmission circuit TRS, and an antenna ANT.

  For example, the transceiver TRSV is included in one function macro or one semiconductor integrated circuit chip. Alternatively, the transceiver TRSV, the voltage generation circuit VGEN, the control circuit CTRL, the reception circuit RSV, and the transmission circuit TRS may be included in one semiconductor integrated circuit chip LSI. The communication device CD may have a plurality of semiconductor integrated circuit chips mounted on the substrate. In this case, the transceiver TRSV, the voltage generation circuit VGEN, the control circuit CTRL, the reception circuit RSV, and the transmission circuit TRS may be included in any of a plurality of semiconductor integrated circuit chips.

  In the transceiver TRSV, the amplifier AMPa, the mixer MIX, and the amplifier AMPb are connected in series between the antenna ANT and the switch circuit SW1, and the local oscillator LO is connected to the mixer MIX.

  For example, the matching circuits IM1, IM2 (FIG. 1, FIG. 2 or FIG. 4) of the amplifier AMPa are manufactured using the layout shown in FIG. 8, and the matching circuits IM3, IM4 (FIG. 1, FIG. 2, or FIG. 4) is manufactured using the layout shown in FIG. Therefore, the S parameter characteristics of the amplifier AMPa are the same as those in FIGS.

  The amplifier AMPa amplifies a high frequency signal from the antenna ANT and outputs the amplified signal to the mixer MIX during the reception mode in which the signal received by the antenna ANT is output to the reception circuit RSV. The amplifier AMPa amplifies the high-frequency signal from the mixer MIX and outputs it to the antenna ANT during the transmission mode in which the signal output from the transmission circuit TRS is output to the antenna ANT.

  During the reception mode, the mixer MIX mixes a high-frequency signal RF (Radio Frequency) received from the amplifier AMPa with a clock generated by the local oscillator LO to generate a low-frequency signal IF (Intermediate Frequency) (down-conversion). . In addition, the mixer MIX mixes the signal IF received from the amplifier AMPb with the clock generated by the local oscillator LO during the transmission mode, and generates the signal RF (up-conversion). Thus, the mixer MIX is a bidirectional mixer.

  For example, the matching circuits IM3 and IM4 (FIG. 1, FIG. 2 or FIG. 4) of the amplifier AMPb are manufactured using the same layout as FIG. 7, and the matching circuits IM1 and IM2 (FIG. 1, FIG. 2 or FIG. 4) is manufactured using the same layout as in FIG. The inductors L1, L2, L3, and L4 included in the amplifier AMPb are used for impedance matching of intermediate frequency signals. For this reason, the sizes of the inductors L1, L2, L3, and L4 included in the amplifier AMPb are larger than the sizes of the inductors L1, L2, L3, and L4 included in the amplifier AMPa. However, the effect of reducing the sizes of the inductors L1 and L2 by including the switches S1 and S2 in the matching circuits IM1 and IM2 is the same as in FIGS.

  The amplifier AMPb amplifies the signal IF from the mixer MIX during the reception mode, and outputs the amplified signal to the reception circuit RCV via the switch circuit SW1. In addition, the amplifier AMPb amplifies the signal output from the transmission circuit TRS via the switch circuit SW1 during the transmission mode, and outputs the amplified signal to the mixer MIX.

  The switch circuit SW1 connects the input / output port of the amplifier AMPb to the input of the reception circuit RCV during the reception mode, and transmits the signal from the amplifier AMPb to the reception circuit RCV. The switch circuit SW1 connects the output of the transmission circuit TRS to the input / output port of the amplifier AMPb during the transmission mode, and transmits the signal from the transmission circuit TRS to the amplifier AMPb.

  When the amplifiers AMPa and AMPb are the amplifier AMP1 shown in FIG. 1, the voltage generation circuit VGEN generates a bias voltage supplied to the terminals VG1 and VG2 for each of the amplifiers AMPa and AMPb. When the amplifiers AMPa and AMPb are the amplifiers AMP2 shown in FIG. 2, the voltage generation circuit VGEN generates the bias voltages supplied to the terminals V1, V2, VG1 and VG2 for each of the amplifiers AMpa and AMPb as shown in FIG. To do. When the amplifiers AMPa and AMPb are the amplifiers AMP3 shown in FIG. 4, the voltage generation circuit VGEN supplies the bias voltages supplied to the terminals V1, V2, VG1, VG2, and VG3 for each of the amplifiers AMpa and AMPb as shown in FIG. To generate. For example, the reception mode is the first mode, and the transmission mode is the second mode.

  The control circuit CTRL controls the operations of the amplifiers AMPa, AMPb, the mixer MIX, and the switch circuit SW1 according to the reception mode and the transmission mode. Control signals output from the control circuit CTRL to the amplifiers AMPa and AMPb control the operations of the switches S1 and S2 shown in FIG. 1, FIG. 2, or FIG.

  The receiving circuit RCV receives audio data, character data, image data, etc. included in a signal received via the antenna ANT and processes the received data. The transmission circuit TRS generates a signal including voice data, character data, image data, and the like, and outputs the generated signal to the amplifier AMPb.

  FIG. 15 shows another example of the communication device CD. For example, the communication device CD is a wireless communication device such as a mobile phone. The communication device CD includes a transceiver TRSV, a voltage generation circuit VGEN, a control circuit CTRL, a reception circuit RSV, a transmission circuit TRS, and an antenna ANT.

  The transceiver TRSV includes reception amplifiers AMPr1 and AMPr2, a mixer MIXr, a local oscillator LOr, transmission amplifiers AMPt1 and AMPt2, a mixer MIXt, a local oscillator LOt, and a switch circuit SW2. For example, the amplifiers AMPr1, AMPr2, AMPt1, and AMPt2 are the amplifier AMP4 shown in FIG. 11, and the input / output port P1 is used as an input port and the input / output port P2 is used as an output port.

  The switch circuit SW2 is connected to the antenna ANT, transmits a signal received by the antenna ANT to the amplifier AMPr1, and outputs a signal from the amplifier AMPt1 to the antenna ANT. Since the signals handled by the amplifiers AMPr1 and AMPt1 are high-frequency signals RF, the transmission loss of the signal by the switch circuit SW2 is larger than the transmission loss by the switch circuit SW1 that handles the signal of the intermediate frequency IF shown in FIG. In order to reduce the transmission loss, the switch circuit SW2 is a complicated circuit. In other words, in the transceiver TRSV and the communication device CD shown in FIG. 14, the switch circuit SW1 can be arranged on the transmission path of the down-converted low-frequency signal. For this reason, the transmission loss of the switch circuit SW1 can be made smaller than the transmission loss of the switch circuit SW2, and the circuit scale of the switch circuit SW1 can be made smaller than the circuit scale of the switch circuit SW2.

  As described above, also in this embodiment, a bidirectional amplifier can be realized by switching the short-circuit and the open-circuit of the switches S1 and S2 similarly to the effects of the amplifiers AMP1, AMP2, and AMP3 shown in FIGS. In addition, the sizes of the inductors L1 and L2 can be reduced compared to the conventional one, and the circuit scale of the amplifier AMP2 can be reduced compared to the conventional one. As a result, the circuit scale of the transmitter / receiver TRSV can be reduced as compared with the conventional case, and the cost of the communication device CD can be reduced as compared with the conventional case.

  Furthermore, since the switch circuit SW1 can be arranged in the down-converted low-frequency signal transmission path, the transmission loss due to the switch circuit SW1 can be made smaller than the transmission loss due to the switch circuit SW2 shown in FIG. In other words, since there is no switch circuit on the antenna ANT side, the generation of reception noise can be suppressed and the power of the signal output from the antenna ANT can be increased as compared with the communication device CD shown in FIG.

  FIG. 16 shows another example of the voltage generation circuit VGEN that generates the bias voltages V1, V2, VG1, and VG2 supplied to the amplifier AMP2 shown in FIG. The voltage generation circuit VGEN includes a voltage generation unit VGEN1 that generates the bias voltage V1, a voltage generation unit VGEN2 that generates the bias voltage V2, a voltage generation unit VGEN3 that generates the bias voltage V3, and a voltage generation unit VGEN4 that generates the bias voltage V4. Have.

  The voltage generator VGEN1 includes a pMOS transistor P1 and an nMOS transistor N1 connected between the voltage line VO2 and the ground line VSS. The gate of the pMOS transistor P1 receives a signal obtained by inverting the logic of the mode signal MD2, and the gate of the nMOS transistor N1 receives a mode signal MD1. The voltage generator VGEN2 includes a pMOS transistor P2 and an nMOS transistor N2 connected between the voltage line VO2 and the ground line VSS. The gate of the pMOS transistor P2 receives a signal obtained by inverting the logic of the mode signal MD1, and the gate of the nMOS transistor N2 receives a mode signal MD2.

  The voltage generator VGEN3 includes a pMOS transistor P3 and an nMOS transistor N3 connected between the voltage line VO1 and the ground line VSS. The gate of the pMOS transistor P3 receives a signal obtained by inverting the logic of the mode signal MD2, and the gate of the nMOS transistor N3 receives a mode signal MD1. The voltage generator VGEN4 includes a pMOS transistor P4 and an nMOS transistor N4 connected between the voltage line VO1 and the ground line VSS. The gate of the pMOS transistor P4 receives a signal obtained by inverting the logic of the mode signal MD1, and the gate of the nMOS transistor N4 receives a mode signal MD2.

  For example, the mode signals MD1 and MD2 are generated by a control circuit that controls the operation of the switches S1 and S2. For example, the mode signal MD1 is set to a high level during the first mode in which the switch S1 is short-circuited and the switch S2 is opened, and is set to a low level during the second mode in which the switch S1 is opened and the switch S2 is short-circuited. Is done. For example, the mode signal MD2 is set to a low level during the first mode in which the switch S1 is short-circuited and the switch S2 is opened, and is set to a high level during the second mode in which the switch S1 is opened and the switch S2 is short-circuited. Is done.

  The operation of the switch S1 may be controlled by the mode signal MD1, and the operation of the switch S2 may be controlled by the mode MD2. When the switches S1 and S2 are field effect transistors, it is preferable to use n-type channel type transistors. Further, the bias voltage VO2 supplied to the voltage line VO2 is higher than the bias voltage VO1 supplied to the voltage line VO1. The voltage generation circuit VGEN may have a circuit such as a regulator that generates the bias voltages VO1 and VO2. The voltage generation circuit VGEN illustrated in FIGS. 3 and 5 may include voltage generation units VGEN1 and VGEN2. In this case, the bias voltages V1 and V2 are generated by the voltage generation units VGEN1 and VGEN2. .

  FIG. 17 shows an example of the operation of the voltage generation circuit VGEN shown in FIG. The voltage generation circuit VGEN shown in FIG. 16 sets the terminal V1 to the ground voltage VSS, sets the terminal VG1 to the ground voltage VSS or higher, for example, during the first mode in which the mode signal MD1 is set to the high level. VG2 is set to a bias voltage VO1 higher than the bias voltage V1, and the terminal V2 is set to a bias voltage VO2 higher than the bias voltage VO1.

  By setting bias voltages to the terminals V1, V2, VG1, and VG2, drain currents flow through the transistors T1 and T2 from the terminal V2 to the terminal V1 shown in FIG. The signal supplied to the input / output port P1 is sequentially amplified by the transistors T1 and T2 and output from the input / output port P2.

  On the other hand, during the second mode in which the mode signal MD2 is set to the high level, the voltage generation circuit VGEN sets, for example, the terminal V1 to the bias voltage VO2, sets the terminal V2 to the ground voltage VSS, and biases the terminal VG1. The voltage VO1 is set, and the terminal VG2 is set to the ground voltage VSS. By setting the bias voltage to the terminals V1, V2, VG1, and VG2, the drain current flows through the transistors T1 and T2 from the terminal V1 to the terminal V2 shown in FIG. 2, as in the first mode. The signal supplied to the input / output port P2 is sequentially amplified by the transistors T2 and T1 and output from the input / output port P1.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A plurality of first transistors arranged in series between the first terminal and the second terminal and gate-grounded;
A first inductor connected between the first terminal and a second transistor disposed on one end of the plurality of first transistors;
The signal connected between the first terminal and the second transistor, short-circuited during the first mode of outputting a signal received at the first terminal to the second terminal, and receiving a signal at the second terminal A first switch opened during the second mode for outputting to the first terminal;
A second inductor connected between the second terminal and a third transistor disposed on the other end side of the plurality of first transistors;
An amplifier comprising: a second switch connected between the second terminal and the third transistor, opened during the first mode, and short-circuited during the second mode.
(Appendix 2)
The first switch has one of a source and a drain connected to the first terminal, the other of the source and the drain connected to the second transistor, and gates a voltage for conducting between the source and the drain during the first mode. A field effect transistor that receives at the gate a voltage that cuts off between the source and drain during the second mode,
The second switch has one of a source and a drain connected to the second terminal, the other of the source and the drain connected to the third transistor, and gates a voltage that cuts off the source and drain during the first mode. The amplifier according to claim 1, further comprising: a field effect transistor that receives at a gate a voltage that conducts between the source and the drain during the second mode.
(Appendix 3)
A third inductor having one end connected between the first terminal and the first inductor and the other end connected to the first voltage terminal;
A fourth inductor having one end connected between the second terminal and the second inductor and the other end connected to a second voltage terminal;
During the first mode, the voltage of the first voltage terminal is set lower than the voltage of the second voltage terminal;
The amplifier according to appendix 1 or appendix 2, wherein the voltage of the first voltage terminal is set higher than the voltage of the second voltage terminal during the second mode.
(Appendix 4)
During the first mode, the gate voltage of the second transistor is set to be higher than the voltage of the first voltage terminal, the gate voltage of the third transistor is set higher than the gate voltage of the second transistor, and The voltage of the second voltage terminal is set higher than the gate voltage of the third transistor,
During the second mode, the gate voltage of the third transistor is set to be higher than the voltage of the second voltage terminal, the gate voltage of the second transistor is set higher than the gate voltage of the third transistor, and The amplifier according to appendix 3, wherein the voltage of the first voltage terminal is set higher than the gate voltage of the second transistor.
(Appendix 5)
When the inductance of the first inductor is Cgd between the gate and drain of the second transistor, Csw is the capacitance when the first switch is open, and ω is the frequency of the signal received at the first terminal, The amplifier according to any one of appendix 1 to appendix 4, wherein the amplifier is smaller than 1 / (ω ² (Csw + Cgd)).
(Appendix 6)
The inductance of the second inductor is that the capacitance between the gate and drain of the third transistor is Cgd, the capacitance when the second switch is open is Csw, and the frequency of the signal received at the second terminal is ω, The amplifier according to any one of appendix 1 to appendix 5, wherein the amplifier is smaller than 1 / (ω ² (Csw + Cgd)).
(Appendix 7)
A first amplifier, a mixer and a second amplifier connected in series between a first terminal to which a high frequency signal is transmitted and a second terminal to which an intermediate frequency signal is transmitted;
The first amplifier includes:
A plurality of first transistors arranged in series between the first terminal and the mixer and having a gate grounded;
A first inductor connected between the first terminal and a second transistor disposed on the first terminal side of the plurality of first transistors;
The signal connected between the first terminal and the second transistor, short-circuited during the first mode of outputting a signal received at the first terminal to the second terminal, and receiving the signal received at the second terminal in the first mode. A first switch opened during the second mode of outputting to one terminal;
A second inductor connected between the mixer and a third transistor disposed on the mixer side of the plurality of first transistors;
A transceiver comprising: a second switch connected between the mixer and the third transistor, opened during the first mode, and short-circuited during the second mode.
(Appendix 8)
The second amplifier includes:
A plurality of fourth transistors arranged in series between the second terminal and the mixer and gate-grounded;
A third inductor connected between the mixer and a fifth transistor disposed on the mixer side of the fourth transistor;
A third switch connected between the mixer and the fifth transistor, short-circuited during the first mode, and opened during the second mode;
A fourth inductor connected between the second terminal and a sixth transistor disposed on the second terminal side of the fourth transistor;
A supplementary note 7 comprising: a fourth switch connected between the second terminal and the sixth transistor, opened during the first mode, and short-circuited during the second mode. The transceiver described.
(Appendix 9)
The second terminal is connected to a receiving circuit that processes a signal received at the first terminal during the first mode, and an original signal output from the first terminal is generated during the second mode. The transmitter / receiver according to appendix 7 or appendix 8, wherein the transmitter circuit includes a switch circuit that connects the second terminal.
(Appendix 10)
A first amplifier, a mixer and a second amplifier connected in series between a first terminal to which a high-frequency signal is transmitted and a second terminal to which an intermediate-frequency signal is transmitted, and the first terminal via the second terminal A transceiver having a switch circuit connected to two amplifiers;
A control circuit for generating a first control signal for controlling the operation of the first amplifier, a second control signal for controlling the operation of the second amplifier, and a third control signal for controlling the operation of the switch circuit;
A receiving circuit for processing a signal received at the first terminal during a first mode in which a signal received at the first terminal is output to the second terminal;
A transmission circuit for generating an original signal of the signal output from the first terminal during the second mode in which the signal from the second terminal is output to the first terminal;
The first amplifier includes:
A plurality of first transistors arranged in series between the first terminal and the mixer and having a gate grounded;
A first inductor connected between the first terminal and a second transistor disposed on the first terminal side of the plurality of first transistors;
A first switch connected between the first terminal and the second transistor, short-circuited during the first mode and opened during the second mode in response to the first control signal;
A second inductor connected between the mixer and a third transistor disposed on the mixer side of the plurality of first transistors;
A second switch connected between the mixer and the third transistor and opened during the first mode and short-circuited during the second mode in response to the first control signal;
The switch circuit connects the second terminal to the receiving circuit during the first mode and connects the second terminal to the transmission circuit during the second mode according to the third control signal. A communication device characterized by:
(Appendix 11)
A third inductor having one end connected between the first terminal and the first inductor and the other end connected to the first voltage terminal;
A fourth inductor having one end connected between the mixer and the second inductor and the other end connected to a second voltage terminal;
A voltage supplied to the first voltage terminal and the second voltage terminal is generated, and a voltage supplied to the first voltage terminal is set lower than a voltage supplied to the second voltage terminal during the first mode. The voltage generation circuit that sets the voltage supplied to the first voltage terminal higher than the voltage supplied to the second voltage terminal during the second mode is provided. Communication device.
(Appendix 12)
The voltage generation circuit includes:
Further, a voltage to be supplied to the gates of the plurality of first transistors is generated,
During the first mode, the gate voltage of the second transistor is set to be equal to or higher than the voltage of the first voltage terminal, the gate voltage of the third transistor is set higher than the gate voltage of the second transistor, and Setting the voltage at the voltage terminal higher than the gate voltage of the third transistor;
During the second mode, the gate voltage of the third transistor is set to be equal to or higher than the voltage of the second voltage terminal, the gate voltage of the second transistor is set higher than the gate voltage of the third transistor, The communication apparatus according to appendix 11, wherein the voltage at the voltage terminal is set higher than the gate voltage of the second transistor.
(Appendix 13)
The second amplifier includes:
A plurality of fourth transistors arranged in series between the second terminal and the mixer and gate-grounded;
A fifth inductor connected between the mixer and a fifth transistor disposed on the mixer side of the fourth transistor;
A third switch connected between the mixer and the fifth transistor, short-circuited during the first mode and opened during the second mode in response to the second control signal;
A sixth inductor connected between the second terminal and a sixth transistor disposed on the second terminal side of the fourth transistor;
A fourth switch connected between the second terminal and the sixth transistor, and opened in the first mode and short-circuited in the second mode in response to the second control signal. The communication device according to any one of appendix 10 to appendix 12, wherein the communication device is characterized in that:
(Appendix 14)
A seventh inductor having one end connected between the mixer and the fifth inductor and the other end connected to a third voltage terminal;
An eighth inductor having one end connected between the second terminal and the sixth inductor and the other end connected to a fourth voltage terminal;
The voltage generation circuit generates a voltage to be supplied to the third voltage terminal and the fourth voltage terminal, and supplies a voltage to be supplied to the third voltage terminal to the fourth voltage terminal during the first mode. The communication device according to claim 13, wherein the voltage supplied to the third voltage terminal is set higher than the voltage supplied to the fourth voltage terminal during the second mode. .
(Appendix 15)
The voltage generation circuit includes:
Further, a voltage to be supplied to the gate of the fourth transistor is generated,
During the first mode, the gate voltage of the fifth transistor is set to be higher than the voltage of the third voltage terminal, the gate voltage of the sixth transistor is set higher than the gate voltage of the fifth transistor, Setting the voltage at the voltage terminal higher than the gate voltage of the sixth transistor;
During the second mode, the gate voltage of the sixth transistor is set to be equal to or higher than the voltage of the fourth voltage terminal, the gate voltage of the fifth transistor is set higher than the gate voltage of the sixth transistor, The communication device according to appendix 14, wherein the voltage at the voltage terminal is set higher than the gate voltage of the fifth transistor.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  AMP1, AMP2, AMP3 ... Amplifier; AMPa, AMPb ... Amplifier; ANT ... Antenna; CD ... Communication device; CTRL ... Control circuit; IM1, IM2, IM3, IM4 ... Matching circuit; L1, L2, L3, L4, L5, L6 Inductor; LO Local oscillator; LSI Semiconductor integrated circuit chip; MIX Mixer; P1, P2 Input / output port; RSV Receive circuit; S1, S2 Switch; SW1 Switch circuit; T1, T2, T3 Transistor TRS Transmission circuit TRSV Transceiver VGEN Voltage generation circuit

Claims (7)

A plurality of first transistors arranged in series between the first terminal and the second terminal and gate-grounded;
A first inductor connected between the first terminal and a second transistor disposed on one end of the plurality of first transistors;
The signal connected between the first terminal and the second transistor, short-circuited during the first mode of outputting a signal received at the first terminal to the second terminal, and receiving a signal at the second terminal A first switch opened during the second mode for outputting to the first terminal;
A second inductor connected between the second terminal and a third transistor disposed on the other end side of the plurality of first transistors;
An amplifier comprising: a second switch connected between the second terminal and the third transistor, opened during the first mode, and short-circuited during the second mode. The first switch has one of a source and a drain connected to the first terminal, the other of the source and the drain connected to the second transistor, and gates a voltage for conducting between the source and the drain during the first mode. A field effect transistor that receives at the gate a voltage that cuts off between the source and drain during the second mode,
The second switch has one of a source and a drain connected to the second terminal, the other of the source and the drain connected to the third transistor, and gates a voltage that cuts off the source and drain during the first mode. 2. The amplifier according to claim 1, further comprising: a field effect transistor that receives at a gate a voltage that conducts between the source and the drain during the second mode. A first amplifier, a mixer and a second amplifier connected in series between a first terminal to which a high frequency signal is transmitted and a second terminal to which an intermediate frequency signal is transmitted;
The first amplifier includes:
A plurality of first transistors arranged in series between the first terminal and the mixer and having a gate grounded;
A first inductor connected between the first terminal and a second transistor disposed on the first terminal side of the plurality of first transistors;
The signal connected between the first terminal and the second transistor, short-circuited during the first mode of outputting a signal received at the first terminal to the second terminal, and receiving the signal received at the second terminal in the first mode. A first switch opened during the second mode of outputting to one terminal;
A second inductor connected between the mixer and a third transistor disposed on the mixer side of the plurality of first transistors;
A transceiver comprising: a second switch connected between the mixer and the third transistor, opened during the first mode, and short-circuited during the second mode. The second amplifier includes:
A plurality of fourth transistors arranged in series between the second terminal and the mixer and gate-grounded;
A third inductor connected between the mixer and a fifth transistor disposed on the mixer side of the fourth transistor;
A third switch connected between the mixer and the fifth transistor, short-circuited during the first mode, and opened during the second mode;
A fourth inductor connected between the second terminal and a sixth transistor disposed on the second terminal side of the fourth transistor;
4. A fourth switch connected between the second terminal and the sixth transistor, opened during the first mode, and short-circuited during the second mode. The transceiver described in 1. The second terminal is connected to a receiving circuit that processes a signal received at the first terminal during the first mode, and an original signal output from the first terminal is generated during the second mode. The transmitter / receiver according to claim 3, further comprising: a switch circuit that connects the second terminal to the transmitter circuit that performs the operation. A first amplifier, a mixer and a second amplifier connected in series between a first terminal to which a high-frequency signal is transmitted and a second terminal to which an intermediate-frequency signal is transmitted, and the first terminal via the second terminal A transceiver having a switch circuit connected to two amplifiers;
A control circuit for generating a first control signal for controlling the operation of the first amplifier, a second control signal for controlling the operation of the second amplifier, and a third control signal for controlling the operation of the switch circuit;
A receiving circuit for processing a signal received at the first terminal during a first mode in which a signal received at the first terminal is output to the second terminal;
A transmission circuit for generating an original signal of the signal output from the first terminal during the second mode in which the signal from the second terminal is output to the first terminal;
The first amplifier includes:
A plurality of first transistors arranged in series between the first terminal and the mixer and having a gate grounded;
A first inductor connected between the first terminal and a second transistor disposed on the first terminal side of the plurality of first transistors;
A first switch connected between the first terminal and the second transistor, short-circuited during the first mode and opened during the second mode in response to the first control signal;
A second inductor connected between the mixer and a third transistor disposed on the mixer side of the plurality of first transistors;
A second switch connected between the mixer and the third transistor and opened during the first mode and short-circuited during the second mode in response to the first control signal;
The switch circuit connects the second terminal to the receiving circuit during the first mode and connects the second terminal to the transmission circuit during the second mode according to the third control signal. A communication device characterized by: The second amplifier includes:
A plurality of fourth transistors arranged in series between the second terminal and the mixer and gate-grounded;
A fifth inductor connected between the mixer and a fifth transistor disposed on the mixer side of the fourth transistor;
A third switch connected between the mixer and the fifth transistor, short-circuited during the first mode and opened during the second mode in response to the second control signal;
A sixth inductor connected between the second terminal and a sixth transistor disposed on the second terminal side of the fourth transistor;
A fourth switch connected between the second terminal and the sixth transistor, and opened in the first mode and short-circuited in the second mode in response to the second control signal. The communication device according to claim 6.

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