JP2013243354A - Semiconductor circuit exposure method and exposure device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit exposure method and an exposure device, which achieve high precision in pattern transfer.SOLUTION: In a semiconductor circuit exposure method of a present embodiment, after exposing EUV light on a first reflection type mask on which a circuit pattern region is formed, the circuit pattern region and a light-shielding frame region are transferred by a projection optical system via a second reflection type mask on which a light-shielding frame region is formed. Accordingly, adhesion to the circuit pattern region of particles from a processing surface generated by a digging process of a multilayer reflective layer when the light-shielding frame region is formed can be prevented. By using an exposure device and the exposure method of the present embodiment, degradation of the semiconductor circuit can be inhibited.

Description

  The present invention relates to a semiconductor circuit exposure method and exposure apparatus. In particular, the present invention relates to an exposure method and an exposure apparatus for a semiconductor circuit used for semiconductor manufacturing using EUV lithography using extreme ultraviolet (EUV) as a light source.

  In recent years, with the miniaturization of semiconductor devices, EUV lithography using EUV having a wavelength of around 13.5 nm as a light source has been proposed. Since EUV lithography has a short light source wavelength and very high light absorption, it needs to be performed in a vacuum. In the EUV wavelength region, the refractive index of most substances is slightly smaller than 1. For this reason, the EUV lithography cannot use a transmission type refractive optical system which has been used conventionally, and becomes a reflection optical system. Therefore, a photomask (hereinafter referred to as a mask) as an original plate must be a reflection type mask because a conventional transmission type mask cannot be used.

  A reflective mask blank that is the basis of such a reflective mask has a multilayer reflective layer showing a high reflectivity with respect to the exposure light source wavelength and an absorption layer of the exposure light source wavelength sequentially formed on a low thermal expansion substrate. Further, a back surface conductive film for an electrostatic chuck in the exposure machine is formed on the back surface of the substrate. There is also an EUV mask having a structure having a buffer layer between the multilayer reflective layer and the absorption layer. When processing from a reflective mask blank to a reflective mask, the absorber layer is partially removed by EB lithography and etching technology, and in the case of a structure having a buffer layer, this is also removed, and from the absorber and reflector A circuit pattern is formed. The light image reflected by the reflection type mask thus produced is transferred onto the semiconductor substrate through a reflection optical system.

  In an exposure method using a reflective optical system, irradiation is performed at an incident angle (usually 6 °) tilted by a predetermined angle from the vertical direction with respect to the mask surface. Therefore, when the absorption layer is thick, a shadow of the pattern itself is generated. Therefore, since the reflection intensity in the shadowed portion is smaller than that in the non-shadowed portion, the contrast is lowered, and the edge portion of the transfer pattern is blurred and deviated from the design dimension. This is called shadowing and is one of the fundamental problems of the reflective mask. In order to prevent such blurring of the pattern edge portion and deviation from the design dimension, it is effective to reduce the thickness of the absorption layer and reduce the height of the pattern, but when the thickness of the absorption layer becomes small In addition, the light shielding property in the absorbing layer is lowered, the transfer contrast is lowered, and the accuracy of the transfer pattern is lowered. That is, if the absorption layer is too thin, the contrast necessary for maintaining the accuracy of the transfer pattern cannot be obtained. Accordingly, since the thickness of the absorption layer is too thick or too thin, it is currently in the range of 50 to 90 nm, and the reflectance of the EUV light absorption layer is 0.5 to 2%. Degree.

  On the other hand, when a transfer circuit pattern is formed on a semiconductor substrate using a reflective mask, chips having a plurality of circuit patterns are formed on one semiconductor substrate. There may be a region where the outer periphery of the chip overlaps between adjacent chips. This is because the chips are arranged at a high density in order to improve productivity in order to increase the number of chips that can be taken per wafer. In this case, this region is exposed (multiple exposure) a plurality of times (up to four times). The chip outer peripheral portion of this transfer pattern is also the outer peripheral portion on the mask, and is usually the absorption layer portion. However, as described above, since the reflectance of EUV light on the absorption layer is about 0.5 to 2%, there is a problem that the outer periphery of the chip is exposed by multiple exposure. For this reason, the necessity has arisen for the area | region (henceforth a light-shielding frame) where the chip | tip outer peripheral part on a mask has a higher light-shielding property of EUV light than a normal absorption layer.

  The multiple exposure described above has a problem that not only EUV light but also the near-infrared region light from vacuum ultraviolet rays other than the 13.5 nm band called out-of-band (OoB: Out of Band) is sensitive to the outer periphery of the chip. is there. The OoB light is reflected by the EUV absorption layer (the main material is a large amount of Ta) on the outermost surface of the mask, and is irradiated onto the wafer. Therefore, light having various wavelengths other than 13.5 nm is irradiated on the resist on the wafer and exposed to light, which adversely affects the pattern size in the vicinity of the chip boundary region.

  In order to solve such a problem, by reducing the reflectance of the multilayer reflective layer by forming a groove dug from the absorption layer of the reflective mask to the multilayer reflective layer, the light shielding property with respect to the wavelength of the exposure light source is reduced. A reflective mask provided with a high light shielding frame has been proposed. (Patent Document 1)

JP 2009-212220 A

However, in order to dig a multilayer reflective layer, it is necessary to process a total of 80 layers of Si and Mo of different materials, and very complicated conditions are indispensable for realizing the dry etching process.
In addition, since this method removes the multilayer reflective layer, the generation of particles from the processed surface of the multilayer reflective layer is unavoidable, and there is a risk of particles adhering to the circuit pattern region, leading to a reduction in mask quality. .

  Accordingly, the present invention has been made to solve the above-described problem, and a semiconductor that can perform pattern transfer without causing particles generated from the processed surface of the multilayer reflective layer to adhere to the circuit pattern region. An object of the present invention is to provide a circuit manufacturing method and an exposure apparatus.

As means for solving the above problems, claim 1 of the present invention provides:
A semiconductor circuit exposure method comprising: combining a first reflective mask pattern by EUV light and a reflective pattern from a second reflective mask pattern and exposing and transferring the resultant pattern onto a semiconductor substrate.
That is, in the semiconductor circuit exposure method according to the present invention, the EUV light from the EUV light source is irradiated to the first reflective mask through the reflective optical system through the reflective optical system, and irradiated to the first reflective mask. Then, the mask pattern formed on the first reflective mask and the mask pattern formed on the second reflective mask are transferred to the semiconductor substrate through the second reflective mask. The reflective mask on the side where the circuit pattern is defined in the circuit pattern region does not have a light shielding frame formed by digging a multilayer reflective layer for defining the outer periphery of the chip.

  According to a second aspect of the present invention, in the mask pattern formed on the first reflective mask and the second reflective mask, the pattern including at least a circuit pattern region is one of the reflective patterns. 2. The semiconductor circuit exposure method according to claim 1, wherein a pattern formed on the mask and including at least a light shielding frame region is formed on the other reflective mask.

  The invention according to claim 3 is an exposure apparatus used in an exposure method using EUV light from an EUV light source, wherein the EUV light is applied to the first reflective mask via a reflective optical system, After irradiating the first reflective mask, the mask pattern formed on the first reflective mask and the mask pattern formed on the second reflective mask via the second reflective mask Is transferred onto a semiconductor substrate by a projection optical system.

  According to a fourth aspect of the present invention, there is provided a mask stage for mounting the first reflective mask, a mask stage for mounting the second reflective mask, or a semiconductor substrate for mounting a semiconductor substrate. The exposure apparatus is characterized in that the stage moves in the X-axis, Y-axis, and Z-axis directions.

  A fifth aspect of the present invention is a reflective mask used in the semiconductor circuit exposure method and exposure apparatus according to the first to fifth aspects.

  In the present invention, after the first reflective mask on which the circuit pattern area is formed is irradiated with EUV light, the circuit pattern area and the light shielding frame are passed through the second reflective mask on which the light shielding frame area is formed. Since the area is transferred to the semiconductor substrate by the projection optical system, the circuit pattern area and the light shielding frame area are separately formed on different masks, so that the processing surface generated by the dug of the multilayer reflective layer when forming the light shielding frame area Can be prevented from adhering to the circuit pattern region. Then, by using the exposure method and the exposure apparatus of the present invention, it is possible to suppress the deterioration of the quality of the semiconductor circuit.

1 is a block diagram showing an example of an exposure apparatus of the present invention. An example of the 1st reflective mask used for the exposure apparatus of this invention. An example of the 2nd reflective mask used for the exposure apparatus of this invention. The first reflective mask used in the examples. The manufacturing process of the 1st reflective mask used in an Example. A second reflective mask used in the examples. The manufacturing process of the 2nd reflective mask used in an Example. Reflective mask used in the examples.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
First, the configuration of an example of the exposure apparatus of the present invention will be described.
FIG. 1 shows a block diagram of an exposure apparatus. The exposure apparatus includes a light source 1 that supplies EUV light having a wavelength of 13.5 nm as exposure light, a reflection optical system 6, a mask stage 2 on which the first reflective mask 4 is placed, and a second reflection. A mask stage 2 for placing the mold mask 5, a reflective projection optical system 9, a semiconductor substrate stage 13 for placing the semiconductor substrate 12, a housing 15 for housing the optical system, and the like. The permutation and position of the reflective optical system, the first reflective mask, and the second reflective mask are arbitrary.

  The optical path from the light source 1 to the semiconductor substrate 12 is evacuated so that EUV light absorption is as low as possible, thereby protecting it from contamination.

  The mask stage 2 on which the first reflective mask 4 and the second reflective mask 5 are placed is supported so as to be movable in the X-axis, Y-axis, and Z-axis directions. The semiconductor substrate stage 13 on which the semiconductor substrate 12 is placed is also supported so as to be movable in the X-axis, Y-axis, and Z-axis directions.

  The reflective optical system is composed of a plurality of multilayer mirrors in which, for example, a multilayer film in which Mo / Si is alternately laminated is coated on the surface of a substrate such as low thermal expansion glass. By forming the reflective surface of the multilayer mirror as a concave surface, a positive optical power can be applied, and conversely, if it is formed as a convex surface, a negative optical power can be applied. The magnitude of the optical power can be determined according to the radius of curvature of the reflecting surface.

FIG. 2 is an example of a first reflective mask used in the exposure apparatus of this example.
The first reflective mask 4 includes a substrate 23, a multilayer reflective layer 22 on the substrate 23, and an absorption film 21 that forms a circuit pattern region 20. The substrate 23 is formed of quartz glass, low thermal expansion glass, or the like.
The multilayer reflective layer 22 is formed of a MoSi multilayer film having a sufficient reflectance with respect to EUV light.
The absorption film 21 is formed of a material that can absorb or block EUV light. For example, there are Ta, TaBN and the like.

FIG. 3 is an example of a second reflective mask used in the exposure apparatus of this example.
The second reflective mask 5 includes a substrate 31, a multilayer reflective layer 54 on the substrate 31, and an absorption layer 29 that forms a light shielding frame region 27.
The substrate 31 is made of quartz glass, low thermal expansion glass, or the like.
The multilayer reflective layer 54 is formed of a MoSi multilayer film having a sufficient reflectance with respect to EUV light.
The absorption layer 29 is formed of a material that can absorb or block EUV light. For example, there are Ta, TaBN and the like.

Next, the exposure operation will be described.
The exposure light supplied from the light source 1 is reflected by the reflection optical system 6 and enters the first reflective mask 4 obliquely. The exposure light reflected from the first reflective mask 4 is reflected by another reflective optical system and enters the second reflective mask 5 obliquely.
The exposure light reflected from the second reflective mask 5 is transferred to the semiconductor substrate 12 via the reflective projection optical system 9.

  An opening 7 through which reflected light reflected from the reflective projection optical system passes is provided on the lower surface of the housing 15, and the opening mouth can be set variably.

Examples of the present invention will be described below.
FIG. 4A shows a low thermal expansion glass substrate 32 used in the first reflective mask.
A conductive film 33 for electrostatic chucking was formed on the back surface as shown in FIG. A 40-pair reflective layer 34 of Mo and Si designed to have a reflectivity of about 64% with respect to EUV light having a wavelength of 13.5 nm is laminated on the low thermal expansion glass substrate 32 as shown in FIG. . Subsequently, an absorption layer 35 made of TaN was formed by a sputtering apparatus (FIG. 4D). The film thickness of the absorption layer 35 at this time was 50 nm. Thus, a reflective mask blank 36 used for the first reflective mask was produced.

A first reflective mask 39 having a circuit pattern region 38 formed from the reflective mask blank 36 shown in FIG. 4D was produced (FIG. 5B). The manufacturing method is shown.
A reflective mask blank 40 in which an electron beam resist 37 is applied on the absorption layer 35 shown in FIG. 5A is prepared, and the reflective mask blank 40 is subjected to electron beam lithography, dry etching, and resist peeling cleaning to obtain a circuit pattern region. A first reflective mask 39 formed with 38 was produced. For electron beam lithography, a chemically amplified positive resist FEP171 (manufactured by FUJIFILM Electronics Materials) is used to draw a dose of 15 μC / cm by a lithography machine JBX9000 (manufactured by JEOL Ltd.), and then a resist is developed with a TMAH 2.38% developer. A pattern was formed. Cl2 inductively coupled plasma was applied to the etching of the absorption layer 35.

FIG. 6A shows a low thermal expansion glass substrate 41 used in the second reflective mask.
A conductive film 42 for electrostatic chucking was formed on the back surface as shown in FIG. A 40 pair reflective layer 53 of Mo and Si designed to have a reflectivity of about 64% with respect to EUV light having a wavelength of 13.5 nm was laminated on the low thermal expansion glass substrate 41 as shown in FIG. . Subsequently, an absorption layer 43 made of TaN was formed by a sputtering apparatus (FIG. 6D). The film thickness of the absorption layer 43 at this time was 50 nm. Thus, the reflective mask blank 44 used for the second reflective mask was completed.

A second reflective mask 48 having a light shielding frame region 47 formed from the reflective mask blank 44 shown in FIG. 6D was produced (FIG. 7B). The manufacturing method is shown.
A reflective mask blank 46 in which an electron beam resist 45 is applied on the absorption layer 43 shown in FIG. 7A is prepared, and the reflective mask blank 46 is subjected to electron beam lithography, dry etching, and resist peeling cleaning to obtain a light shielding frame region. A second reflective mask 48 having 47 was formed. For electron beam lithography, a chemically amplified positive resist FEP171 (manufactured by FUJIFILM Electronics Materials) is used to draw a dose of 15 μC / cm by a lithography machine JBX9000 (manufactured by JEOL Ltd.), and then a resist is developed with a TMAH 2.38% developer. A pattern was formed. Cl2 inductively coupled plasma was applied to the etching of the absorption layer 43.

  Using the reflective mask blank 40 shown in FIG. 5A, a circuit pattern region 50 was formed by the same procedure for producing the first reflective mask 39 (FIG. 8A). After the formation, an electron beam resist was applied on the absorption layer 35, electron beam lithography, dry etching, and resist peeling cleaning were performed to produce a reflective mask 49 in which the light shielding frame region 51 was formed (FIG. 8B). For electron beam lithography, a chemically amplified positive resist FEP171 (manufactured by FUJIFILM Electronics Materials) is used to draw a dose of 15 μC / cm by a lithography machine JBX9000 (manufactured by JEOL Ltd.), and then a resist is developed with a TMAH 2.38% developer. A pattern was formed. Cl2 inductively coupled plasma was applied to the etching of the multilayer reflective layer 34.

  An appearance inspection was performed on the first reflective mask 39 in which the circuit pattern region 38 was formed and the second reflective mask 48 in which the light shielding frame region 47 was formed. As a result, no foreign matter was detected with the first reflective mask 39, and two foreign matters were detected with the second reflective mask 48. Further, when the appearance inspection of the reflective mask 49 in which the circuit pattern region 50 and the light shielding frame region 51 were formed, 20 foreign matters were detected. Therefore, by not forming the circuit pattern area and the light shielding frame area with the same mask, it prevents the particles from the processing surface generated by the dug of the multilayer reflective layer from adhering to the circuit pattern area when forming the light shielding frame area. did it.

DESCRIPTION OF SYMBOLS 1 ... Light source 2, 3 ... Mask stage 4, 16, 19, 39 ... 1st reflective mask 5, 24, 28, 48 ... 2nd reflective mask 6 ... Reflection Optical system 7: openings 8, 9, 10, 11 ... reflective projection optical system 12 ... semiconductor substrate 13 ... semiconductor substrate stage 14 ... EUV light 15 ... housings 17, 21, 26, 29, 35, 43 ... absorption layers 18, 20, 38, 50 ... circuit pattern regions 22, 34, 52, 53 ... multilayer reflective layers 23, 31 ... substrates 25, 27, 47 , 51..., Light shielding frame regions 32, 41... Low thermal expansion glass substrates 33, 42... Conductive films 36, 40, 44, 46 ... reflective mask blanks 37, 45. ... Reflective masks

Claims (5)

  The EUV light from the EUV light source is irradiated to the first reflective mask through the reflective optical system, and after being irradiated to the first reflective mask, the first reflection is performed through the second reflective mask. A method for exposing a semiconductor circuit, comprising: transferring a mask pattern formed on a mold mask and a mask pattern formed on a second reflective mask to a semiconductor substrate.   The mask pattern formed on the first reflective mask and the second reflective mask has a pattern including at least a circuit pattern region formed on one of the reflective masks and includes at least a light shielding frame region. 2. The semiconductor circuit exposure method according to claim 1, wherein the pattern is formed on the other reflective mask.   In an exposure apparatus used in an exposure method using EUV light from an EUV light source, the EUV light is applied to the first reflective mask through a reflective optical system, and is applied to the first reflective mask. Thereafter, the mask pattern formed on the first reflective mask and the mask pattern formed on the second reflective mask are transferred to the semiconductor substrate by the projection optical system via the second reflective mask. An exposure apparatus characterized by the above.   A mask stage for placing the first reflective mask and a mask stage for placing the second reflective mask, or a semiconductor substrate stage for placing a semiconductor substrate are an X-axis, a Y-axis, and a Z-axis. 4. The exposure apparatus according to claim 3, wherein the exposure apparatus moves in a direction. At least in a reflective mask in which a multilayer reflective layer and a patterned absorption film are formed on a substrate,
The first reflective mask defines a circuit pattern by patterning the absorbing film,
The second reflective mask defines a circuit pattern region formed by removing the absorption film, and defines a light shielding frame formed by removing the absorption film and the multilayer reflective layer in a frame shape around the circuit pattern region. Structure,
A reflective mask used to synthesize and transfer the patterns defined by the first and second masks.

Images