JP2013243342A - Semiconductor device, and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield and quality of products at a low cost.SOLUTION: A memory mat (101) includes a body part (200) including a first capacitor (203A), a linear conductive film (204) formed between the body part (200) and a peripheral circuit(104), and a second capacitor (203B) formed in a state where the conductive film (204) contacts its bottom part. The first capacitor (203A) is formed in a state where a contact layer (202) contacts its bottom part.

Description

  The present invention relates to a semiconductor device having memory cells.

  In a memory cell such as a DRAM (Dynamic Random Access Memory) cell, peripheral circuits such as a sub word driver and a sense amplifier are formed around a memory mat that is a circuit for storing data.

  In a memory mat, capacitors are formed on a contact layer called a capacitor and are formed in a matrix. This capacitor is usually formed by removing the interlayer insulating film of the capacitor using wet etching. A punching process is required. However, during the external removal process, there is a problem that the solution used in wet etching oozes out to the peripheral circuit, resulting in a decrease in product yield and a decrease in product quality.

  On the other hand, in the semiconductor device described in Patent Document 1, a solution used in wet etching is formed by forming a support film made of silicon nitride or the like on an interlayer oxide film of a capacitor so as to surround the memory mat. Prevents the memory mat from seeping into the peripheral circuit from the lateral direction or the upper surface side.

JP 2010-165742 A

  However, the semiconductor device described in Patent Document 1 has a problem that it may not be possible to prevent the solution used in wet etching from leaking into the peripheral circuit.

  Hereinafter, this problem will be described with reference to FIGS. FIG. 8 is a top view of the memory mat, and FIG. 9 is a cross-sectional view of the outer periphery of the memory mat (B-B ′ line in FIG. 8), in which phenomena that cause problems are written.

  As shown in FIGS. 8 and 9, each capacitor 1 of the memory mat 10 is formed on a capacitor 2. However, the position of the capacitor 1 and the position of the capacitor capacitor 2 do not completely coincide with each other due to the constraints on the layout of the memory cell and the positional deviation of the pattern caused by photolithography. As shown in FIG. The capacitor 1 may step off the capacitor 2.

  Conventionally, the pad is inserted between the capacitor 1 and the capacitor 2 to prevent the capacitor from being stepped on. In recent years, due to the miniaturization of the semiconductor device, double patterning is also performed to form the pad. This is often done, and the cost for forming the pad is high. For this reason, padlessness which does not use a pad advances, As a result, the stepping off of the capacitor 1 increases.

  Further, as the capacitor is miniaturized, the thickness of the lower electrode 1A of the capacitor 1 is reduced, and as a result, the solution used for wet etching may ooze downward from the lower electrode 1A. At this time, if the capacitor 1 has stepped off the capacitor 2, the solution will ooze out in a large amount into the interlayer oxide film 3 of the capacitor under the capacitor 1.

  In particular, when the capacitor 1 at the outermost periphery of the memory mat 10 has stepped off the capacitor 2, the solution oozes out to the peripheral circuit through the interlayer oxide film 3 of the capacitor 2, and the interlayer oxide film in the peripheral circuit. 3 large-scale elution occurs.

  If it is in the memory mat 10, the solution can be repaired even if the solution oozes out to the interlayer oxide film 3, but if the solution oozes out to the peripheral circuit, the repair becomes very difficult. It is important to prevent leaching of the solution into.

  On the other hand, in the semiconductor device described in Patent Document 1, since it is assumed that a pad is inserted between the capacitor and the capacitor, the stepping off of the capacitor is not taken into consideration, and the upper surface of the interlayer oxide film of the capacitor is not considered. Therefore, the solution cannot be prevented from oozing out to the peripheral circuit through the interlayer oxide film of the capacitor.

  A semiconductor device according to the present invention is a semiconductor device having a memory mat and a peripheral circuit formed around the memory mat, wherein the memory mat includes a main body having a first capacitor, and the main body. A linear conductive film formed between the peripheral circuit and a second capacitor formed in contact with the conductive film and the bottom, wherein the first capacitor has a contact layer and a bottom It is formed in contact.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device as described above, and includes a step of patterning the conductive film and a predetermined wiring in the peripheral circuit using a single mask.

  According to the present invention, since the second capacitor between the main body and the peripheral circuit is in contact with the conductive film and the bottom, the solution used in the wet etching is transferred from the lower electrode of the second capacitor to the capacitor. It becomes possible to prevent the solution from seeping out into the interlayer oxide film, and it is possible to prevent the solution from seeping out into the peripheral circuit. Furthermore, since the conductive film is linear, it is possible to pattern the conductive film using a predetermined wiring and a single mask of the peripheral circuit, thereby suppressing an increase in the cost for increasing the number of masks. Is possible. Therefore, the yield and quality of the product can be improved at low cost.

1 is a top view schematically showing memory cells included in a semiconductor device according to a first embodiment of the present invention. It is a figure which shows an example of a memory mat and the peripheral circuit formed in the circumference | surroundings. It is a top view which shows typically an example of a structure of a memory mat. It is a longitudinal cross-sectional view which shows an example of a structure of a memory mat typically. It is a top view which shows typically the other example of a structure of a memory mat. It is a top view which shows typically the other example of a structure of a memory mat. It is a top view which shows typically the other example of a structure of a memory mat. It is a figure for demonstrating the problem of a prior art. It is a figure for demonstrating the problem of the semiconductor device of a prior art. It is a figure which shows the other example of the memory mat and the peripheral circuit formed in the circumference | surroundings. It is the figure which expanded the area | region R of FIG. 10A. It is a figure for demonstrating the 1st process of the formation method which forms a memory mat. It is a figure for demonstrating the 2nd process of the formation method which forms a memory mat. It is a figure for demonstrating the 3rd process of the formation method which forms a memory mat. It is a figure for demonstrating the 4th process of the formation method which forms a memory mat. It is a figure for demonstrating the 5th process of the formation method which forms a memory mat. It is a figure for demonstrating the 6th process of the formation method which forms a memory mat. It is a figure for demonstrating the 7th process of the formation method which forms a memory mat. It is a figure for demonstrating the 8th process of the formation method which forms a memory mat. It is a figure for demonstrating the 9th process of the formation method which forms a memory mat. It is a figure for demonstrating the 10th process of the formation method which forms a memory mat. It is a figure for demonstrating the 11th process of the formation method which forms a memory mat. It is a figure for demonstrating the 12th process of the formation method which forms a memory mat. It is a figure for demonstrating the 13th process of the formation method which forms a memory mat. It is a longitudinal cross-sectional view which shows the other example of a structure of a memory mat typically. It is a longitudinal cross-sectional view which shows the other example of a structure of a memory mat typically. It is a top view which shows typically the other example of a structure of a memory mat.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having the same function may be denoted by the same reference numerals and description thereof may be omitted.

  FIG. 1 is a top view schematically showing a memory cell provided in the semiconductor device according to the first embodiment of the present invention.

  A memory cell 100 shown in FIG. 1 includes a plurality of memory mats 101 formed in a matrix and peripheral circuits 102 formed around each memory mat 101. In the present embodiment, each memory mat 101 is formed in a rectangular shape, and among the surface directions of the memory mat 101, the direction along one side of the memory mat 101 is the X direction, and the direction orthogonal to the X direction is the same. The Y direction is assumed.

  FIG. 2 is a diagram illustrating an example of the memory mat 101 and the peripheral circuit 102 formed around the memory mat 101. As shown in FIG. 2, a sub word driver (SWD) 103 and a sense amplifier (SAMP) 104 which are peripheral circuits 102 are formed around the memory mat 101. Specifically, the sub word driver 103 is formed on both sides of the memory mat 101 in the X direction, and the sense amplifier 104 is formed on both sides of the memory mat 101 in the Y direction.

  FIG. 3 is a top view schematically showing an example of the configuration of the memory mat 101.

  As shown in FIG. 3, the memory mat 101 includes a plurality of bit lines 201 extending in the Y direction, which is the first direction in the plane, and a plurality of container capacitors formed side by side along each bit line 201. 202 and a plurality of capacitors 203 formed on each capacitor 202.

  The bit lines 201 are arranged at predetermined intervals in the X direction, which is the second direction. The bit line 201A on the outermost periphery of the bit lines 201 is a dummy bit line.

  Each capacitor 202 is a contact layer that electrically connects the diffusion layer constituting the MOSFET that is the switching element of the memory mat 101 and the capacitor 203. Of each container 202, the container 202A on the outermost periphery in the Y direction is a dummy container. Hereinafter, the bit line 201A may be referred to as a dummy bit line 201A, and the capacitor 202A may be referred to as a dummy capacitor 202A.

  A portion surrounded by the dummy bit line 201A and the dummy capacitor capacitor 202A becomes the main body 200 that actually stores data. Therefore, a dummy bit line 201A extending in the Y direction is formed between the main body 200 and the peripheral circuit 102 in the X direction, and between the main body 200 and the peripheral circuit 102 in the Y direction. , Dummy capacitors 202A arranged in a line in the X direction are formed.

  An outermost peripheral capacitor pad 204, which is a linear conductive film, is formed between the main body 200 and the peripheral circuit 102 so as to cover the dummy capacitor 202A.

  Specifically, the outermost peripheral conpad 204 is provided on each of both sides in the Y direction of the main body 200 and extends in the X direction. The first capacitor, which is the capacitor 203 of the main body 200, is formed in contact with the capacitor capacitor 202, and the second capacitor, which is the capacitor 203 on the dummy capacitor capacitor 202 A, is connected to the outermost capacitor capacitor pad 204. The bottom is formed in contact.

  4 is a vertical cross-sectional view of the outer periphery of the memory mat 101 (A-A ′ line in FIG. 2).

As shown in FIG. 4, each capacitor 202 is embedded in the interlayer oxide film 211. The material of the interlayer oxide film 211 is, for example, SiO ₂ (silicon dioxide).

  An outermost peripheral capacitor pad 204 is formed on the dummy capacitor capacitor 202A of the capacitor capacitors 202 so that the bottom portion is in contact with the dummy capacitor capacitor 202A.

  Further, an interlayer insulating film 212 is formed so as to cover the capacitor capacitor 202, the interlayer oxide film 211, and the outermost peripheral capacitor pad 204. The interlayer insulating film 212 penetrates the interlayer insulating film 212 directly to the capacitor capacitor 202 or the outermost peripheral capacitor pad 204. A capacitor 203 is formed in contact with each other.

  Specifically, a first capacitor 203A is formed on each capacitor capacitor 202 except for the dummy capacitor capacitor 202A so that the bottom portion is in direct contact with the capacitor capacitor 202, and on the dummy capacitor capacitor 202A, the bottom portion is formed. A second capacitor 203 </ b> B is formed so as to be in contact with the outermost peripheral capacitor pad 204. The material of the interlayer insulating film 212 is, for example, SiN (silicon nitride).

  The outermost peripheral conpad 204 is formed by patterning predetermined wiring in the peripheral circuit 102 (for example, the M0 wiring 221 in the sense amplifier 104) by simultaneous exposure using a single mask. .

  As described above, according to the present embodiment, the second capacitor 203B between the main body 200 and the peripheral circuit 102 is in contact with the outermost peripheral capacitor pad 204 and the bottom, so that the solution used in wet etching is used. However, it is possible to prevent the solution from leaking out from the lower electrode of the second capacitor 203B to the interlayer oxide film 211 of the capacitor, and it is possible to prevent the solution from bleeding into the peripheral circuit 102. Further, since the outermost peripheral conpad 204 is linear, the outermost peripheral conpad 204 can be patterned using a predetermined wiring of the peripheral circuit 102 and a single mask, which increases the number of masks. An increase in cost can be suppressed. Therefore, the yield and quality of the product can be improved at low cost.

  In the present embodiment, a dummy bit line 201 is formed between the main body 200 and the peripheral circuit 102 in the Y direction. Therefore, since the dummy bit line 201 can prevent the solution from leaking out in the X direction, it is possible to prevent the solution from leaking out in the X direction, that is, the sub word driver 103.

  As described above, the semiconductor device according to the present embodiment includes the memory mat (101) and the peripheral circuit (104) formed around the memory mat (101). The memory mat (101) includes the first capacitor. (203A), a linear conductive film (204) formed between the main body (200) and the peripheral circuit (104), and the conductive film (204) and the bottom are in contact with each other. A second capacitor (203B) formed, and the first capacitor (203A) is formed in contact with the contact layer (202).

  In addition, the semiconductor device according to the present embodiment has the bit line (201) extending in the first direction in the plane of the memory mat (101), and the conductive film (204) includes the main body (200) and the peripheral circuit. (104) between the first direction and the second direction perpendicular to the first direction.

  In addition, the semiconductor device according to the present embodiment includes the dummy bit line (201A) extending in the first direction between the second direction of the main body (200) and the peripheral circuit (104). Yes.

  In addition, the method of manufacturing the semiconductor device according to the present embodiment includes a step of patterning the conductive film (204) and the predetermined wiring (221) in the peripheral circuit (104) using a single mask. Is called.

  Next, another embodiment of the present invention will be described.

  FIG. 5 is a top view schematically showing the configuration of the memory mat provided in the semiconductor device according to the second embodiment of the present invention.

  Compared with the memory mat 101 shown in FIG. 2, the memory mat 101A shown in FIG. 5 has an outermost peripheral capacitor pad 204A instead of the outermost peripheral capacitor pad 204A. It is different.

  The outermost peripheral compad 204A has a wider width than the outermost peripheral compad 204, and the outermost peripheral compad 204A has a width corresponding to a plurality of columns in the outermost peripheral portion as well as the one in the outer peripheral portion of the outer peripheral portion in the Y direction. In FIG. 4, it is formed so as to cover the container capacitors 202 (for two rows). In this case, all the capacitor capacitors 202 covered by the outermost peripheral capacitor pad 204 become dummy capacitor capacitors 202A, and all of the second capacitors 203B are formed in contact with the outermost peripheral capacitor pad.

  Therefore, a plurality of second capacitors 203B are formed side by side in the Y direction from the peripheral circuit 102 (specifically, the sense amplifier 104) toward the main body 200. For this reason, it becomes possible to more reliably prevent the solution from seeping out into the peripheral circuit through the interlayer oxide film 211.

  As described above, the semiconductor device according to the present embodiment is configured by arranging a plurality of second capacitors (202B) in the direction from the peripheral circuit (102) toward the main body (200).

  FIG. 6 is a top view schematically showing the configuration of the memory mat provided in the semiconductor device according to the third embodiment of the present invention.

  The memory mat 101B shown in FIG. 6 differs from the memory mat 101 shown in FIG. 2 in that it has an outermost peripheral compad 204B instead of the outermost peripheral compad 204.

  The outermost peripheral conpad 204B has a shape in which both ends of the outermost peripheral conpad 204 are bent in the Y direction toward the side opposite to the side toward the peripheral circuit 102 (specifically, the sense amplifier 104). The outermost peripheral conpad 204B may have a shape in which at least one end of the outermost peripheral conpad 204 is bent in the Y direction.

  When there is a large amount of the solution used for wet etching to the interlayer oxide film 211, the solution may ooze out from the corner of the memory mat 101B to the sub word driver 103. In this embodiment, the outermost peripheral compad 204B Is bent in the Y direction toward the opposite side to the sense amplifier 104, so that even when the solution oozes into the interlayer oxide film 211, the solution of the solution to the subword driver 103 can be prevented. It becomes possible.

  As described above, the semiconductor device according to the present embodiment is configured such that at least one end of the conductive film (204) is bent in the first direction to the side opposite to the peripheral circuit (102).

  FIG. 7 is a top view schematically showing the configuration of the memory mat provided in the semiconductor device according to the fourth embodiment of the present invention.

  The memory mat 101C shown in FIG. 7 is different from the memory mat 101 shown in FIG. 2 in that it has an outermost peripheral compad 204C instead of the outermost peripheral compad 204.

  The outermost peripheral conpad 204C is formed not only in the Y direction but also in the X direction so as to surround the main body 200. For this reason, it becomes possible to more reliably prevent the solution from seeping out in the X direction, that is, the sub word driver 103.

  As described above, the semiconductor device of the present embodiment is configured by forming the conductive film (204C) so as to surround the main body (200).

  10A and 10B are diagrams showing a configuration of a memory cell provided in the semiconductor device according to the fifth embodiment of the present invention. Specifically, FIG. 10A is a diagram showing an example of the memory mat 101 and the peripheral circuit 102 of the present embodiment, and FIG. 10B is an enlarged view of the region R shown in FIG. 10A. However, in FIG. 10B, the region R shown in FIG. 10A is rotated 90 ° clockwise. The configuration shown in FIG. 10A has the same configuration as the configuration shown in FIG.

  As shown on the left side of FIG. 10B, in the memory mat 101, the active region 11 in which the memory element is formed is formed obliquely with respect to the X and Y directions, the word line 12 is formed in the X direction, and the bit line 13 is formed in the Y direction. A capacitor capacitor 14 is formed in each of the active regions 11, and a capacitor is formed on the capacitor capacitor 14. Note that the region R includes a dummy capacitor which is a capacitor located at the outermost peripheral portion of the memory mat 101 (that is, the boundary between the memory mat 101 and the peripheral circuit 102). A bit contact 13A, which is a bit contact layer (Poly-Si), is formed under the bit line 13.

  10B shows a part of the peripheral circuit region in which the peripheral circuit 102 (specifically, the sense amplifier circuit 104) is formed. The peripheral circuit region includes a gate. (Hereinafter referred to as peripheral gate 15) and a contact layer (hereinafter referred to as peripheral capacitor 16) are formed.

  Hereinafter, a method for forming a memory cell having the memory mat 101 and the peripheral circuit 102 shown in FIG. 10B will be described with reference to FIGS. In FIGS. 11 to 23 below, (a) is a diagram showing a cross section along the line AA ′ in FIG. 10B, and (b) is along the line BB ′ in FIG. 10B. It is a figure which shows a cross section, (c) is a figure which shows the cross section along CC 'line of FIG. 10B.

  First, as shown in FIG. 11, the capacitor capacitor 14 is formed on the cell region where the memory mat 101 is formed, and the peripheral capacitor 16 is formed on the peripheral circuit region.

  The formation method up to the configuration shown in FIG. 11 will be briefly described. First, active regions are periodically formed on a silicon substrate (Si-sub) 21, and these active regions are formed by STI (Shallow Trench Isolation) method. A silicon oxide film (SiO 2) 22 is buried in between. Further, ions are implanted into the silicon substrate.

  Subsequently, a trench for a buried word line is formed in the active region, and the trench is filled with a gate insulating film (Gate-Ox) 23, a diffusion barrier material (TiN) 24, and a gate electrode material (W) 25. A buried word line is formed. Then, ions are implanted again into the silicon substrate 21, and then the trench is completely covered with the silicon nitride film (SiN) 26, and the silicon substrate 21 is completely covered with the silicon oxide film (SiO 2) 27.

  Then, a bit capacitor 13A is formed at a position sandwiched between two word lines in the active region, and then a bit line 13 is formed in the cell region, and a peripheral gate 15 is formed in the peripheral circuit region. After ions are implanted into the gates of the peripheral circuits, a polysilicon layer (Poly-Si) 29 and a diffusion barrier layer (TiN) are formed in the cell region through the silicon nitride film 28 between the bit lines 13 on the bit capacitor. A capacitor capacitor 14 composed of 30 and a tungsten layer (W) 31 is formed, and a peripheral capacitor 16 is formed in the peripheral circuit region. The space between the capacitor capacitors 14 is filled with a silicon nitride film 32. The peripheral capacitor 16 is formed adjacent to the peripheral gate 15 through a sidewall insulating film, and is connected to a diffusion layer (specifically, a source diffusion layer or a drain diffusion layer) 33.

  Note that the detailed configuration of each part of the peripheral circuit region is not directly related to the invention and is omitted, but FIG. 11 shows materials and the like of each part of the peripheral circuit region.

  When the memory cell shown in FIG. 11 is formed as described above, next, as shown in FIG. 12, a 10 nm tungsten nitride film (WN) 51 and a 40 nm film are formed on the memory cell by sputtering. A tungsten film (W) 52 is formed.

  Thereafter, as shown in FIG. 13, a photoresist (PR) 53 is applied on the tungsten film 52, and with respect to the photoresist 53, the upper part of the capacitor 14 in the outermost peripheral portion of the cell region and the periphery of the peripheral circuit region. Patterning using exposure is performed so that the photoresist 53 remains on the top of the capacitor 16. Further, the tungsten film 52 and the tungsten nitride film 51 are etched by plasma dry etching using the photoresist 53 as a mask. Thus, the outermost peripheral capacitor pad that covers the dummy capacitor that is the outermost capacitor is formed of the tungsten film 52 and the tungsten nitride film (WN) 51. In the peripheral circuit region, wiring connected to the peripheral capacitor 16 is formed. Here, the outermost peripheral compad is formed with a width that covers one row of the outermost peripheral capacitors in correspondence with the first embodiment.

  Subsequently, as shown in FIG. 14, the photoresist 53 is removed, and then nitridation of 30 nm is performed on the memory cell at a temperature of 500 ° C. to 600 ° C. by an atomic layer deposition (ALD) method. A silicon film (SiN) 54 is formed. As a result, the surface of the outermost peripheral conpad is completely covered with the silicon nitride film 54.

  Further, as shown in FIG. 15, a silicon oxide film (SiO 2) 55 is deposited on the silicon nitride film 54 by 1600 nm by plasma CVD (PECVD: Plasma-Enhanced Chemical Vapor Deposition). Then, a silicon nitride film (SiN) 56 of 80 nm is deposited on the silicon oxide film 55 at a temperature of 500 ° C. to 600 ° C. by atomic layer deposition. Instead of the silicon oxide film 55, another oxide film such as BPSG (Boron Phosphorus Silicon Glass) may be used. A plurality of types of oxide films may be stacked depending on the application.

  Thereafter, as shown in FIG. 16, the silicon nitride film 54, the silicon oxide film 55, and the silicon nitride film 56 are formed by lithography on the silicon nitride film 54, the silicon oxide film 55, and the silicon nitride film 56, using an amorphous carbon (not shown) as a mask. The etching used is applied. As the mask, a material that can secure a selection ratio between an oxide film and a nitride film, such as amorphous silicon, can be used instead of amorphous carbon. For patterning the mask, a multi-patterning method in which a single pattern is formed by performing lithography twice or more may be used.

  Subsequently, as shown in FIG. 17, a titanium nitride film (TiN) 57 for a capacitor lower electrode is formed to 8 nm at a temperature of 400 ° C. by an atomic layer deposition method.

  Further, as shown in FIG. 18, an 80 nm silicon oxide film (SiO 2) 58 is formed on the titanium nitride film 57 by a low pressure chemical vapor deposition (LPCVD) method. Thereby, in the description of FIG. 16, the hole opened by etching is completely filled.

  Thereafter, as shown in FIG. 19, a photoresist 59 is applied on the silicon oxide film 58, and the photoresist 59 is patterned by exposure so that the photoresist 59 remains in the cell region.

  Subsequently, as shown in FIG. 20, the silicon oxide film 58 and the titanium nitride film 57 are etched in this order using the photoresist 59 as a mask. Then, the photoresist 59 is removed, and the silicon oxide film 58, the silicon nitride film 56, and the titanium nitride film 57 are etched in this order. Further, a hole (not shown) for removing the silicon oxide film 55 using a wet etching method is opened in the silicon nitride film 56.

  Further, as shown in FIG. 21, the silicon oxide films 55 and 58 are removed by a wet etching method, specifically, a wet etching method using an etching solution containing buffered hydrofluoric acid. As a result, all the oxide films in the peripheral circuit region are removed.

  Subsequently, as shown in FIG. 22, a capacitor film 61 containing zirconia (ZrO 2) is deposited by 5 nm by an atomic layer deposition method. 62) is deposited 8 nm. Further, a silicon germanium (SiGe) film 63 is formed thereon by low pressure CVD, and a plate 64 formed of tungsten (W) is deposited by 100 nm by sputtering.

  Then, as shown in FIG. 23, a photoresist (not shown) is applied and exposed, and the capacitor film 61, the titanium nitride film 62, the silicon germanium film 63, and the tungsten film 64 in unnecessary portions are etched by an etching method. Removed.

  Thereafter, in order to form a DRAM, a contact for connecting the wiring to the plate 64 in the cell region and a contact for connecting to the tungsten wiring in the peripheral circuit region are formed. And the 1st thru | or 3rd wiring layer is formed on it, and those wiring layers are connected with said contact. These wiring layers are covered with an insulating film such as an oxide film or a polyimide film, whereby the pre-process before forming the DRAM is completed. As a wiring layer connected to the plate 64 in the cell region, laminated wiring of aluminum, titanium nitride and titanium is mainly used, but wiring using copper (Cu) having a lower resistance may be used.

  FIG. 24 is a diagram showing the outer periphery shown in FIG. 4 in more detail. Specifically, the peripheral circuit region (specifically, the sense amplifier 104) in the cell region of the memory cell formed as described above. FIG. 6 is a vertical cross-sectional view of a portion where one row of container capacitors 202 closest to the region) is formed as a dummy capacitor capacitor 202A. However, the longitudinal sectional view shown in FIG. 24 and the longitudinal sectional view shown in FIG. 4 are not sectional views in the same process.

  FIG. 25 is a diagram showing the outer periphery shown in FIG. 5 in more detail. Specifically, the peripheral circuit region (specifically, sense amplifier 104) in the cell region of the memory cell formed as described above. FIG. 6 is a vertical cross-sectional view of a location where two rows of container capacitors 202 closest to the region) are formed as dummy capacitor capacitors 202A. However, the longitudinal sectional view shown in FIG. 25 and the longitudinal sectional view shown in FIG. 5 are not sectional views in the same process.

  As described above, the method of manufacturing the semiconductor device according to the present embodiment includes the step of patterning the conductive film (204) and the predetermined wiring (221) in the peripheral circuit (104) using a single mask.

  FIG. 26 is a top view schematically showing the configuration of the memory mat provided in the semiconductor device according to the sixth embodiment of the present invention.

  The memory mat 101D shown in FIG. 26 is different from the memory mat 101 shown in FIG. 3 in that it further includes an outermost peripheral compad 204D. The outermost peripheral conpad 204D is formed along the Y direction between the memory mat 101D and the peripheral circuit 102 (specifically, the sub word driver 103). In addition, the outermost peripheral conpad 204 and the outermost peripheral conpad 204D are separated.

  According to this embodiment, similarly to the memory mat 101C described in the fourth embodiment (FIG. 7), it is possible to more reliably prevent the solution from oozing out to the sub word driver 103 side, and further, Even if a part of the outer peripheral volume conpads 204 and 204D is exposed to an acidic solution, the separation of the outermost peripheral volume conpads 204 and 204D can prevent the entire outermost peripheral volume conpad 204 from being lost. .

  As described above, the semiconductor device according to the present embodiment is formed between the first direction of the main body (200) and the peripheral circuit (102) along the second direction orthogonal to the first direction. A conductive film (204) and a second conductive film (204D) formed along the first direction between the main body part (200) and the peripheral circuit (102) in the second direction are configured. Thus, the first conductive film (204) and the second conductive film (204D) are separated.

  In each embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

DESCRIPTION OF SYMBOLS 100 Memory cell 101, 101A-101D Memory mat 102 Peripheral circuit 103 Subword driver 104 Sense amplifier 200 Main part 201 Bit line 201 Dummy bit line 202 Capacitor 202A Dummy capacitor 203 Capacitor 203A 1st capacitor 203B 2nd capacitor 204, 204A-204D Outermost circumference compad 221 M0 wiring

Claims (8)

A semiconductor device having a memory mat and a peripheral circuit formed around the memory mat,
The memory mat is
A main body having a first capacitor;
A linear conductive film formed between the main body and the peripheral circuit;
A second capacitor formed in contact with the conductive film and the bottom,
The first capacitor is a semiconductor device in which a contact layer and a bottom are in contact with each other. The main body has a bit line extending in a first direction in the plane of the memory mat,
2. The semiconductor device according to claim 1, wherein the conductive film is formed along a second direction orthogonal to the first direction between the first direction between the main body and the peripheral circuit.   3. The semiconductor device according to claim 2, further comprising a dummy bit line extending in the first direction between the main body portion and the peripheral circuit in the second direction.   4. The semiconductor device according to claim 2, wherein at least one end of the conductive film is bent in a direction opposite to a side toward the peripheral circuit in the first direction. 5.   The semiconductor device according to claim 1, wherein the conductive film is formed so as to surround the main body portion. The conductive film
A first conductive film formed along a second direction perpendicular to the first direction between the main body portion and the peripheral circuit in a first direction;
A second conductive film formed along the first direction between the main body portion and the peripheral circuit in the second direction;
The semiconductor device according to claim 1, wherein the first conductive film and the second conductive film are separated.   The semiconductor device according to claim 1, wherein a plurality of the second capacitors are formed side by side in a direction from the peripheral circuit toward the main body. A method of manufacturing a semiconductor device according to any one of claims 1 to 7,
A method of manufacturing a semiconductor device, comprising a step of patterning the conductive film and a predetermined wiring in the peripheral circuit using a single mask.

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