JP2013242960A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read a memory cell at high speed by large current while preventing read disturbance of the memory cell using a spin injection magnetization reversal.SOLUTION: A semiconductor device comprises: a plurality of word lines WL; a plurality of bit lines BL; a plurality of memory cells MC; readout circuits SA and LA which read information from selected memory cells; and rewriting circuits WD1 and WD2 which perform rewriting to the selected memory cells on the basis of the information which the readout circuits SA and LA read. Periods when the readout circuits SA and LA read the information from the selected memory cells are shorter than periods when the rewriting circuits WD1 and WD2 write the information in the selected memory cells on the basis of the information which the readout circuits SA and LA have read.

Description

  The present invention relates to a semiconductor device, and more particularly to a high-speed read method or a read disturb-free method in a memory cell array using magnetoresistance change.

  Among non-volatile memories, MRAM (Magnetic Resistive Random Access Memory) and SPRAM (Spin Transfer Torque RAM, spin injection RAM), which use magnetoresistive changes, are capable of high-speed operation and are practically infinite. As a rewritable nonvolatile RAM.

  As shown in the circuit diagram of FIG. 60A, the SPRAM cell shown in Non-Patent Document 1 and Non-Patent Document 2 includes one tunnel magnetoresistive element TMR, a select transistor MCT, a word line WL, a bit line BL, It consists of a source line SL. FIG. 60B shows an example of the cross-sectional structure. As shown in FIG. 61, tunnel magnetoresistive element TMR has at least two magnetic layers, one is fixed layer PL in which the spin direction is fixed, and the other is spin direction with respect to the fixed layer. The free layer FL has two states, a parallel state and an antiparallel state. There is a tunnel barrier film TB between these films. Information is stored in the direction of the spin of the free layer. In the antiparallel state (AP) with respect to the fixed layer of FIG. 61A, the electric resistance of the tunnel magnetoresistive element becomes a high resistance state, and FIG. In the parallel state (P) of b), the low resistance state is obtained. This is assigned to information “0” and “1”. In the read operation, the magnitude of the resistance of the tunnel magnetoresistive element TMR is read to obtain stored information. In the rewrite operation, the spin direction of the free layer can be controlled by a current in a direction perpendicular to the direction in which the fixed layer PL, tunnel barrier film TB, and free layer FL are stacked.

  That is, when a current is passed from the fixed layer PL in the direction of the free layer FL, electrons having a spin in the direction that makes the magnetization direction of the layer opposite to the fixed layer PL mainly flow to the free layer FL. . For this reason, when the current value exceeds a certain threshold value, the magnetization directions of the fixed layer PL and the free layer FL become antiparallel. On the other hand, when a current flows in the direction from the free layer FL to the fixed layer PL, electrons having a spin in the same direction as the fixed layer PL flow mainly in the free layer FL. When this current value exceeds a certain threshold value, the magnetization directions of the fixed layer PL and the free layer FL become parallel. That is, in this memory, the information “0” and “1” can be written in the direction of current. When this method is used, the current (threshold) required for rewriting is proportional to the size of the tunnel magnetoresistive element TMR, so that the rewriting current can be reduced along with miniaturization, which is excellent in terms of scalability. MgO or the like is used as the tunnel barrier film TB.

  FIG. 13 of Patent Document 1 describes experimental results showing the relationship between the rewriting time and the rewriting current necessary at that time (FIG. 62 of this application shows FIG. 13 of Patent Document 1 (partial reference numerals). ))). According to FIG. 13 of Patent Document 1 (FIG. 62 of the present application), the tunnel magnetoresistive element TMR increases the current value necessary for rewriting when the rewriting time is shortened. Utilizing this property, the time of the current flowing through the tunnel magnetoresistive element TMR at the time of reading is set to t1, which is shorter than the time t2 of the current flowing through the tunnel magnetoresistive element TMR during the rewriting operation, and the current value is about the same as i1. Thus, Patent Document 1 discloses an invention that distinguishes reading / rewriting.

JP 2007-310949 A

2009 Symposium on VLSI Circuits, Digest of Technical Papers, pp.84-85, June 2009. IEEE Journal of Solid-State Circuits, Vol. 43, pp. 109-120, January 2008

  However, as scaling (miniaturization) progresses, the rewrite current decreases, which is a feature of this memory. At this time, a problem arises regarding the read current. That is, since the current flows through the tunnel magnetoresistive element during reading as well as during rewriting, the state of the memory cell is affected by this current. This is called a read disturb. The read disturb refers to a phenomenon in which a weak rewrite operation occurs in a read operation and the written data changes or changes to an unstable state that is easily changed even if it does not change. In order to avoid this, the read current is generally set sufficiently lower than the rewrite current.

  However, the ability to reduce the write current as scaling progresses means that the read current also decreases. That is, as scaling progresses, the current required for rewriting shifts downward as a whole as shown in FIG. 62 (shifts from curve (a) to curve (b)). At this time, if the reading / rewriting is distinguished by the rewriting time as in Patent Document 1, it is necessary to sufficiently shorten the time t1 to t1 'or to sufficiently reduce the reading current i1 to i1'. However, shortening the time may not be realized due to the characteristics of the transistors in the driver circuit. On the other hand, reducing the read current has a problem that high-speed reading becomes difficult. It is necessary to solve this problem in order to take advantage of the feature of this memory element that is excellent in scalability.

  Representative means shown in the present invention are as follows. A plurality of word lines; a plurality of bit lines wired in a direction orthogonal to the plurality of word lines; and a plurality of memory cells disposed at predetermined intersections of the plurality of word lines and the plurality of bit lines; A read circuit that reads information from a selected memory cell among the plurality of memory cells, and a rewrite circuit that rewrites the selected memory cell based on information read by the read circuit, Each of the plurality of memory cells includes a tunnel magnetoresistive element in which a tunnel film, a fixed layer, and a free layer are stacked, a gate connected to a corresponding one of the plurality of word lines, and a drain connected to the tunnel A MOSFET connected to the fixed layer side of the magnetoresistive element, and the free layer side of the tunnel magnetoresistive element corresponds to the plurality of bit lines. The fixed layer is disposed adjacent to the tunnel film, the direction of electron spin is fixed in a predetermined direction, and the free layer faces the surface of the tunnel film adjacent to the fixed layer. Adjacent to each other in a plane, the direction of electron spin is either parallel or anti-parallel to the fixed layer, and the read circuit reads the information from the selected memory cell while the read circuit reads information from the selected memory cell. The period is shorter than a period of writing information to the selected memory cell based on information read by the circuit.

  The effect of read disturb is significantly reduced. Further, the current required for rewriting depends on the pulse width. Therefore, a read operation can be performed without changing the TMR state if the pulse width is short, that is, if the pulse application time is short. For this reason, high-speed reading is possible even if the rewrite current is reduced by scaling. As a result, high-speed reading is possible even if the rewrite current is reduced by scaling.

1 is a schematic circuit block diagram showing a first embodiment of the present invention. FIG. 3 is a first operation example of the circuit block diagram of FIG. 1. FIG. FIG. 3 is a first operation example of the circuit block diagram of FIG. 1. FIG. FIG. 6 is a second operation example of the circuit block diagram of FIG. 1. FIG. FIG. 6 is a second operation example of the circuit block diagram of FIG. 1. FIG. FIG. 6 is a third operation example of the circuit block diagram of FIG. 1. FIG. FIG. 6 is a third operation example of the circuit block diagram of FIG. 1. FIG. FIG. 2 is a detailed circuit diagram of the circuit block diagram of FIG. 1. 6 is an operation example of the circuit diagram of FIG. 5. It is a schematic diagram of the experimental result of the time change of the resistance of a memory cell when the Example of this invention is used. It is the figure which added the electric current and time corresponding to the operation | movement of FIG. 2 to the schematic diagram of an experimental result. It is a schematic diagram of the other experiment result using the Example of this invention. It is the figure which added the electric current and time corresponding to the operation | movement of FIG. 2 to the schematic diagram of the experimental result which considered temperature. It is a figure explaining the Example of this invention for every generation of a transistor or a refinement | miniaturization process rule. It is a figure explaining the other Example of this invention for every generation of a transistor or a refinement | miniaturization process rule. It is a schematic circuit block diagram which shows the 2nd Example of this invention. It is a schematic circuit block diagram which shows the 3rd Example of this invention. FIG. 15 is an operation example of the circuit block diagram of FIG. 14. FIG. FIG. 15 is an operation example of the circuit block diagram of FIG. 14. FIG. It is a schematic circuit block diagram which shows the 4th Example of this invention. FIG. 17 is an operation example of the circuit block diagram of FIG. 16. FIG. It is a schematic circuit block diagram which shows the 5th Example of this invention. FIG. 19 is an operation example of the circuit block diagram of FIG. 18. FIG. It is a figure which shows the memory cell array applied in the 1st Example to the 5th Example of this invention. FIG. 21 is a diagram showing a chip control circuit for controlling the memory cell array of FIG. 20. It is the operation example of FIG. It is a figure which shows the example of a cross-section of a memory cell array applied to the 1st Example to the 5th Example of this invention, and a circuit diagram. It is a figure which shows the other cross-sectional structure example and circuit diagram of the memory cell array applied to the 1st Example to the 5th Example of this invention. It is a figure which shows the structural example of a TMR element part. It is a figure which shows the other structural example of a TMR element part. It is a figure which shows the example of a layout of a memory cell array. It is a figure which shows sectional drawing between A-A 'of FIG. 27, and sectional drawing of a peripheral circuit. It is a figure which shows sectional drawing between B-B 'of FIG. 27, and sectional drawing between C-C'. It is a figure which shows the other cross-sectional structure example of a memory cell array. FIG. 31 is a diagram showing an example of a plan view of the memory cell array of FIG. 30. It is a figure which shows the temperature characteristic example of a TMR element resistance-current characteristic. It is a figure which shows the temperature characteristic example of a TMR element resistance. It is a figure which shows the implementation | achievement method of the reference cell which implement | achieves Vref used for read-out operation. It is a figure which shows the operation example of FIG. It is a figure which shows the example of a cross-section of a memory cell and a peripheral circuit. It is a figure which shows the other cross-sectional structure example of a memory cell and a peripheral circuit. It is a figure which shows the example of a processor system using this invention. It is a figure which shows the structural example of SP-FF which is a flip-flop which has a TMR element. It is a figure which shows the operation example of FIG. It is a figure which shows the example of an internal power generation circuit used in the cross-section structure example and the processor system example. It is a figure which shows the other example of the processor system using this invention. FIG. 43 is a diagram illustrating an operation example of FIG. 42. It is a figure which shows the switch element circuit example at the time of comprising a variable logic unit. It is a figure which shows the operation example of FIG. It is a figure which shows the example of a switch element circuit symbol. It is a figure which shows a TMR switch array example. It is a figure which shows the example of AND-OR surface using a TMR switch. It is a figure which shows the 1st structural example of a variable logic unit. It is a figure which shows the 2nd structural example of a variable logic unit. It is a figure which shows the 3rd structural example of a variable logic unit. It is a figure which shows the 4th structural example of a variable logic unit. It is a figure which shows the variable logic unit operation example. 1 is a diagram illustrating an example of an LSI system. It is a figure which shows the example of a portable device system. It is a figure which shows the board system example. It is a figure which shows the example of a multichip package. It is a figure which shows the example of a network processor. It is a figure which shows the example of a computing structure comparison. Conventional structure example Example of TMR element configuration with conventional structure It is the figure which showed FIG. 13 of patent document 1, and the subject.

  A first embodiment of the present invention will be described with reference to FIGS. 1 and 2A and 2B. First, the configuration of this embodiment will be described with reference to FIG. The memory cell MC of the main part of the memory cell array includes a selection transistor (MOSFET) MCT and a variable resistance element TMR that takes different resistances according to stored information. These are arranged in series between the bit line BL and the source line SL, and the MCT is controlled by the word line WL. SA is a sense amplifier connected to the bit line BL, and the SA activation signal is SAE. The sense amplifier SA compares the reference voltage Vref and the voltage of the bit line BL, and amplifies the voltage difference. IO is a signal that conveys the result of amplifying a signal read to the bit line BL described later with SA to a circuit that outputs the result to the outside of the chip or the memory block via the switch S1 controlled by the column selection signal YS. In addition, it is a signal for transmitting a signal to be written to the memory cell to SA via S1 controlled by YS.

  LA is a latch circuit that latches the SAO signal to which the result of the signal amplified by SA or taken in from IO is output. The outputs of LA are LA1 and LA2, and are generally complementary signals. This is input to the write drivers WD1 and WD2. WD1 and WD2 are activated by a write activation signal WE. WD1 drives the bit line BL, and WD2 drives the source line SL, which controls the direction and magnitude of the current flowing through the memory cell MC during rewriting. As will be described later, when the direction of the current at the time of reading is such that the disturb is not given to the write signal at that time, there is an operation in which rewriting is not performed.

  2A and 2B show an operation example of the present invention. This is an example of performing a rewrite operation together with a read operation. In the signal of the word line WL, the low level is 0 and the high level is V1. During the rewrite operation, both the bit line BL and the source line SL have a low level of 0 and a high level of V1. The V1 is the same for the three signal lines here, but may be different. For example, the high level of the word line WL may be higher than other bit lines BL and source lines. In addition, the precharge voltage of the bit line at the time of the read operation is V2, which is a potential lower than V1 here. As described in the conventional example, the writing of information “0” and “1” is performed according to the direction of current. First, FIG. 2A shows an example in which the TMR state of the memory cell to be read is antiparallel and has a high resistance. The bit line is precharged to V2, and the source line SL remains at 0. When this cell is selected, the word line WL goes from 0 to V1. As a result, the memory cell information is read out to the bit line. After a certain time t1, SAE is switched from 0 to V1, the sense amplifier SA is activated, and the read signal is amplified. At this time, since the resistance of the memory cell is high, the potential of the bit line is higher than the reference signal voltage Vref. For this reason, in this example, the SAO has a high level V1 and is latched by the latch circuit LA. The sum of the time during which reading is performed, the amplification by t1 and SA, and the time until latching by LA is shorter than the rewrite time, for example, 10 ns.

  When the read signal is latched by the latch circuit LA, YS is selected, the switch S1 controlled by this is turned on, and the read signal is transmitted to the IO. In parallel, LA1 and LA2 which are complementary outputs of LA are at the high level V1 and LA2 remains 0 as shown in the figure. Here, the activation signal WE of the write drivers WD1 and WD2 becomes the high level V1, and a signal for writing the same signal as the read signal is applied to the bit line BL and the source line SL. That is, the bit line BL becomes 0, and the source line SL becomes the high level V1. As a result, a current flows from the source line SL to the bit line BL, and the TMR state is rewritten to the state before reading. As a result, the disturbance given at the time of reading is reset.

  Thus, the present invention is characterized in that since the same information as the read signal is written thereafter, the disturb at the time of reading is reset and the memory cell becomes stable. In addition, after being taken in by the sense amplifier, even if the information in the memory cell is destroyed by the read current, rewriting is performed in the present invention, so that the original information is not lost. Therefore, there is no need to provide a read current margin for preventing rewriting, and it is possible to perform reading with a relatively large current and to perform reading at high speed.

  FIG. 2B shows a case where the read signal is the reverse of FIG. 2A. Similarly, the bit line BL is precharged to V2 and the word line WL is selected to start reading, but here the TMR state in the memory cell is a parallel state and its resistance value is small. Therefore, after a certain time t1, the potential of the bit line BL is lower than the reference signal voltage Vref. This is amplified by the sense amplifier SA, the result is transmitted to the latch LA, and the rewrite drivers WD1 and WD2 operate based on this information. That is, when WE is switched, the bit line BL is driven to the high level V1 and the source line SL is driven to 0. As a result, a current flows from the bit line BL to the source line SL, and the TMR state is rewritten to the state at the time of reading. After reading, YS is selected as described with reference to FIG. 2A, the switch S1 controlled by this is turned on, and the read signal is transmitted to the IO. Features are the same as in FIG. 2A. The disturb given at the time of reading is reset.

  Thus, in the present invention, reading can be performed with a relatively large current. Note that according to the TMR structure, the direction of current at the time of rewriting, that is, the potential relationship between the bit line BL and the source line SL may be opposite to that of the present embodiment.

  3A and 3B show an example of writing operation. In this example, the IO signal is taken into the sense amplifier SA via the switch S1 controlled by YS, latched by the latch circuit LA, and the write drivers WD1 and WD2 are driven according to the output of the latch circuit LA. Thus, a signal is written to the memory cell. FIGS. 3A and 3B are examples corresponding to different IO signals depending on the information “1” and “0” written in the memory cell. In FIG. 3A, for example, when writing “0”, at this time, the IO signal when the signal is taken in by the switch S1 is V1. When this signal is input to the sense amplifier SA and the SA is activated by the SAE signal, a corresponding signal appears in the SAO. This signal is latched by the latch circuit LA, and corresponding outputs appear at LA1 and LA2. That is, LA1 is V1 and LA2 is 0. At the same time, the WE is switched and the write drivers WD1 and WD2 operate to drive the bit line BL and the source line SL and write information into the memory cell. The source line SL is V1, and the bit line BL is 0. FIG. 3B shows the writing of “1”. At this time, the IO signal when the signal is taken in by the switch S1 is 0. This signal is amplified by the sense amplifier SA and taken into the latch circuit LA, and gives the opposite polarity to LA1 and LA2 as shown in FIG. 3A. That is, LA1 is now 0 and LA2 is V1. Correspondingly, the source line SL becomes 0 and the bit line BL becomes V1, whereby information is written in the memory cell.

  4A and 4B show another example of the operation of the main part of the memory cell array of FIG. In this example, unlike the example of FIG. 2, the precharge voltage of the bit line BL is V1 like the voltage at the time of rewriting. As a result, the types of power supplies can be reduced. Further, a circuit for controlling the bit line BL can be simplified depending on the circuit configuration. Also in this embodiment, by shortening the time for supplying current to the memory cell at the time of reading, the write information can be read without destroying the information of the memory cell, and this is amplified by the sense amplifier SA, and the result is obtained. The voltage required for rewriting can be applied to the bit line BL and the source line SL by the latch LA and the write drivers WD1 and WD2. Note that the readout waveform of the signal to the IO line is omitted, but the readout by controlling S1 after the readout to the sense amplifier is the same as in FIG.

  4A and 4B differ in the information written in the memory cell, but the difference is sensed depending on whether the potential of the bit line is higher or lower than the reference signal voltage Vref after a certain time t1. They are common in that they are amplified by the amplifier SA, taken into the latch circuit LA, and driven by the write drivers WD1 and WD2. According to the present embodiment, although the number of power supplies is small, reading is performed with a short pulse width or application time and rewriting is performed, so that reading can be performed with a relatively large current. Further, since the same information as the read signal is written thereafter, the disturb at the time of reading is reset, and the memory cell is in a stable state. Similar to the example of FIG. 2, after being taken into the sense amplifier, even if the information in the memory cell is destroyed by the read current, rewriting is performed, so that the original information is not lost.

  1 to 4 together, it is possible to read out with a relatively large current by performing reading and rewriting with a short pulse width or application time, and further disturbing at the time of reading is The memory cell is reset and is in a stable state. Therefore, even if the scaling progresses and the current required for rewriting decreases, high-speed reading is possible with a relatively large current, and reading and rewriting can be controlled by changing only the time with the same current value. Control is also simple.

  FIG. 5 is a diagram showing a circuit configuration example of the block diagram shown in FIG. Here, only the periphery of the memory cell is shown. Between the bit lines BLL and BLR and the source lines SLL and SLR, memory cells SLC1 and SCR1 driven by the word lines WL1 and WR1 by the word driver are arranged. Actually, a large number of memory cells, such as 512, are arranged for a set of bit lines and source lines, and a large number of bit line / source line pairs each having such a large number of memory cells are arranged on the chip. DCL and DCR are dummy memory cells, which are driven by dummy word lines DWL and DWR by a word driver, and the currents flow in two states corresponding to information “0” and “1” that can be taken by the memory cells. In the example of this figure, DCG is controlled so as to be in the middle of the current value. The DCG voltage may have a temperature characteristic so that the dummy memory cells DCL and DCR have a temperature characteristic that follows the temperature characteristic of the TMR element. As will be described later, the dummy memory cell can also be configured using a memory cell storing “1” information and a cell storing “0” information.

  PC is a precharge signal. By this signal, the bit lines BLL and BLR are precharged to Vdd, and the input portion of the sense amplifier SA is precharged to Vdd 'via a precharge MOSFET. RE is a signal for connecting the bit lines BLL and BLR and the sense amplifier SA at the time of reading, and controls the reading MOSFET. The sense amplifier SA is activated by the signal SAE. The output is SAO, which in this embodiment is connected to a latch circuit LA that also serves as the load resistance of the sense amplifier SA. The latch circuit LA also has a function of further amplifying the signal difference detected by the sense amplifier SA. The output result of the sense amplifier is connected to the IO lines IOR and IOL in the chip via the MOS selected by the selection signal YS, and the read result is transmitted to the IO line.

  These precharge MOSFET, read MOSFET, sense amplifier SA, and latch circuit LA constitute a read circuit. Note that various specific implementation methods of the read circuit are conceivable, but in short, the read circuit only needs to read information by flowing a current through a selected memory cell.

  Next, WE is an activation signal for the rewrite drivers WD1R, WD2R, WD1L, and WD2L to which the output of the latch circuit LA is connected. The output of the rewrite driver is electrically connected to the bit lines BLL and BLR and the source lines SLL and SLR for rewriting by a MOSFET controlled by WEL and WER (may be regarded as a part of the rewrite driver). Is done. This is also used for normal writing. These rewrite drivers WD1R, WD2R, WD1L, WD2L, and MOSFETs controlled by WER, WEL constitute a rewrite circuit. The rewrite circuit can be realized in various specific ways. In short, the direction of the current flowing in the memory cell (tunnel magnetoresistive element) when writing “0” and when writing “1”. As long as it can be changed. In this figure, a MOS transistor that lowers the source line controlled by DCS and a MOS transistor that lowers the bit line controlled by DCB are arranged.

  In FIG. 1, the data at the time of rewriting is input from the IO line to the sense amplifier SA and then input to the latch circuit LA. However, in FIG. 5, the latch circuit LA is detected by the sense amplifier SA. Since it also functions to further amplify the signal difference, the data at the time of rewriting is input directly from the IO line to the latch circuit LA.

  FIG. 6 is a diagram illustrating an operation example of the circuit of FIG. First, reading is performed. When PC changes from high level to low level, DCB changes from high level to low level, and RE rises, word line WR1 is selected. At the same time, the dummy word line DWL paired with this is selected. Thereby, a change corresponding to the information of the memory cell appears on the bit line BLR, and a change (dotted line) corresponding to the cell of the dummy memory appears on the BLL. Here, a large amplitude signal is generated in LA1 and LA2 by changing the SAE to activate the sense amplifier SA and transmitting the result to the latch circuit LA. Since the signal of the memory cell is read to the sense amplifier, RE may return to the original level and the bit line may be disconnected from the sense amplifier. Since SAE is also necessary for holding the state of the latch circuit LA, it is held at a high level. Thereafter, YS is selected, and this read signal is transmitted to the IO lines IOR and IOL. Since reading has already been completed in this state, the word line WR1 and the dummy word line DWL are closed, and the DCB is returned to the original level. In the embodiments so far, the word line is kept open and rewriting is performed. However, the word line may be once closed in this way in order not to pass an unnecessary current. An operation with the word line open may be possible although DCS and DCB may be controlled independently on the left and right sides. Next, rewriting is started. The operation of selecting YS and transmitting the read signal to the IO line can be performed in parallel with the rewrite operation, thereby hiding the rewrite time.

  In rewriting, first, DCS and DCB are set to a low level. Here, WE and WER are changed. Thereby, the information in the latch LA is connected to the bit line BLR and the source line SLR, and the potential relationship between the bit line BLR and the source line SLR is determined according to the rewrite information. At the same time, the word line WR1 is selected and writing starts. When writing is completed, the word line WR1 is closed, WE and WER are restored, and PC, DCS, and DCB are restored. Return SAE and YS at an appropriate time. By such an operation example, the reading and rewriting operations according to the present invention are completed.

  FIG. 7 shows an example of a schematic diagram of the experimental result of the time change of the resistance of the memory cell when the embodiment of the present invention is used. When TMR is in a parallel state and takes a low resistance, its resistance value is R1, and when TMR is in an anti-parallel state and takes a high resistance, its resistance value is R2. The current is written in the opposite state to the written state, and the time change of the resistance is plotted. If this current is applied for a sufficient period of time, then if a long pulse is applied, the TMR state is reversed, that is, a value that can be written. In the upper diagram of FIG. 7, the TMR is in a parallel state, and when a current is applied at t0, the resistor R1 is shown. The resistance value does not change until time t1.

  That is, at the time interval t1-t0, the current value required for rewriting is large and writing is difficult to occur. In the present invention, reading is performed using this period. Next, the current continues to be applied until time t2. Then, rewriting occurs at any point between t1 and t2, and the resistance value changes to R2. The time point between t1 and t2 changes depending on the thermal stability and ambient temperature, which are the characteristics of TMR, but does not change in the time width (pulse width) of t1-t0, that is, it is not rewritten. However, it continues to be applied until t2 and is rewritten in the time width (pulse width) of t2-t0.

  The present invention utilizes this phenomenon. The lower diagram in FIG. 7 shows a case where TMR is in an antiparallel state, and shows resistance R2 when current is applied at t0. Similarly, it does not change with the time width and pulse width of t1-t0, but it is rewritten with the time width and pulse width of t2-t0. As shown in the figure, the time that does not change is different depending on whether the initial state is the parallel state or the anti-parallel state, but it does not change in the time width of t1-t0 that satisfies both, but it is written in the time width of t2-t0. The condition of changing can be easily found. In particular, since rewriting is performed, it is not necessary to take a margin between t1 and the rewriting phase.

  FIG. 8 is an example in which the current and time corresponding to the operation of FIG. 2 of the present invention are added to the schematic diagram of the experimental results. Reading corresponds to a point p, and the current is i1 and the time is t1. Rewriting corresponds to the point q, and the current is i2 and the time is t2. The read point p is a characteristic in which rewriting occurs (a), and the time is short and the current is sufficiently small. However, the current is not greatly reduced for the rewrite point q. It is about 60% to 40%. By taking in this way, high-speed reading can be performed without greatly reducing the read current, and read information necessary for subsequent rewriting can be obtained.

  FIG. 9 shows an example of a schematic diagram of another experimental result using the embodiment of the present invention. This is when the temperature is changed. The horizontal axis represents the time for flowing current, that is, the pulse width, and the vertical axis represents the current flowing through the memory cell. Here, two curves (a) and (b) indicated by solid lines indicate the pulse width and the necessary current value required for rewriting the memory cell used in the present invention at low and high temperatures, respectively (drawing). For convenience, it is a polygonal line, but this is a smooth curve that generally shows the same tendency).

  These are characteristics common to the TMR element structure shown in the conventional example and various modifications thereof. (A) is at a low temperature, and (b) is at a high temperature. With the same pulse width, the current value is larger at a low temperature than at a high temperature. The low temperature is, for example, the same or lower temperature as the minimum temperature guaranteed in the product specification, and the high temperature is the same or higher temperature as the maximum temperature guaranteed in the product specification. In both curves, the required current value increases as the pulse width decreases. This increase becomes significant when the pulse width is 10 ns or less, for example.

  For a memory cell having such characteristics, the present invention is characterized by an operation based on the following concept. First, a method of performing the same current value i1 in the memory cell for reading and rewriting, that is, a method of the embodiment of FIG. 4 will be described. This current value is larger than the necessary rewriting current at a low temperature at the writing time t2. A lower rewrite current is required at a lower temperature than at a higher temperature. Therefore, if the current value i1 is the application time t2 at the time of rewriting, the rewriting can be reliably performed at any temperature. This is the first feature. As a second feature, at the current value i1, the read pulse width t1 is set to a short pulse width at which rewriting does not occur in the rewriting characteristics indicated by the curve (b) at high temperature. Rewriting is less likely to occur at lower temperatures than at higher temperatures. As a result, stable reading can be performed at any temperature. Such a setting is characterized in that a stable read + rewrite operation can be performed in the entire temperature range of the product specification, and a highly reliable semiconductor memory device with stable operation can be realized.

  FIG. 10 is an example in which the current and time corresponding to the operation of FIG. 2 of the present invention are added to the schematic diagram of the experimental result in consideration of the temperature. Reading corresponds to a point p, and the current is i1 and the time is t1. As a result, it is possible to perform sufficiently stable reading with respect to the characteristic (b) at a high temperature at which writing is likely to occur, that is, when reading is more unstable, and reading information necessary for subsequent rewriting can be obtained. it can. Rewriting corresponds to the point q, and the current is i2 and the time is t2. Thereby, a sufficient rewriting current can be supplied for the low temperature characteristic (a) which is difficult to write. From the above, as in this example, the current value (which can be controlled by the word line voltage and the bit line voltage. FIG. 2 shows an example in which the bit line voltage is changed without changing the word line voltage) and the application time are selected. For example, reading with a rewriting operation can be stably performed in a wide temperature range. As described above, when the operating temperature is taken into consideration, a more stable operation can be realized by reducing the writing and reading of the current value. By performing rewriting at this time, the margin of the read current can be reduced, so that the read current at a high temperature can be increased.

  FIG. 11 is a diagram for explaining an embodiment of the present invention for each generation of transistors or miniaturization processing rules. In this figure, the horizontal axis indicates a processing rule for creating a memory element, or a minimum dimension. The processing rule becomes smaller as it goes to the right on the horizontal axis, that is, a state in which miniaturization and scaling have progressed. The vertical axis represents write and read currents. For example, in the rule of 90 nm, the planar dimension of the TMR element is set to 90 nm × 90 nm. The minimum dimension of the MOS transistor and the minimum dimension of the TMR element may be different. For example, even in a memory cell using a 45 nm rule MOS transistor, the planar dimension of the TMR element may be 90 nm × 90 nm. Or conversely, the processing rule of the TMR element may be more advanced than the processing rule of the MOS transistor.

  As shown in this figure, in the spin injection type RAM, the current required for writing decreases as the scaling progresses and the element becomes finer. On the other hand, the read current generally needs to be smaller than this in order to avoid read disturb. This figure shows an example in which a value that is about one digit smaller is selected. However, in this case, there is a problem that the value of the read current becomes too small in a region where the miniaturization progresses and the write current becomes small. This causes the same problem even if the read current is selected to be 1/3 of the write current, for example. Therefore, in the present invention, it is possible to avoid further lowering under the condition where the read current is not more than a certain value. As shown in FIGS. 7 to 10, the present invention makes use of the fact that the current required for rewriting depends on the application time, and that the read current can be increased by rewriting. Is due to.

  As shown in FIG. 12, the idea that the current values for reading and rewriting are exactly the same from the generation of a certain processing rule can be realized by the present invention. An example of the operation is as described in FIG.

  FIG. 13 is a diagram showing a second embodiment of the present invention. The idea of the present invention is to rewrite the memory cell that has been subjected to the read disturb and eliminate the influence of the read disturb. On the other hand, the direction in which the current flows during reading may not be disturbed for the state stored at that time. In general, reading is performed in one direction. For example, in a configuration in which a free layer is connected to the bit line side, it is assumed that reading is performed in the direction of current from the bit line to the source line, that is, from the free layer to the fixed layer. At this time, electrons flow from the fixed layer to the free layer, but according to the principle of the spin injection method, only electrons in a spin state having a function of making the free layer parallel to the fixed layer flow to the free layer. Therefore, if the originally stored state is a parallel state, no disturbance occurs in this reading. Therefore, there is no need to rewrite.

  In this embodiment, rewriting is not performed in such a case. By doing so, it is not necessary to drive the bit line or the source line by a rewrite driver necessary for rewriting, and the power can be reduced. For this purpose, in this embodiment, two systems of rewrite driver control signals are prepared. That is, the rewrite signal WE is used during normal rewrite operation, and the rewrite signal WERE is used during rewrite following read. When the rewrite signal WERE is input, writing does not occur in the direction corresponding to the read current direction. For example, in the above example, if reading is in the direction from the bit line to the source line, the operation may be performed so that the bit line is not set to the high level at the time of rewriting. If the read result indicates that the bit line is set to a high level when rewriting is performed and the source line is set to 0 V, that is, the direction from the bit line to the source line is the same as when reading, the bit line is set to a high level. Rewriting does not occur. On the other hand, when the read result indicates that the bit line is set to 0 V and the source line is set to the high level as rewriting, this voltage is applied as it is.

  Various specific circuit configurations can be considered. In accordance with the above-mentioned concept, logic is taken between WE and WERE, or only one side of the write driver is set in a predetermined read current direction, that is, in a condition in which no disturbance occurs. There is a simple circuit configuration to make it inactive. For example, when the reading is in the current direction from the bit line to the source line, the operation with the current in this direction becomes unnecessary at the time of rewriting. At this time, in the WD1R or WD1L rewrite mode of FIG. 5, the output of the WD1R or WD1L may always be at a low level even if the write operation starts with WE, WER, or WEL. If this signal is at a low level due to WERE, it is sufficient to add a logic that always outputs the output of WD1R or WD1L at a low level. There are various specific examples, but there is an example in which WD1R or WD1L is a three-input NAND + inverter, one of the three inputs is WERE, and one stage of the WD2R or WD2L inverter is two stages.

  Whether or not to rewrite can be determined for each bit of the memory cell to be read. Therefore, in this embodiment, the power at the time of rewriting can be reduced. In general, when the data pattern is time-averaged or averaged over a plurality of read bits, “1” and “0” can be regarded as being almost half at random. Therefore, in this case, since rewriting is performed only in half of the cells, the power in this portion is halved.

  FIG. 14 is a diagram showing a third embodiment of the present invention. As described above, even if WERE is selected, if disturb does not occur in the read current direction, a method in which the latch circuit does not output a write operation signal in that direction to the write driver can be used. 15A and 15B are examples of the operation of FIG. In this example, the direction of the current at the time of reading is a direction in which electrons having a spin in a direction in which the free layer in the TMR element is oriented in parallel with the fixed layer flows in the free layer. That is, when the read result is in a parallel state, this read does not disturb the TMR element of the read memory cell at all. Therefore, there is no need to rewrite.

  FIG. 15A assumes that the resistance of the memory cell is in a high resistance state. In the signal of the word line WL, the low level is 0 and the high level is V1. During the rewrite operation, both the bit line BL and the source line SL have a low level of 0 and a high level of V1. The bit line is precharged to V1, and the source line SL remains at 0. When this cell is selected, the word line WL goes from 0 to V1. As a result, the memory cell information is read out to the bit line. After a certain time t1, SAE is switched from 0 to V1, the sense amplifier SA is activated, and the read signal is amplified. At this time, since the resistance of the memory cell is high, the potential of the bit line is higher than the reference signal voltage Vref. The memory cell is disturbed by the read current while it is being read. The direction of the read current is a current in a direction in which the free layer is parallel to the fixed layer. However, since the free layer in the memory cell is antiparallel to the fixed layer (therefore, the resistance is high and the signal read to the bit line) Is higher than the reference signal voltage Vref). For this reason, in this example, the SAO has a high level V1 and is latched by the latch circuit LA. Here, the rewrite signal WERE at the time of rewriting rises. Here, since the direction is disturbed, LA1 becomes V1 and LA2 becomes 0, and the latch circuit performs rewriting in the antiparallel direction.

  On the other hand, FIG. 15B shows a case where the resistance of the memory cell is in a low resistance state, that is, the state of the free layer and the fixed layer of the TMR element is parallel. Here, after a certain time t1, the potential of the bit line is lower than the reference signal voltage Vref. At this time, the memory cell is not disturbed by the read current while it is being read. Therefore, rewriting is not necessary. SAE is switched from 0 to V1, the sense amplifier SA is activated and the read signal is amplified and becomes 0 at SAO, which is latched by the latch circuit LA. At this time, even if the rewrite signal WERE at the time of rewriting rises, both LA1 and LA2 remain 0. Therefore, there is a feature that rewriting is not performed and power for this is not consumed.

  As a specific circuit configuration example, a switch controlled by WIRE is provided at the output of the latch circuit LA, and a precharge circuit for setting the inputs of WD1 and WD2 to 0 is provided. In addition, when the BLR side is selected, the switch provided in LA1 is turned on, and when the BLL side is selected, the switch provided in LA2 is controlled to be turned on.

  FIG. 16 is a circuit diagram of a memory cell and related circuits showing a fourth embodiment of the present invention. Here, a selection transistor and a TMR element are arranged between the bit line BL and the common source line CSL. A constant voltage of the common source line CSL is defined as VCSL. This embodiment is characterized in that the voltage of the common source line CSL is a constant voltage VCSL during read and rewrite operations. As a result, the drive circuit and the array structure can be simplified. FIG. 17 shows an operation example of the circuit of FIG. In the signal of the word line WL, the low level is 0 and the high level is V1. In both the bit line BL and the source line SL, the low level is 0, the high level is VB1 when reading, and V2 when writing. The VCSL is set to be between the low level 0 and the high level V1. Usually, it is half the voltage of V1.

  In the read operation of FIG. 17A, the bit line is precharged to V2 from the VCSL, and reading is performed when the word line WL is selected. Here, the TMR element in the memory cell is in an antiparallel state, and its resistance is high. Accordingly, the voltage of the bit line becomes higher than Vref, and the waveform is not shown here, but is amplified by the sense amplifier SA, read to IO, latched to LA, and re-similar to the description of the previous embodiments. Writing becomes possible. In the example of (a), the bit line is set to V1 by the write driver WD1, and the common source line CSL is VCSL. Therefore, a rewrite current for rewriting flows.

  On the other hand, FIG. 17B shows a case where information opposite to that shown in FIG. Here, the voltage of the bit line becomes lower than Vref by reading, and although the waveform is not shown here, it is amplified by the sense amplifier SA, read to IO, latched to LA, and can be rewritten. Here, the bit line is set to 0 by the write driver WD1. This is a voltage lower than that of the common source line CSL, and a current in a direction opposite to that in the case of (a) flows through the TMR element. Thus, in this operation example, rewriting can be performed in accordance with the read information. Read time, bit line precharge voltage, and the like are as described in the previous embodiments. The reading time can be shortened. Therefore, the reading current can be increased, and stable reading can be performed. At the time of reading + rewriting, as described in other embodiments, when it is found by reading that the direction of the reading current is a direction not giving disturbance, the reading can be ended without performing rewriting. .

  FIG. 18 is a circuit diagram showing the concept of a memory cell and its related circuit according to the fifth embodiment of the present invention. A rewrite control circuit WCT is inserted between the latch circuit and the rewrite drivers WD1 and WD2. The rewrite control circuit WCT receives the output of the latch circuit LA, first writes the reverse information of the signal to be written before the original write operation, and continuously writes the signal to be originally written that is the reverse of the information. WD1 and WD2 are controlled. That is, the current flowing through the memory cell flows in both directions for each writing. This can be the same operation during normal writing. As a result, the reliability of the memory cell can be improved. Thus, even if rewriting is repeated, the number of traps generated in the tunnel oxide film is small, and the distribution is not biased. In addition, a phenomenon in which a portion of the free layer is stochastically rotated in the opposite direction can be suppressed.

  FIG. 19 shows an operation example of the embodiment of FIG. Reading is the same as usual. In (a), a bit line voltage higher than Vref is a read result. In the rewrite operation, the original write operation is the direction of current flowing from the bit line to the source line through the memory cell, with the bit line set to V1 and the source line set to 0. In the present invention, as shown in the period (R) of (a), the bit line is set to V1 and the source line is set to 0, and a current in the direction opposite to the current flowing in the original writing is supplied. Thereafter, the original writing is performed in the period (N). (B) shows a case where the read result is the opposite result to (a), but the rewrite operation is also similar to the period (R) in which the write is performed in the direction opposite to the current flowing in the original write. There is a period (N) during which original writing is performed. Note that even when the source line is a common source line and a constant voltage is used, the same writing can be performed by driving the potential of the bit line above and below the voltage of the common source line.

Hereinafter, the part common to the above-mentioned Examples 1 to 5 will be referred to.
<Memory cell array>
FIG. 20 is an example showing a configuration example of ARY11 and ARY12 in which memory cell arrays are assembled in a circuit around the memory cell of FIG. 1 and an input / output terminal DQ outside the chip. In this figure, the description is made in accordance with the embodiment of FIG. 1, but it goes without saying that it can be applied to other embodiments. MC11 and MC12 to MC42 connected to the corresponding bit lines B1 to B4 and source lines S1 to S4 are memory cells, and each is composed of a TMR element TMR and a selection transistor MCT as shown in MC11. The select transistor of each memory cell is driven by the word lines WL1 and WL2. SA1 to SA4 are sense amplifiers, LA1 to LA4 are latch circuits for storing the sense results of the sense amplifiers, and WD11 / WD12 to WD41 / WD42 are rewrite drivers.

  The sense amplifier of ARY11 is selected by the YS signal YS1, and the sense amplifier of ARY12 is selected by the YS signal YS2. In this example, each memory cell array ARY11, ARY12 is configured to transmit the result of the sense amplifier to four internal input / output lines IO1-IO4. Connection between the IO1 to IO4 and the memory cell arrays ARY11 and ARY12 is performed by YS1 and YS2. Note that more memory cell arrays are actually arranged, and corresponding word lines and YS signals are prepared. One of the internal input / output lines IO1 to IO4 is selected by the multiplexer MUX1, and the signal is output to the input / output terminal DQ outside the chip. The same applies to the input of data from the outside, and the signal from DQ is distributed to each IO1 to IO4 by MUX1, and the signal is transmitted to the array to be written by the YS signal. With such an array configuration example, the present invention can be realized as a memory array.

<Chip control circuit>
FIG. 21 shows an example of a control circuit on a chip for controlling the memory cell array of FIG. CHIP is a chip of this memory chip or a device including this memory part, Vdd is an external power supply, Ai is an address signal, Clock is a clock signal, Command is a command signal, and DQ is an input / output signal. Command may be a dedicated signal or may be a signal synthesized from these signals, and these are collectively shown. In addition, it may be connected to the ground and may have a wireless interface. OVG is an internal voltage generation circuit. From Vdd and ground, based on a built-in reference voltage generation circuit, internal Vdd, Vdd ′, Vdl1, V1, V2, voltages lower than Vdd, higher voltage, or almost the same However, the stabilized voltage is supplied to the circuit on the chip.

  The CMD is an external input buffer circuit or a circuit that generates an internal signal from a command signal, and generates a sense amplifier activation signal SAE, a write enable signal WE, and the like. DEC is a decode circuit that selects a word line to be selected from an address signal, WLD is a word driver, and drives the word line WL1 and the like. YSD is a decoding circuit and a driver circuit for selecting the YS signal YSi to be selected from the address signal. IOk is an internal IO signal, and MUX and DOB are circuits for selecting and driving the output to DQ and distributing the input from DQ by IOk. What is represented by MC in the array is a memory cell, and the actual configuration is like MC11 in FIG. According to the present embodiment, the present invention can be realized, and a memory that exchanges data in synchronization with a clock signal can be realized.

  FIG. 22 shows an operation example of the circuit of FIG. In synchronization with the clock signal Clock, when ACT is input as the command signal Command, the word line rises, the sense amplifier is activated by SAE, and a read signal is obtained. SAi collectively indicates outputs of a plurality of SAs. When a read signal is obtained in the sense amplifier, a rewrite operation proceeds as shown in the previous embodiments, although not shown here in parallel with the following operation. When Read is input, YS rises and a read signal appears at IO, which is sequentially output to DQ. When Write is input, the input from DQ is distributed to IO and written to the memory cell by the PRE signal via the sense amplifier. Thus, the operation of the present invention synchronized with the clock signal can be performed.

<Specific configuration example of memory cell array>
FIG. 23 shows a cross-sectional structure example (a) of a memory cell used in the present invention together with its circuit diagram (b). A MOS transistor (MOSFET) is formed on a Si substrate, which becomes a selection transistor. D is a drain region of the MOS transistor, and S is a source region of the MOS transistor, and electrical operations can be both a source and a drain as needed. WL is a gate connected to the word line. A source line SL and a bit line BL are formed of metal wirings in the MOS transistor that serves as the selection transistor. In this example, the TMR element TMR is disposed between the metal wiring BE connected to the drain region D of the MOS transistor and the bit line BL, and the disposed location is the drain region D and the metal wiring BE. In this figure, the region may be in a different location from the region in contact with the vertical metal wiring. Depending on the process, a TMR element can be formed on a flatter surface of the metal wiring BE, thereby obtaining a TMR element having good characteristics. Note that in this figure, the vertical metal wiring in this figure that connects the metal wiring BE and the drain region D is not connected to the source line SL but passes behind the source line SL. ing. The operation of the present invention can be performed using a memory cell having such a cross-sectional structure example.

  FIG. 24 shows a cross-sectional structure example (a) of another memory cell used in the present invention together with its circuit diagram (b). Each cell has two word lines WL that are basically selected at the same time. In this configuration, as shown in the cross-sectional structure example (a), the voltage of the word line of the cell is 0 V, that is, the gate voltage is 0 V, thereby being electrically insulated. This makes it possible to reduce the layout area while using two transistors per memory cell. The operation of the present invention can be performed using a memory cell having such a cross-sectional structure example.

  FIG. 25 shows an embodiment of the TMR element portion. As described in the conventional example, the tunnel magnetoresistive element TMR has at least two magnetic layers, one is the fixed layer PL in which the spin direction is fixed, and the other is the spin direction with respect to the fixed layer. , (A) is a parallel state, and (b) is an anti-parallel state. There is a tunnel barrier film TB between these films. A more detailed example of this structure is shown in (c). The metal wiring ML and the bit line BL correspond to FIG. Also in this figure, there are a fixed layer PL, a free layer FL, and a tunnel barrier film TB.

  First, the metal layer 108 is placed on the metal wiring ML. A fixed layer PL is disposed thereon, and in this figure, a two-layer structure of 103 and 102 is formed. Reference numeral 103 denotes an antiferromagnetic film, and reference numeral 102 denotes a ferromagnetic film. By aligning the antiferromagnetic film 103 with the ferromagnetic film 102 in this way, the initially determined magnetization direction is firmly fixed. As a result, the fixed layer PL whose magnetization is not changed by a rewriting current or the like is obtained. A tunnel barrier film TB is placed thereon, and a free layer FL is placed thereon. The tunnel barrier film TB is an insulating film such as MgO. In this example, the free layer FL has a multilayer structure of 104, 105, and 106. 104 and 106 are ferromagnetic films, and 105 is a metal such as Ru (ruthenium). Also, the magnetizations of 104 and 106 are antiparallel to each other. Here, the metal layer is sandwiched between two ferromagnetic films, but this is increased to use four ferromagnetic films. Further, a structure in which metal layers (in this case, three layers in total are required) are inserted between them may be used, or a multilayer may be used. By doing so, it is possible to increase resistance to fluctuations in the magnetization direction of the free layer FL due to thermal disturbance. In general, when the temperature rises, the magnetization direction of the free layer FL easily fluctuates due to heat, and the probability of rotating in the direction opposite to the written direction increases. However, with such a multi-layer structure, the probability of rotating in the opposite direction can be suppressed to a low level that is practically acceptable. In addition, the threshold value of the current for rewriting can be kept low. The upper portion of the free layer FL is connected to the bit line BL via the metal layer 107. A TMR element like this example can perform the operation of the present invention.

  FIG. 26 schematically shows a portion of a TMR element of another memory cell array realizing the present invention. In this embodiment, the magnetization directions of the free layer and the fixed layer are not horizontal but perpendicular to the tunnel barrier layer. By selecting such a material, a memory element in which two states (parallel and antiparallel) of the TMR element are stable against thermal disturbance can be obtained. In the embodiment to which the temperature control and the rewriting method of the present invention are applied, there is a feature that a memory operation that stably operates in a wide temperature range can be realized even if scaling is advanced. By using various memory cells to which the TMR element having such a structure is applied, an operation of giving a rewrite signal having a characteristic opposite to that of the original rewrite signal, which is a feature of the present invention, can be realized.

  FIG. 27 shows another layout example of the memory cell array for realizing the embodiment of the present invention. This is an embodiment in which a local bit line and a source line are arranged under a global bit line. The upper global bit line is not shown. The area of the memory cell is 8F2 when the wiring pitch of the word lines or bit lines is 2F. FIG. 28 shows a cross-sectional view taken along a line A-A ′ in FIG. 27 and a cross-sectional view of a peripheral circuit. FIG. 29 shows a cross-sectional view between B-B 'and a cross-sectional view between C-C'.

  The memory cell includes one nMOS transistor and a tunneling magnetoresistance TMR. The word line WL is connected to the gate GP of the transistor. As the gate material, silicide or tungsten (W) is stacked on top of P-type polysilicon or P-type polysilicon to reduce resistance. The memory cell transistor is formed in the p-type semiconductor region pWEL. The p-type semiconductor region pWEL is formed in the n-type semiconductor region DWEL, and this DWEL is formed on the P-Sub. A source line contact SLC is disposed on one of the diffusion layers LN of the nMOS transistor. The source line contact is shared with adjacent memory cells to reduce the area. A source line is wired on the source line contact in a direction perpendicular to the word line. In the diffusion layer LP where the source contact is not disposed, the lower electrode contact BEC connected to the tunnel magnetoresistance TMR is disposed. The lower electrode contact BEC is connected to the lower electrode BE where the tunneling magnetoresistance is arranged. On the lower electrode BE, a tunnel magnetoresistance TMR composed of a plurality of magnetic films and a tunnel film is disposed. The tunnel magnetoresistance TMR includes at least one tunnel film TB and a fixed layer PL and a free layer FL disposed on both sides thereof. In the magnetic fixed layer PL, the direction of spin of electrons inside is fixed in a fixed direction. On the other hand, in the magnetic free layer FL, the internal spin direction of the electrons is in one of two states, a parallel state and an antiparallel state to the fixed layer.

  In this configuration, the fixed layer PL is disposed between the tunnel film TB and the lower electrode, and the free layer FL is disposed between the bit line BL and the tunnel film TB wired on the upper layer of the tunnel magnetoresistance TMR. The bit line is wired perpendicular to the word line and parallel to the source line. The tunnel magnetoresistance TMR has a rectangular or elliptical shape in which the bit line wiring direction is longer than the word line wiring direction. Thereby, there is an advantage that the retention characteristic in the spin direction of the free layer FL is improved. The operation of the present invention can be performed using a memory cell having such a cross-sectional structure.

  FIG. 30 is a diagram showing an example of a cross-sectional structure of another memory cell array for realizing the present invention. The memory cell transistor is composed of a vertical MOS, and the memory cell area can be reduced to 4F2 with F being the minimum dimension for processing. PL is a fixed layer, FL is a free layer, TB is a tunnel barrier, and forms a TMR element. In this figure, PL is at the top, but PL may be below FL. Also, the order of arrangement in the height direction with the vertical MOS may be different from this figure. GA is a gate, upper and lower n + regions are a source and a drain, and the same operation as that of a normal MOS is performed by a voltage applied to the gate GA in the p region. The gate GA may wrap the p region in a ring shape, or may control the surface of the vertical structure from two directions or from three directions. As the vertical MOS, this figure is an nMOS, but a pMOS can also be used.

  FIG. 31 is a plan view of this structure. Although corresponding to FIG. 30, in order to explain the structure, the layers to be displayed in four cells are changed and shown. The lower right cell shows a source line SL, a transistor region, and a gate wiring. The upper right shows a state where BE, which is a metal layer of a pedestal that forms the TMR element, is placed on the upper right. The upper left is a state in which the TMR element TMR is mounted, and the lower left is a state in which the bit line BL is covered. The operation of the present invention can be performed using a memory cell having such a structure.

<Generation method of reference voltage>
FIG. 32 shows an example of temperature characteristics of the TMR element used in the present invention. In the reading and rewriting of the present invention, the flowing current is determined in consideration of this characteristic example. In this figure, the horizontal axis represents the current flowing through the TMR element, and the vertical axis represents the resistance at that time. The solid line is when the temperature is low, and the broken line is when the temperature is high. If the initial state is a parallel state, the resistance is low at this time, and its value is Rp. When the current is increased in the right direction in this figure, when the amount of current in this direction becomes larger than a certain current value, the state of the TMR element changes and the antiparallel state is obtained. In this state, the resistance is large and the value of Rap. After this state is reached, the current to be passed is increased in the opposite direction. Then, when the amount of current in this direction becomes larger than a certain current value, the state of the TMR element changes and returns to the original parallel state. This characteristic varies with temperature. First, the resistance value Rap in the anti-parallel state, which is a high resistance state, is large at low temperatures but small at high temperatures. In addition, the magnitude of the current at which the state is switched is large at low temperatures but small at high temperatures in absolute values in the respective directions. On the other hand, the resistance value Rp in the parallel state hardly depends on the temperature. FIG. 33 shows the resistance at the time of reading with the horizontal axis representing the temperature. In consideration of this characteristic, a memory cell array for realizing the present invention is assembled.

  FIG. 34 shows another example of a method for realizing a reference cell that realizes Vref used for a read operation in an array used in the present invention, based on such characteristics. There are two memory cell arrays Array1 and Array2, each having a read cell and a reference cell for the sense amplifier AMP (whose output is SAt). In this example, for example, in Array1, the left RC1 is a readout cell, and the right side constitutes a reference cell together with Array2 as described below. At the same time, although not shown in the drawing for simplicity, there is also a reference cell on the left side, which is used when reading the right memory cell. Rsa is a load resistance of the input of the sense amplifier, Csa is a parasitic capacitance of this portion, and Cb is a parasitic capacitance of the bit line. Further, at the input terminal of the sense amplifier AMP, there is a switch between Array1 and Array2, the reference cell side is closed (On), and the read cell side is opened (Off).

  In this way, two cells are used as reference cells (dummy cells), which are Rap “1” state cells and Rp “0” state cells. At this time, the load resistance is equivalently half of Rsa by short-circuiting the inputs of the sense amplifiers of Array1 and Array2. As a result, an intermediate potential Vref between “1” reading and “0” reading can be generated at the input of the sense amplifier on the reference cell side. On the left side, reading is performed in both Array1 and Array2.

  From these, a current corresponding to the resistance corresponding to the stored information flows, and in the sense amplifier, the voltage signal corresponding to the load resistance Rsa at the other input terminal paired with the terminal input by the reference cell. Appears. The difference between this signal and Vref can be read at high speed by reading with the sense amplifier as described in the embodiments so far. In this embodiment, by using Array1 and Array2, the parasitic capacitances in the sense amplifier are equal and the same resistance is used, so that Vref generated by the reference cell is “ Since it is intermediate between “1” reading and “0” reading, the activation timing of the sense amplifier can be advanced and high-speed access can be realized.

  FIG. 35 shows a simulation waveform describing the entire array. The potential of the reference cell is intermediate between “1” reading and “0” reading even in a transient state during reading. As a result, the sense amplifier activation signal SAE can be operated early. Thereafter, the read cell and the reference cell are rewritten. The reference data is rewritten so that the same data is always written. By using the memory cell array having such a structure and performing rewriting at the time of reading, which is a feature of the present invention, it is possible to stably perform reading at a high speed with a relatively large current.

<Structure of MOS transistor>
The present invention is particularly effective when the TMR element is miniaturized. However, various problems arise when the miniaturization of the MOS transistor advances with the miniaturization of the TMR element. Therefore, a structure of a MOS transistor suitable when the present invention is implemented will be described below.

  FIG. 36 is a diagram showing another embodiment of the present invention. The cross-sectional structures of three types of elements are shown. Both are characterized by having a UTB which is a buried oxide film (BOX) layer, and the thickness is as thin as 30 nm or less. The nMOS and pMOS portions are fully depleted (FD), the Si layer on the UTB is thin, and the Memory portion has a TMR element. Also, the Memory portion may be formed using pMOS. By taking such a cross-sectional structure, it is possible to perform the control operation by using the back gate formed under the UTB as a gate insulating film. In the fully depleted (FD) type portion, variations in threshold voltage and dynamic threshold voltage control according to the operation mode can be performed, and high speed, low power, and low leakage current can be realized. In the memory cell portion, the leakage current can be kept small during standby while obtaining the driving capability necessary for rewriting. To realize these, the thickness of the UTB needs to be as thin as 30 nm or less. With this thin UTB, the voltage under the UTB can be controlled to dynamically control the threshold current or correct the variation, and a rewriting current large enough to invert the TMR element can be obtained. become. In particular, only a selected memory cell is excellent in that a sufficient rewriting current can be obtained with a low threshold. In addition, during the rewriting operation, a current can be sufficiently obtained even when the current supplied to the TMR element is supplied in the MOS source follower mode from the direction of the current.

  Hereafter, the structure of each part of this figure in a present Example is demonstrated. The nMOS and pMOS are formed on the p-sub with a structure described below, and both are separated by STI, which is a trench type insulating region. First, regarding the pMOS, an n region is placed under the buried oxide film UTB, which serves as a back gate. This back gate is taken out to the semiconductor surface via n +. In the nMOS portion, a p region is placed under the buried oxide film UTB, which serves as a back gate. This back gate is taken out to the semiconductor surface via p +. Further, a dn region that is an n-type semiconductor is provided to separate the p region under the UTB from the p-sub that is the same p-type semiconductor. This dn region is taken out to the semiconductor surface by an n region and an n + region arranged under the STI region. The STI separates the nMOS and the pMOS configured as described above. The dn region and the n region which is the back gate region of the pMOS are also separated. As a result, the threshold voltage can be changed according to the operation state of the circuit, and a high-speed, low power and low leakage current semiconductor device can be realized. The Memory portion has the same MOS structure as the nMOS.

  The gate is connected to the word line (WL), the drain is connected to the bit line (BL), and the source is connected to the source line (SL). SL connects memory cells with a diffusion layer, and is connected to a lower resistance metal wiring or the like for each of several memory cell clusters. Again, a p region is placed under the buried oxide film UTB, which serves as a back gate, and this back gate is taken out to the semiconductor surface via p +. Further, a dn region that is an n-type semiconductor is provided to separate the p region under the UTB from the p-sub that is the same p-type semiconductor. This dn region is taken out to the semiconductor surface by an n region and an n + region arranged under the STI region. As a result, it is possible to realize a memory cell that can obtain a driving capability necessary for rewriting and suppress a leakage current during standby. The MOS threshold voltage can be increased during standby, and the MOS threshold can be decreased during selected operations. Of course, at the time of reading, which is a feature of the present invention, reading can be performed stably with a relatively large current by performing rewriting.

  FIG. 37 shows another embodiment of the present invention. The difference from the embodiment of FIG. 36 is that it has a MOS portion from which UTB is removed. The portion described as bulk corresponds to the pMOS and nMOS portions. Since UTB is as thin as 30 nm or less, such a portion can be easily formed. The structure of this part is the same as that of a conventional bulk CMOS. With this structure, a protection element in the input / output circuit can be realized. It is also possible to utilize the past bulk assets of some analog circuits.

<Application example of the present invention>
As described above, when the present invention is applied, the TMR element can be miniaturized, and accordingly, the MOS transistor can be miniaturized. As a result, many MOS transistors can be integrated and various applications can be considered. In the following, an application example suitable when the TMR element and the MOS transistor are miniaturized will be described.

  FIG. 38 is a diagram showing an application example of the present invention, which has a circuit block using a flip-flop circuit having a TMR element in a logic circuit to be described later, and is configured by a MOS transistor having the structure of FIG. 36 or FIG. The figure shows an example of a processor having a memory cell array SPRAM having a block and rewriting at the time of reading. The main content of this figure is that in a processor composed of a plurality of accelerators (arithmetic units), each accelerator performs a pipeline operation. The threshold voltage of the MOS transistor constituting the circuit of each stage of the pipeline is It has a chance to control each stage independently.

  Specifically, when one accelerator 1 is taken as an example in the plurality of accelerators 1 to n in FIG. 38, it is as shown in the lower part of FIG. That is, in the accelerator 1, an SP-FF that is a flip-flop having a TMR element that holds a state and a logic block provided between two SP-FFs are arranged, and this is a unit of a stage. In the figure, logical block 1, logical block 2 to logical block m are shown. Corresponding to the logic blocks of the respective stages, CBG1, CBG2 to CBGm are arranged as circuits for controlling the threshold voltages of the MOS transistors constituting the logic block. By these circuits, the threshold voltage of the MOS transistor constituting each logic block is controlled by changing BGmN / BGmP from voltages BG1N / BG1P and BG2N / BG2P supplied to each logic block. These are used as the back gate voltage of the MOS transistor.

  A configuration example of the MOS transistor is shown in FIG. 36 or FIG. As a result, the speed of each logic block in each stage can be changed after manufacturing. This makes it possible to finish the processing within the same fixed time in each stage. Although there may be one accelerator having such a configuration, the present invention constitutes a processor system in which a plurality of such accelerators are integrated. Each of the plurality of accelerators is an arithmetic unit that performs a pipeline operation. In each accelerator, the speed of each stage of the pipeline can be changed after manufacturing.

  As will be described later, this processor is configured to perform parallel processing by combining a plurality of processors. Furthermore, tens of thousands of processors are connected through a network to form a computer system. As described above, this one processor may supervise a plurality of accelerators 1 to n having a pipeline capable of adjusting the speed of each stage after manufacturing, and the entire processor. In addition, the arithmetic circuit ON, the memory block SPRAM that performs rewriting at the time of reading described in the embodiments so far, the memory controller that controls the external memory, and the generation of the substrate voltage and the back gate voltage for the entire processor , And a back bias voltage generation circuit, and includes a PLL and clock generation and control for generating a plurality of clocks and using them appropriately. In the circuit block CBG1 described as an example of the accelerator 1, all of the circuits may be placed in each accelerator, or the common part as much as possible is placed in the back bias control and back bias voltage generation circuit portion in FIG. There is also a case where In order to control the threshold voltage of the MOS transistor, the substrate voltage is controlled in the bulk MOS, and the back gate is controlled in the FD-SOI as in the example of FIG. As a result, as long as the state is stored in the SP-FF which is a flip-flop having a TMR element for holding the state, the MOSs of the logic blocks 1 to m can be cut off at any time, or the MOS can be turned off. It is also possible to keep the leak extremely small by setting the threshold voltage high. Further, the SPRAM portion can perform stable reading with a relatively large current.

  FIG. 39 shows an example of a memory element that constitutes an SP-FF that is a flip-flop having a TMR element that holds a state. In this example, in addition to the MOS transistors M21, M22, M31, M32, M41, and M42 constituting the SRAM circuit, the TMR elements TMR1 and TMR2 are connected to the storage node of the SRAM via the MOS transistors M12 and M12. . The other end of the TMR element is connected to S1. RW is a word line, D1 and / D1 are bit lines, SW is a control line for driving M12 and M12 when writing and transferring data to the TMR element, and VD and VS are power supplies. In this memory element, since the TMR elements TMR1 and TMR2 retain information even when the power is turned off, the stored data is loaded into the SRAM circuit portion when the power is next turned on. Can do. As a result, a flip-flop that maintains the state even when the power is cut off can be realized.

  FIG. 40 shows an operation example of the circuit of FIG. (A) is an operation for writing data to the TMR elements TMR1 and TMR2, and (b) is an example in which the information of the TMR element is loaded, and thereafter, the operation is performed by reading the data of the SRAM circuit portion. First, in (a), RW is set to the high level VA, and the MOS transistors M21 and M22 are sufficiently turned on. Next, a signal to be written is applied to D1 and / D1, where a high level VA is applied to D1, 0V is applied to / D1, SW is set to a high level VA, and S1 is set to VB, which is a half potential of VA. As a result, in TMR1, a voltage lower than the threshold value M11 from VA is applied to the node N1, which is one terminal, and a voltage VB is applied to the other terminal S1, and the current flows from N1 to S1. In TMR2, since a voltage of 0 V is applied to one terminal / N1, and a voltage VB is applied to the other end S1, a current flows from S1 to / N1 in the opposite direction to TMR1. As a result, TMR1 and TMR2 are written in the opposite states. For example, TMR1 is written in the high resistance state and TMR2 is written in the low resistance state. In (b), at the time of data loading, SW which is a control line for driving M12 and M12 is set to the high level VB. RW remains at 0V. As a result, the resistance difference between TMR1 and TMR2 is transferred to the SRAM portion. At this time, there is a case where VD is boosted from 0 V to a desired voltage. Thereafter, this information can be read at any time by selecting the RW by normal reading.

  Next, FIG. 41 shows a circuit block diagram for changing the substrate voltage (back gate voltage) described in FIG. The circuit CKE is a circuit such as the logic block 1 of FIG. 38, the power supply voltages are Vd and Vs, the substrate voltage (back gate voltage) terminals and the voltages are VP and VN. Here, there are provided Vthp and Vthn for generating a voltage corresponding to a process variation or the like. Each operates with power supplies Vdd and Vss (this may or may not be the same as Vd and Vs). In Vthp, a voltage is generated by a pMOS and a resistor, and in Vthn, a voltage is generated by an nMOS and a resistor. Occur. These voltages are generated according to the process conditions by reflecting the process conditions by the used pMOS and nMOS. These voltages are once stabilized by the OP amplifier. At this time, a reference voltage Vref independent of the process is required. This can occur with a well-known bandgap generator or the like.

  These output voltages are VPL and VNL, respectively, and in the present invention, they are substrate voltages (back gate voltages) serving as threshold values suitable for high-speed operation of the circuit CKE, and compensate for process variations and design variations as described above. You can also. A voltage shifted by a certain voltage from these voltages is created by the voltage shifter. These can be generated by using a diode, a resistor, or a charge pump with a power supply voltage or an internally generated voltage and VPL and VNL. When the outputs are VPH and VNH and there is a state in which the circuit is not operated, the threshold voltage of the circuit CKE can be increased to reduce the leakage current. These generated voltages may be switched by MUX and used as VP or VN voltage. This switching is performed by rewriting the contents of the register indicated as B-Register by the signal MSB from the controller MC. When this register is switched, the MUX is switched accordingly, and the output to VP and VN can be selected from VPH / VPL and VNH / VNL. In addition, in MUX, the stability of the output voltage may be increased using an OP amplifier together with switching. As described above, the function of changing the substrate voltage (back gate voltage) necessary for the present invention can be realized by using the mechanism.

  FIG. 42 shows another embodiment of the present invention. The main contents of this embodiment are that the memory controller on the semiconductor chip CHIP controls the memory (main memory). This is based on the operation state of the memory controller or the signal indicating the operation state. The power state of the circuit block PU performing the operation is changed during the period in which the head address of the memory is searched. The entire configuration example includes a circuit block PU that performs at least one operation on the semiconductor chip CHIP, which has a function of changing the power state, and is connected to the internal bus BUS1 together with a cache memory CM using SPRAM. The BUS1 is a circuit block for exchanging signals between the CPU, the memory, and the outside for managing various circuit blocks on the CHIP, and is IO-connected. The bus BUS3 to the outside of the chip is connected to the IO, and a file memory, for example, is connected to the BUS3. The file memory is composed of, for example, a flash memory or an HDD.

  A memory controller is connected to BUS1, a bus BUS2 to the outside of the chip is connected to this memory controller, and a memory (main memory) is connected to BUS2. This memory (main memory) is SPRAM or a mixture of SPRAM and DRAM. In such a configuration, the circuit CKE of the PU is composed of a CMOS element, and the power source has a high potential of Vd and a low potential of Vs, but the substrate or back gate voltage can be controlled. . The voltage applied to the substrate or the back gate and its terminals are VP and VN, the pMOS is VP, and the nMOS is VN. The circuit block that controls these values is the BB controller, and the circuit block that controls the frequency of the clock CLK applied to the circuit CKE is CLKG. These may be prepared for each PU, or may be collected by a plurality of PUs depending on the operation content. Moreover, a common part may be taken out and other PUs may be provided in each PU. The power state of the PU can be changed by these BB controller and CLKG.

  The signals for changing the power state are MSK and MSB, both of which are signals depending on the state of the memory controller. In other words, this signal indicates that the memory controller is in a state of searching for the start address of the memory (main memory). By this signal, the frequency of the circuit CKE of the PU and the substrate voltage (back gate voltage) are changed. It can be in a power state. Note that since the state of the memory controller is performed by the CPU connected to BUS1, it can be said that the MSK and MSB are signals generated by the CPU. With such a configuration, in the present invention, the circuit block PU that performs the operation cannot operate with only the information in the cache memory CM (cache miss), and is searching for the start address of the memory outside the CHIP (main memory). The circuit block PU can be brought into a low power state by changing the frequency of the circuit CKE and the voltage applied to the substrate or the back gate by MSK and MSB.

  It should be noted that when there are a plurality of circuit blocks PU, each of them has a feature that it can take such a low power state. In addition, the standby power of the on-chip memory is very small. In the PU, the SP-FF can be used to find the non-operating time and turn off the power. Among the above, a part or all of the SPRAM is a memory cell array that performs rewriting at the time of reading.

  FIG. 43 shows an example of a main part of the operation of the present invention. MSB and MSK are signals for changing the clock frequency and the substrate voltage (back gate voltage) applied to the circuit CKE in FIG. VP and VN are the substrate voltage (back gate voltage) signals, and CLK is the clock frequency. In FIG. 42, it is assumed that a miss to the cache memory has occurred and the state of searching for the start address of the memory (main memory) is reached at time t1. Then, MSB and MSK are switched, and the circuit CKE shifts to a state where power is lower. That is, VP changes from potential VPL to VPH, and VN changes from VNL to VNH. Here, in the circuit CKE, at the potentials VPL and VNL, both the pMOS and nMOS have low threshold voltages and can operate at high speed. On the other hand, at the potentials VPH and VNH, the threshold voltages of the pMOS and nMOS are high and the leakage current can be kept low.

  At t1, CLK is also changed. Before the time t1, the frequency f1 was high, but here it switches to the low frequency f2. As a result, in the state where the head address of the memory (main memory) is searched, the frequency is low and the threshold voltage is high, so that the charge / discharge power and the leak power can be kept low. Or if it is a circuit provided with SP-FF, you may cut off a power supply completely. Thereafter, when the operation of searching for the head address of the memory (main memory) is completed, MSB and MSK are switched again at time t2, VP and VN return to VPL and VNL, and CLK returns to f1. As a result, high-speed operation is possible. As described above, in this embodiment, it is possible to keep power low in a state where the head address of the memory (main memory) is searched. As will be described later, at t2, the PU may directly operate using data from the memory (main memory), which is generally slower than when operating on the contents of the cache memory CM. . Therefore, the clock frequency CLK and the substrate voltages (back gate voltages) VP and VN suitable for this can be given.

  2. Description of the Related Art A technology for configuring an arithmetic circuit using a variable logic unit called an FPGA (Field Programmable Gate Array) or an FPLD (Field Programmable Logic Device) is in progress. The variable logic unit requires a rewritable nonvolatile switching element, which can be created using a TMR element. Therefore, if this switch element is made, the power of the variable logic unit can be greatly reduced by using the stable SPRAM or the nonvolatile flip-flop SP-FF capable of relatively large read current as described above.

  FIG. 44 shows an example of the configuration of the switch element S11. A flip-flop circuit is inserted between the node N2 on the MOS transistor M1 side and the node N3 on the MOS transistor M3 side. By this circuit, a signal appearing at the node N2 can be held, and an inverted signal of this N2 appears at N3, whereby the MOS transistor M3 can be controlled. The signal N2 is determined by the TMR element TMR1 between the terminal b and the node N1 and the MOS transistor M2 controlled by SW. The TMR element TMR1 may be in a high resistance state or a low resistance state. When the SW is switched, a signal corresponding to this state appears at N2 and is held by the flip-flop circuit. If the voltage at the node N3 is high by the flip-flop, the MOS transistor M3 is turned on, and D1 and D2 are conducted. On the other hand, if the voltage at the node of N3 is low level by the flip-flop, M3 is turned off, so that D1 and D2 become non-conductive. Using this, the variable logic unit can be rearranged as described later.

  FIG. 45 shows an operation example at the time of writing to the circuit of FIG. RW remains at 0V and SW is raised, but in the portion indicated as writing 1, b is at the high level V1, and S1 is at the low level 0V. Therefore, a current flows from b to S1 in the TMR element, and information corresponding to the current is written. On the other hand, in the portion shown as writing 2, b is 0V and S1 is V1. Therefore, a current flows in the direction from S1 to b in the TMR element, and information corresponding to this flows. Note that writing 1 and writing 2 show two cases according to the information to be written, and do not indicate that these operate continuously in time.

  FIG. 46A shows a switch that connects the orthogonal signal line CN and the signal line RN. This type of connection is often used for variable logic units. This switch can be realized by the circuit shown in the embodiment of FIG. That is, as shown in FIG. 46B, D1 and D2 of RC1 in FIG. 44 may be connected to the signal line CN and the signal line RN. In the future, the switch S is a circuit using the RC1 as an example, and will be referred to as a “TMR switch”. The state in which the switch is closed is a state in which D1 and D2 are electrically connected, and the state in which the switch is open is an electrically out of state state. These two states are TMR states. As described with reference to FIGS.

  FIG. 47A shows a TMR switch array in which the TMR switches of FIG. 46 are arranged on the array. Here, S11 is a switch that can selectively connect and disconnect the vertical signal wiring CN1 and the horizontal signal wiring RN1. In some cases, this is shown in FIG. 47 (b). As shown in this figure, any CN1 to CNn and any RN1 to RNm can be connected by a configuration in which TMR switches are arranged in n columns of CN1 to CNn and m rows of RN1 to RNm.

  FIG. 48 illustrates an AND / OR circuit as an example of a circuit block having a variable function or a variable logic unit RCP1. The circuit block RCP1 has an AND surface and an OR surface. For general logic operations, an AND circuit that performs a product operation and an OR circuit that performs a sum operation are prepared for a plurality of inputs. It is decomposed to which one is subjected to OR operation. If a circuit as shown in the example of FIG. 48 is prepared, this combination can be realized. That is, in the example of this figure, for the inputs A, B, C, and D, which signal is to be AND-operated is selected by the aforementioned TMR switch array inside the AND plane. The resulting signal is input to the OR plane. Here again, which of these signals is subjected to the OR operation is selected by a TMR switch array described later. The results F1 to F4 are the results of performing a desired product-sum operation on the inputs A, B, C, and D. In this way, by operating a TMR switch using a TMR element, a function variable logic operation circuit that can be rearranged into a device that performs a desired logic operation can be realized. If this is used as a component of the present invention, a low-power and function-variable LSI can be created.

  FIG. 49 shows an RCP unit which is an example in which a TMR switch element is applied to an FPGA unit. This unit includes a plurality of logic cells L11 to L33, connection cells C11 to 52, and switch cells S11 to S22 arranged in a matrix. Each of the logic cells L11 to L33, the connection cells C11 to 52, and the switch cells S11 to S22 is provided with the TMR switch element, and a desired function can be set according to these states. For example, in the logic cells L11 to L33, logic functions such as NOR and NAND can be changed by the TMR switch element. In the connection cells C11 to 52, the connection between the corresponding logic cells L11 to L33 and the wiring can be changed by the TMR switch element. In the switch cells S11 to S22, the connection between the wirings can be changed by the TMR switch element. Conventionally, these can be changed by a switch composed of a nonvolatile memory and a MOS circuit, but there is a drawback that low voltage operation is not possible.

  FIG. 50 shows another example. This unit has logic blocks L11 to L22 and an interconnection block CB. Each of the logic blocks L11 to L22 and the interconnection block CB is provided with the TMR switch element, and a desired function can be set according to these states. For example, the logical blocks L11 to L22 can be set with logical functions such as registers and arithmetic units. In the interconnection block CB, the interconnection of the functional circuits set in the logic blocks L11 to L22 can be switched. This configuration generally corresponds to a configuration called CPLD (Compliant Programmable Logic Device). Since the wiring is concentrated around the switchable interconnection block, there is an advantage that the wiring delay is small and almost constant.

  FIG. 51 shows an example of another functional variable logical block RCP3. In this figure, A1 is a circuit block whose function can be changed by the TMR switch, and is a unit unit or block constituting FIG. 48 itself or FIG. 49, or a combination thereof. Among these, the circuit that controls the TMR switch is the CTR, the input / output circuit for the calculation result of A1 is INF, the SPRAM is a spin injection RAM that performs rewriting at the time of reading, and the PRC performs its own calculation. However, it is a processor that integrates the whole, and the input / output bus with the outside is IO. The SPRAM may be connected to the INF in this way and used in common with each A1. Alternatively, the SPRAM may be distributed within each A1. According to the present embodiment, the connection method of A1 and each function can be changed according to data and commands from the IO.

  FIG. 52 shows an example of another function variable logical block RCP4. The difference from FIG. 51 is that each circuit block constituting this matrix may have a different circuit configuration, and a circuit for internally switching the circuit function indicated as SHFL is added. First, since each circuit block has a different circuit configuration, each of A11 to Aij shown in this figure is a circuit block having a different circuit configuration. Each of these functions and the method of connection between them is CTR. It is controlled by. The means for switching between these is performed using a TMR switch. As a result, each function can be switched and these connection methods can be switched, so that more advanced functions can be switched. Next, the function of SHFL will be described with reference to FIG. In this figure, the time change of the data processing amount in the A22, Aab, and Axy circuits is schematically shown. In this example, only A22 has a large data processing amount between t1 and t2 of time, but other Aab and Axy have a small processing amount compared to this. Processing is concentrated on A22. At this time, in A22, the power consumption is large, the heat generation is also large, and the processable amount may be exceeded. If this state continues, the overall processing is degraded. On the other hand, once entering such a state, this state often continues. In order to avoid this, SHFL is provided. This SHFL monitors the activity of each circuit block from the current amount and data amount of each circuit block, and when an excessive amount of processing is added to A22, the function is reorganized again. This may be realized by simply passing half of the processing to another circuit block and adding a function for integrating them to another circuit block or the circuit block in question. By doing this, in the example of FIG. 53, the processing amount is distributed after t2.

  FIG. 54 shows an example of a semiconductor integrated circuit according to the present invention using an RCP (FPGA using a TMR switch or a circuit block using another variable logic) using a TMR switch element. The semiconductor integrated circuit shown in the figure is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique. This semiconductor integrated circuit has, for example, a microcomputer unit, an RCP unit as a logic unit whose function can be switched by a TMR switch, an input / output circuit IO, a peripheral circuit unit, and a P bus which is a peripheral bus. The microcomputer unit includes a CPU (Central processing Unit) and an SPRAM, and other types of memory ORAM may be mounted together. These are commonly connected to an internal bus (I bus). The peripheral circuit portion Peri is connected to the P bus, and the IO is connected to the P bus and the I bus. IO is interfaced with an external bus or an external peripheral circuit (not shown). The RCP unit is connected to the I bus and IO. The other peripheral circuit section is not particularly limited, but includes a timer, a counter, and the like.

  As described with reference to FIG. 38, the CPU and Peri can freely stop the internal operation without losing the information by SP-FF, and the SPRAM is rewritten at the time of reading, so that stable operation can be performed. According to this, a high-speed FPGA using a normal programmable microcomputer and a TMR switch element by SPRAM and CPU can be formed on the same chip, and the processing speed and flexibility can be greatly improved. Furthermore, the power can be greatly reduced by SP-FF and SPRAM utilizing the non-volatility.

  FIG. 55 shows an example of a data processing system to which the semiconductor device according to the present invention is applied. The system shown in the figure is a mobile device system such as a mobile phone, and includes an antenna, a power amplifier 81, a high frequency unit (RF-IC), a processor, A / D / D / A, a microphone / speaker, and a liquid crystal display (LCD). LCD driver, ORAM (various RAM) / OROM (various ROM), SPRAM, IC card interface and flash memory card interface. The processor includes an RCP + CPU unit using SPRAM and a TMR switch. Furthermore, SP-FF is used, and the operation can be stopped freely without losing information. Accordingly, both software processing by the CPU and hardware processing by the RCP can be set in a programmable manner, so that it is possible to quickly respond to market changes, standard changes, and service changes. And low power.

  FIG. 56 shows an example in which the semiconductor device according to the present invention is made into an MCM (multichip module). 56A is a plan view, and FIG. 56B is a front view. CPU chip that can switch functions with TMR switch and SPRAM, variable-function RCP chip with TMR switch, SPRAM that may be rewritten at the time of reading, storage element SSD composed of solid state elements such as NAND flash Is mounted on a high-density mounting board. An RF chip or the like may be mounted. According to this, the function that the user wants to realize can be realized in a shorter period than in the case of high performance and single chip.

  FIG. 57 shows an example in which the semiconductor device according to the present invention is made into an MCP (multichip package). FIG. 57A is a plan view, and FIG. 57B is a front view. The MCP semiconductor device includes a CPU chip that can be switched in function by including a TMR switch and an SPRAM, a variable function RCP chip that includes a TMR switch, an SPRAM, and the like. Thus, a system with a short trial period and low power can be configured.

  58, each processor is the processor shown in FIG. 38, for example. In the example of FIG. 58, four processors, processor 0 to processor 3, form one node, and M nodes (node 1 to node M-1) are formed in a network. The processors 0 to 3 may be four processors of the same type or a combination of different processors. A large computer having such a configuration is suitable for parallel computation, and necessary computations distributed to each node are simultaneously processed by four processors. At this time, for example, the processor 0 is responsible for scheduling of the entire calculation and communication processing with other nodes.

  FIG. 59 is a diagram showing a hierarchical structure mainly including a memory in the computer system. Three layers of CPU, RAM, and storage are used. Among these, the CPU includes logic, registers, FFs, caches, and the like. The storage is composed of an HDD, a NAND flash or the like. (A) is conventional. Roughly speaking, the CPU and RAM are premised on volatility, that is, on the premise that all information will be lost when the power is cut off, and only the storage becomes non-volatile. Yes. A part of ROM exists as a non-volatile element in a CPU (in the case of mixed mounting) and a RAM area, but many areas of the memory are volatile DRAM and SRAM. The storage also has a configuration called e-file memory configured with DRAM. Here, in order to avoid unexpected power interruption, data is normally multiplexed and held. Also, a measure is taken to prepare a battery and avoid erasing the volatile data at the time of data retention. In order to adopt such a configuration, that is, the non-volatile part and the volatile part are mixed, and the data reliability must be placed in the non-volatile part. It takes a long time to load, and also when the power is cut off, it is necessary to store everything necessary for the volatile contents in the non-volatile portion, which also takes time. In addition, since the copy of the non-volatile part is in the volatile part, it is necessary to make the both coincide with each other at regular intervals, or it is necessary to multiplex like an e-file memory. Or preparing batteries, there are problems such as an increase in the area occupied by power and devices.

  If the system described in the present embodiment is used, this can be changed to all non-volatile parts as shown in (b), and the NV-CPU, NV-RAM, and storage are all non-volatile three layers. Further, mainly in the NV-RAM portion, the rewrite operation can be performed after the read operation to improve the reliability. As a result, the above-mentioned problems are solved, the system can be started instantly, can be shut off at any time, and there is no need to hold data with a minute current. According to the embodiment of the present invention, an apparatus having such characteristics can be realized.

  The present invention relates to a semiconductor memory device, and is a non-volatile, large number of rewrites, a small area memory array that performs a rewrite operation after a read operation, eliminates the influence of the read disturb, and improves the high speed and reliability. The present invention relates to the field of memory or single item memory.

  MCT: selection transistor, TMR: magnetic element taking different resistance depending on stored information, Vref: read reference voltage, BL: bit line, SL: source line, WD1, WD2: rewrite driver, WE: write control Signal, SA: sense amplifier, LA: rewrite latch, SAE: sense amplifier control signal, YS: Y selection signal, IO: IO line, MC, MC11, MC12, SCR1: memory cell, T1: TMR element, WL1, WR1: Word line, MC11, MC12: Memory cell, RE: Read control signal, IO: I / O line, Y1: Column selection signal, SL, SL1: Source line, SLC: Source line contact, BEC: Lower electrode contact, BL, BL1 : Bit line, BE: lower electrode, TMR: tunnel magnetoresistive element, GP: P-type polysilicon gate LP: P type diffusion layer, FL: free layer, TB: tunnel film, PL: fixed layer, GN: n type polysilicon gate, LN: n type diffusion layer, PWEL: P type semiconductor region, NWEL: N type Semiconductor region, P-Sub: p-type substrate, STI: element isolation region.

Claims (6)

Multiple word lines,
A plurality of bit lines wired in a direction orthogonal to the plurality of word lines;
A plurality of memory cells arranged at predetermined intersections of the plurality of word lines and the plurality of bit lines;
A read circuit for reading information from a selected memory cell among the plurality of memory cells;
A rewriting circuit for rewriting the selected memory cell based on information read by the read circuit;
Each of the plurality of memory cells includes a tunnel magnetoresistive element in which a tunnel film, a fixed layer, and a free layer are stacked, a gate thereof connected to a corresponding one of the plurality of word lines, and a drain thereof A MOSFET connected to the fixed layer side of the tunnel magnetoresistive element,
The free layer side of the tunnel magnetoresistive element is connected to a corresponding one of the plurality of bit lines,
The fixed layer is disposed adjacent to the tunnel film, and the direction of electron spin is fixed in a predetermined direction.
The free layer is adjacent to a surface opposite to the surface adjacent to the fixed layer of the tunnel film, and the direction of electron spin is either parallel or antiparallel to the fixed layer,
2. A semiconductor device according to claim 1, wherein a period in which the read circuit reads information from the selected memory cell is shorter than a period in which the rewrite circuit writes information read by the read circuit into the selected memory cell again. In claim 1,
The read circuit has a first direction as a current flowing through the tunnel magnetoresistive element when reading information from the selected memory cell,
The tunnel magnetoresistive element has a second current opposite to the first direction when current flows in the first direction when the first information is written and second information different from the first information is written. Current flows in the direction
The rewrite circuit does not perform a rewrite operation when the information received from the read circuit is the first information, and performs a rewrite operation when the information received from the read circuit is the second information. A semiconductor device comprising: In claim 1,
The tunnel magnetoresistive element has a second current opposite to the first direction when current flows in the first direction when the first information is written and second information different from the first information is written. Current flows in the direction
When the first information is written, the rewrite circuit passes a current in the second direction, then flows a current in the first direction, and writes the second information in the first direction. After flowing, a current flows in the second direction. In claim 1,
The tunnel magnetoresistive element has a second current opposite to the first direction when current flows in the first direction when the first information is written and second information different from the first information is written. Current flows in the direction
The source of the MOSFET is connected to a fixed potential,
When the first information is written, the rewrite circuit sets the potential of the selected bit line out of the plurality of bit lines to a first potential lower than the fixed potential, and writes the second information. A semiconductor device characterized in that the potential of the bit line is a second potential higher than the fixed potential. In claim 1,
Information read by the reading circuit is output in synchronization with a clock signal. In claim 1,
The free layer and the fixed layer have a magnetization direction perpendicular to the direction of the interface between the tunnel film and the free layer or the fixed layer.

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