JP2013235601A - Layout design method, device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for more properly performing detailed layout design.SOLUTION: A layout design method includes: a process P1 in which a floor plan is performed; a process P2 in which each of modules, into which a semiconductor integrated circuit is divided through the floor plan, is divided into smaller sub-modules; a process P3 in which locations of module terminals for connection between the sub-modules are determined; a process P4 in which cell arrangement is determined for each of the sub-modules; a process P5 in which wiring for connection between cells is determined; and a process P6 in which manufacturing data for manufacturing the semiconductor integrated circuit is created. Division into the sub-modules is performed except grid point being basic units of the wiring.

Description

  The present invention relates to a layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit.

  There are many steps in designing a large scale integrated-circuit (LSI) that requires operation at a high frequency, such as a CPU. In recent years, layout design that handles the entire LSI has become difficult due to miniaturization due to progress in processing technology and an increase in circuit scale accompanying the miniaturization. For this reason, the layout design is usually divided into a plurality of modules and advanced in parallel for each module.

  At the initial stage of layout design, the module details are not determined. For this reason, a floor plan is usually created manually in consideration of the circuit scale, rough signal flow, etc., and the approximate position and shape of each module are determined. In addition, in the floor plan, the position of the external terminal (module terminal) of the module serving as the module interface is determined. The module terminal is used for connection between modules or an external terminal of a chip.

  When adopting a design method in which layout design is performed by dividing into modules, it is necessary to review in order to optimize the position of the module terminals. As a method of performing the optimization, a rough route is preliminarily performed to optimize again a wiring having a large difference between the wiring length calculated from the determined route and the wiring length estimated from the distance between the module terminals. It is known that the route to be determined and actually set is limited to the approximate route.

  High-speed operation and miniaturization of processing make the influence of signal wiring delay serious. In addition, due to the presence of a coupling capacitance that is an inter-wiring capacitance generated between two parallel wires, a change in a signal flowing through one induces an electromotive force in the other, thereby generating crosstalk noise. The crosstalk noise is known to cause problems such as increased delay and malfunction. For these reasons, in recent years, there has been a demand for designs that take into account the occurrence of defects even at the initial stage of layout design.

  As a countermeasure against the crosstalk noise, the wiring interval is made wider. When the wiring is connected to the module terminals, the arrangement of the module terminals is usually changed accordingly.

  Here, a conventional layout design support apparatus that supports layout design by dividing a semiconductor integrated device into a plurality of modules will be specifically described with reference to a functional configuration diagram shown in FIG.

  This conventional layout design support device inputs a logically designed semiconductor integrated circuit, for example, a net list, disassembles the semiconductor integrated circuit into a plurality of modules by floor plan design, and determines cell arrangement and wiring for each module. Support detailed (implementation) design. For this purpose, a module shape determining unit 11, a schematic wiring unit 12, a terminal position adjusting unit 13, a module dividing unit 14, and a detailed design unit 15 are provided.

  The module shape determining unit 11 performs a floor plan for determining the shape and arrangement of the modules that divide the semiconductor integrated circuit according to the instructions of the designer. A module is a part of a semiconductor integrated circuit, and a signal determined by logic design is exchanged between the modules. The signals to be exchanged are automatically determined according to the assignment of functions to the modules. The schematic wiring unit 12 determines schematic wiring for transmitting and receiving signals between modules. The terminal position adjustment unit 13 adjusts (changes) the position of the module terminal whose arrangement range is limited by determining the schematic wiring. The module dividing unit 14 divides the semiconductor integrated circuit into a plurality of modules according to the floor plan result.

  FIG. 1 shows that three module data D1 are generated by dividing the semiconductor integrated circuit into three modules. The module data D1 includes a net list for the corresponding module, arrangement information indicating the arrangement of each module terminal, and arrangement information indicating the shape and arrangement of the module.

  The detailed design unit 15 performs detailed design for determining the arrangement and wiring of each cell indicated by the data D1 for each module data D1. Each design result is output as module data D2. For example, the data D2 is obtained by adding arrangement information indicating arrangement for each cell, wiring information indicating a route for each wiring, and the like to the module data D1. The wiring information for one wiring indicates the cell pin to which the wiring is connected, the path between the pins, and the like.

  FIG. 2 is a diagram illustrating an example of module division. This division example is a case where the semiconductor integrated circuit 30 is divided into four modules 31 to 34. In FIG. 2, the module is indicated as “BLOCK”.

  The module 32 shown in FIG. 2 is after the arrangement and wiring are determined. A rectangle hatched with “CL” indicates a cell, and a rectangle with “ST” indicates a site which is an area where the cells CL are collectively arranged. A solid line connecting cells CL existing in different sites ST indicates wiring.

  FIG. 3 is a diagram illustrating another example of module division. In this division example, the semiconductor integrated circuit 40 is divided into two modules 41 and 42. Also in FIG. 3, the module is described as “BLOCK”. A solid line separating modules 41 and 42 indicates a boundary.

  In the module 41, the cell is arranged at a position relatively away from the boundary with the module 42. Similarly, in the module 42, the cell is arranged at a position relatively away from the boundary. In this way, the distance between the adjacent cells CL is made larger in the direction perpendicular to the boundary so as to sandwich the boundary. This is because the space between the cells serves as a buffer region where the mutual wiring or the like does not affect other modules.

JP-A-8-44784 JP 2003-30266 A JP 2002-215704 A JP-A-10-116910 JP 2001-093980 A Japanese Patent Laid-Open No. 04-113473

  By performing a floor plan, it can be confirmed whether or not all functions can be realized in a desired chip area. When a useless area is likely to occur, the useless area can be reduced. For this reason, conventionally, floor plans have been made with an emphasis on minimizing the chip area. This is because by minimizing the chip area, the number of chips that can be collected from one semiconductor wafer is increased and productivity is improved.

  However, miniaturization due to progress in processing technology and an increase in circuit scale accompanying the miniaturization have a great influence on the implementation of detailed design for determining cell arrangement and wiring. Specifically, the increase in the circuit scale makes the processing time required for carrying out the detailed design longer. Miniaturization of processing makes optimal wiring more difficult. In order to perform optimal wiring, it is necessary to more appropriately determine the arrangement of module terminals. For this reason, it is considered that a design that considers the detailed design should be performed in the previous stage of the detailed design.

  An object of the present invention is to provide a technique for enabling a detailed design of a layout to be implemented more appropriately.

  In one system to which the present invention is applied, in order to support layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit, grid points serving as basic units of wiring are divided when the semiconductor integrated circuit is divided. Boundary setting means for setting the boundary avoiding, dividing means for dividing the semiconductor integrated circuit into a plurality of modules along the boundary set by the boundary setting means, and cells in the module for each module divided by the dividing means And detailed design means for carrying out detailed design of the layout for determining the layout and wiring.

  The number of grid points that cannot be used can be suppressed by setting the module boundaries while avoiding the grid points that are the basic unit of wiring. By controlling the number of grid points, the detailed layout design can be implemented more appropriately. A cell is a component of a semiconductor integrated circuit, and includes functional blocks that are past design assets.

  When the present invention is applied, detailed layout design can be implemented more appropriately.

It is a functional block diagram of the conventional layout design support apparatus. It is a figure which shows the module division example. It is a figure which shows another example of module division. It is a figure which shows the schematic flow of the layout design realizable by application of this embodiment. It is a functional block diagram of the layout design support apparatus by this embodiment. It is explanatory drawing of the division method of a module. It is explanatory drawing of the setting method of the boundary divided | segmented into a block. It is explanatory drawing of the block (module) terminal arrange | positioned for the connection between blocks. It is explanatory drawing of the arrangement | positioning prohibition range mapped (the 1). It is explanatory drawing of the arrangement | positioning prohibition range mapped (2) It is explanatory drawing of the method of setting the area of the wiring which passes a boundary. It is explanatory drawing of the prediction method of wiring length. It is a figure which shows the example of the content of a terminal position control table. It is explanatory drawing of the example of arrangement | positioning of a block terminal. It is a flowchart of a prohibition mapping process. It is a flowchart of a cell prohibition setting process. It is a flowchart of a wire / via prohibition setting process. It is a flowchart of a net (Net) section length calculation process. It is a flowchart of a terminal position allocation process. It is a figure which shows an example of the hardware constitutions of the computer which can apply this invention.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
FIG. 4 is a diagram showing a schematic flow of layout design that can be realized by applying the present embodiment.

  In the present embodiment, as shown in FIG. 4, a step P1 for performing a floor plan for dividing a semiconductor integrated circuit into a plurality of modules, a smaller module (hereinafter referred to as “sub-module”) for each module divided by the floor plan. Step P2 for determining the position of the module terminal for connection between the submodules, Step P4 for determining the arrangement of the cells for each submodule, and Step P5 for determining the wiring connecting the cells, A process P6 for creating manufacturing data for manufacturing a semiconductor integrated circuit is performed. Actually, the processes P1 to P5 are repeatedly performed as needed to cope with the found defects and design changes.

  Steps P4 and P5 are performed as a detailed design. In this embodiment, the module obtained by the floor plan is further divided into sub-modules, and detailed design is performed. The processing time required for determining the wiring increases exponentially as the number of cells (pins provided in the cells) increases. For this reason, by dividing into sub-modules, the wiring can be determined in a shorter processing time. Even if the division into sub-modules and the determination of the position of the module terminal performed in accordance with the division are performed, the entire processing time is greatly reduced. The cell here is a generic term for components of a semiconductor integrated circuit that has been logically designed, and includes functional blocks (IP: Intelligent Property) that are past design assets.

  FIG. 5 is a functional configuration diagram of the layout design support apparatus according to the present embodiment. This layout design support device (hereinafter abbreviated as “support device”) is realized as a device that supports layout design for modules obtained by dividing floor plan results, that is, logically designed semiconductor integrated circuits (LSIs). Has been. In order to support the layout design, the area dividing unit 51, the existing wiring terminal converting unit 52, the prohibited mapping unit 53, the terminal side setting unit 54, the wiring length prediction unit 55, the allocation order determining unit 56, the terminal allocation unit 57, the module A division unit 58, a sub-module detailed design unit 59, and a flattening processing unit 60 are provided.

  The flat data D10 in FIG. 5 is data for one module, and corresponds to, for example, one of the three module data D1 shown in FIG. The area dividing unit 51 further divides the module indicated by the flat data D10 into a plurality of smaller submodules according to the instruction of the designer. Here, the further divided submodule is also referred to as a “block”.

  FIG. 6 is an explanatory diagram of a module dividing method. In the example shown in FIG. 6, a state in which the module 80 is divided into two blocks 81 and 82 is shown.

  FIG. 7 is an explanatory diagram of a method for setting a boundary to be divided into blocks. “+” Shown in FIG. 7 indicates a grid (GRID) point serving as a basic unit representing the minimum pitch interval between the arrangement and the wiring. The left side of FIG. 7 shows a conventional boundary setting method, and the right side of FIG. 7 shows the boundary setting method in the present embodiment.

  Conventionally, as shown on the left side of FIG. 7, the boundary line BL1 indicating the boundary is set as a straight line passing through adjacent grid points. On the other hand, in this embodiment, a straight line that does not pass through adjacent grid points is also handled as the boundary line BL2. For this reason, the position of the boundary in the horizontal direction is between grid points adjacent in the horizontal direction. The reason why the boundary is set between the grid points in this way is as follows.

  Since a grid point is a basic unit of wiring, a route is determined as a combination of straight lines passing through adjacent grid points. For this reason, when a boundary is set only by a straight line passing through adjacent grid points, the number of grid points that can be used as a path is reduced. The decrease in the number of grid points can be avoided by newly providing a buffer area as shown in FIG. 3, that is, adding grid points for the buffer area. However, newly providing a buffer area means that the floor plan result cannot be used as it is. Therefore, data representation or management becomes complicated.

  On the other hand, when a boundary is set between adjacent grid points, it is possible to avoid the occurrence of grid points that cannot be used as paths. The floor plan result can be used as it is. For this reason, a boundary is set between adjacent grid points.

  On the right side of FIG. 7, the part extending in the horizontal direction of the boundary line BL2 is a straight line passing between adjacent grid points. This is because the designer determines that it is not necessary to set a boundary between adjacent grid points from one block having that portion as a boundary or two blocks adjacent to each other at the boundary. Whether or not to set a boundary between adjacent grid points may be determined individually by dividing the boundary into a plurality of parts. Hereinafter, the data indicating the set boundary is generically referred to as “boundary data”, and the aggregated boundary data is collectively referred to as “frame information”.

  In this embodiment, hierarchization is performed by further dividing a module into blocks (submodules). The hierarchization is eliminated by merging the divided blocks and flattened. The data thus flattened can be hierarchized again by the area dividing unit 51. This is why the data input to the area dividing unit 51 is the flat data D10.

  The flat data D10 normally includes wiring data indicating already determined wiring (existing wiring, determined by schematic design or detailed design). The already-wired terminal unit 52 extracts a section of wiring information (NET) passing through the boundary set for block division from the already determined wirings, and makes the section a terminal. Terminalization is performed according to the designer's choice.

  FIG. 8 is an explanatory diagram of block (module) terminals arranged for connection between blocks. W1 is a wiring passing through the boundary between the blocks, and t1 is a block terminal arranged at the boundary position on the wiring W1.

  The width in the direction orthogonal to the boundary line of the block terminal t1 is the distance between the grid points closest to the boundary line in each of the two blocks. As a result, even when the wiring can be handled only by coordinates based on the grid points, the block terminals for connecting the blocks can be arranged on the boundary while securing the connection by the wiring passing through the boundary. For this reason, terminalization is performed between adjacent grid points across the boundary line in a direction orthogonal to the boundary line.

  In FIG. 8, the width in the direction parallel to the boundary line is the same width as the wiring W1, although the terminal portion is shown large in order to describe the block terminal.

  The prohibition mapping unit 53 maps the wiring prohibition range in the direction along the boundary line to the boundary in order to avoid occurrence of violations in violation of the design rule (design rule). Specifically, in the detailed design stage where the wiring is determined by the mapping, it is considered that there is a relatively high possibility that violations of design rules such as shorts and spacing (interval) violations will occur. The arrangement of the block terminals is prohibited by the arrangement of the mask pattern indicating the wiring prohibited range. For this reason, detailed design can be performed more appropriately. This has an effect in that the number of times the design is repeated is reduced, and the stage (process) in which the design is repeated is required later. A summary of the prohibited range data indicating the prohibited wiring range on the mapped boundary is hereinafter collectively referred to as “prohibited information”.

  9 and 10 are explanatory diagrams of the arrangement prohibition range to be mapped. FIG. 9 shows an arrangement prohibition range mapped by OB1 and OB2 which are obstacles (objects) existing within a certain range in the orthogonal direction of the boundary. FIG. 10 shows a large-scale cell CL11 such as a RAM and the like. The arrangement prohibition range mapped by CL12 existing in the vicinity in the orthogonal direction of the boundary is shown. In FIG. 9 and FIG. 10, the arrangement prohibition range is expressed by “x”.

  FIG. 15 is a flowchart of the prohibition mapping process. The prohibition mapping unit 53 is realized by the computer executing this process. Here, the prohibition mapping process will be described in detail with reference to FIG.

  First, in step S1, a cell prohibition setting process is performed in which a placement prohibition range is mapped by a cell (cell) including an obstacle present near the boundary, a circuit cell such as an AND (logical product) gate, or a macro cell such as a RAM. To do. In the subsequent step S2, a wire (wire) / via prohibition setting process for mapping an arrangement prohibition range by a wiring existing within a certain range from the boundary or a via hole (via hole) connecting the wiring layers is executed. After the execution, the prohibition mapping process is terminated.

  FIG. 16 is a flowchart of the cell prohibition setting process executed as step S1. Next, the cell prohibition setting process executed as a subroutine process in the prohibition mapping process will be described in detail with reference to FIG.

  In this setting process, in addition to the frame information D41, cell extraction range information D42 indicating the conditions of a cell for which the placement prohibited range is set based on the distance from the boundary, placement (coordinates), and wiring are prohibited for each cell. This is executed with reference to cell information D43 indicating the layer to be processed. The arrangement prohibition range is expressed by, for example, a coordinate range and a layer to which the coordinate range is applied. The arrangement prohibition range expressed as such, that is, prohibition range data, is stored as prohibition information D44.

  First, in step S11, block boundaries are extracted with reference to the frame information D41. The boundary extracted here is, for example, a portion (boundary line) expressed by a single straight line. In the next step S12, referring to the cell extraction range information D42 and the cell information D43, a cell that is a target for setting an arrangement prohibition range at the extracted boundary is extracted. After the extraction, the process proceeds to step S13.

  In step S13, it is determined whether or not the extracted cell is forbidden as a whole or partially as a range in the direction along the boundary. The determination can be made, for example, by preparing area information indicating a range in which wiring is prohibited in the direction along the boundary in the cell information D43 or a library for each cell. If the extracted cell area information does not indicate a range in which wiring is prohibited, the determination is no and the process proceeds to step S16. If the area information indicates a range where wiring is to be prohibited, the determination is yes and the process proceeds to step S14.

  In cell extraction, there are cases where a cell to be targeted cannot be extracted. In this case, although not particularly illustrated, the process proceeds from step S12 to step S17.

In step S14, the distance between the boundary and the cell is calculated. This distance corresponds to the distance L shown in FIG. After calculating the distance L, the process proceeds to step S15 to calculate a wiring prohibited range on the boundary. When the wiring prohibition range is h and the range indicated by the area information is H, the calculation is as follows: h = H−α × L (1)
To do. Here, α is a constant less than 1, and is 0 when the calculation result is negative. Thereby, the wiring prohibition range h is made narrower as the cell moves away from the boundary. The calculated wiring prohibition range h is stored as prohibition information D44 along with the layer where the extracted boundary exists. The process proceeds to step S16 after the storage.

  In step S16, it is determined whether or not there is another cell that is a target for setting the wiring prohibited range h. If there is another target cell, the determination is yes, the process returns to step S12, and the target cell is extracted next. If there is no other target cell, the determination is no and the process proceeds to step S17.

  In step S17, it is determined whether there is another target boundary (boundary line). If there is another target boundary, the determination is Yes, the process returns to step S11, and the next target boundary is extracted. If there is no other target boundary, the determination is no, and the cell prohibition setting process ends here.

  FIG. 17 is a flowchart of the wire / via prohibition setting process executed as step S2 in the prohibition mapping process shown in FIG. Next, the wire / via prohibition setting process will be described in detail with reference to FIG. Wiring and via holes are treated as obstacles as shown in FIG. The obstacle may be other than wiring and via holes.

  In this setting process, in addition to the frame information D41, forbidden extraction range information D51 indicating a condition of an obstacle (in this case, a wiring or a via hole) for which a placement prohibited range is set according to the distance from the boundary, This is executed with reference to wire / via information D52 indicating the shape, arrangement (coordinates), and formed layer for each via hole. The arrangement prohibition range is stored as prohibition information D44.

  First, in step S21, block boundaries are extracted with reference to the frame information D41. In the next step S22, with reference to the prohibition extraction range information D51 and the wire / via information D52, a wiring or via hole that is a target for setting a placement prohibition range at the extracted boundary is extracted. After the extraction, the process proceeds to step S53, where a range in the direction along the boundary of the extracted wiring or via hole is set as a wiring prohibition range, and is stored as prohibition information D44 together with the extracted layer. The process proceeds to step S24 after the storage.

  In the extraction of the obstacles, there are cases where the obstacles to be targeted cannot be extracted as in the case of the cell. In this case, although not particularly illustrated, the process proceeds from step S22 to step S25.

  In step S24, it is determined whether or not there is another target wire or via hole. If there is no other target among the wires and via holes indicated by the wire / via information D52, the determination is no and the process proceeds to step S25. If there is another target wire or via hole, the determination is yes and the process returns to step S22, and the target wire or via hole is extracted next.

  In step S25, it is determined whether or not there is another target boundary (boundary line). If there is another target boundary, the determination is yes, the process returns to step S21, and the target boundary is extracted next. If there is no other target boundary, the determination is no, and the wire / via prohibition setting process ends here.

  In this way, the range for prohibiting wiring on the boundary between blocks is automatically set and stored as prohibition information D44. By using the prohibition information D44 for wiring design, more appropriate wiring can be determined.

  The terminal side setting unit 54 sets the arrangement of block terminals that connect blocks, that is, a section of wiring that passes through a boundary to connect cells.

  The wiring section is set by extracting an output pin of a cell that outputs a signal to a cell of another block in the block of interest. When such an output pin does not exist, an input pin of a cell to which a signal output from a cell of another block is input is extracted. In order to minimize the wiring delay, the arrangement of the block terminals is set with priority given to a pin predicted to have a short wiring length within a group of one or more pins obtained by such extraction. Assuming a rectangle connecting two pins, the target position of the block terminal is set to a portion where the rectangle intersects the boundary. When there are a plurality of boundary portions intersecting with the rectangle, the one with the higher degree of freedom is selected and set. The wiring length can also be estimated assuming the rectangle.

  FIG. 11 is an explanatory diagram of a method of setting a section of wiring that passes through the boundary. The example shown in FIG. 11 is a case where the module 1100 is divided into blocks 1101 and 1102. Two cells CL 21 and 22 are arranged in the block 1101, and two cells CL 31 and 32 are arranged in the block 1102. With reference to this FIG. 11, the position setting of the block terminal performed as mentioned above is demonstrated concretely. Here, it is assumed that the output pin Aa of the cell CL21 is connected to the input pin Bc of the cell CL31 in the block 1102, and the input pin Ab of the cell CL22 is connected to the input pin Bd of the cell CL32 in the block 1102. That is, it is assumed that two wirings are performed between the blocks 1101 and 1102. It is assumed that the cells CL21, 22, 31, and 32 are arranged at the positions shown in FIG. “LSG” shown in FIG. 11 is an abbreviation for layout subgroup.

  In the two wirings shown in FIG. 11, the wiring length between the pin Aa and the pin Bc is shorter than the wiring length between the pin Ab and the pin Bd. For this reason, the target positions of the block terminals are set with priority between the pins Aa and Bc in the two wirings.

  A rectangle connecting the pin Aa and the pin Bc is shown on the right side of FIG. The boundary portion indicated by the rectangle is set as the target position of the block terminal.

  On the other hand, although not particularly illustrated, the rectangle connecting the pin Ab and the pin Bd intersects the boundary line indicated by two straight lines. For this reason, a higher degree of freedom is selected from two boundary portions intersecting with the rectangle.

  The degree of freedom is determined by paying attention to, for example, the length of the boundary portion or the number of grid points that can be used in a route passing through the boundary portion. Thereby, the longer boundary portion or the larger number of grid points is regarded as having a high degree of freedom, and the target position of the grid terminal is set. At this time, since the target positions of other grid terminals that have already been set exist, the setting is performed while avoiding the existing target positions.

  The wiring length prediction unit 55 obtains a predicted wiring length by using the setting result of the target position of the grid terminal. A method for predicting the wiring length will be specifically described with reference to an explanatory diagram shown in FIG.

  In order to further reduce the wiring delay, it is desirable to perform wiring in the shortest time, in other words, avoid unnecessary detours. When crosstalk noise is taken into consideration, it is desired that the length of the portion where the two wirings are parallel is made shorter or the distance between the wirings is made larger as the portion becomes longer. For this reason, the present embodiment assumes a rectangle connecting two pins, and focuses on the length Lv of the portion where the rectangle intersects the boundary and the length Lh in the direction orthogonal to the boundary. . In the case where the length Lv is extremely short, there is a high possibility of detouring unless priority is given to the setting of the target position of the block terminal. On the other hand, in the case where the length Lv is long, the possibility of detouring is reduced. For this reason, it is unlikely that the setting priority is low. For this reason, the shortest path can be secured, that is, detouring can be suppressed by considering the length Lv.

  On the other hand, the influence of noise (crosstalk noise) generated between two parallel wires increases as the length of the parallel portion increases and the interval decreases. The noise or an increase in delay due to noise generates an error. Therefore, the length Lh is used as an index indicating the possibility of such an error occurring. Thereby, the wiring length prediction unit 55 calculates the lengths Lv and Lh for each wiring passing through the boundary. These lengths Lv and Lh are hereinafter collectively referred to as “section length”.

  FIG. 18 is a flowchart of net (Net) section length calculation processing executed to calculate the lengths Lv and Lh, that is, the section length. Here, the calculation process will be described in detail with reference to FIG.

  This calculation process is executed with reference to the cell information D43 in addition to the net list (NetList) D61 and the frame information D41 shown in FIG. This netlist D61 reflects, for example, block division. FIG. 18 shows an extracted process executed to calculate the length of one section.

  First, in step S31, all the wirings (nets) are extracted with reference to the net list D61, and sorted by block with reference to, for example, the frame information D41. In a succeeding step S32, a cell pin (indicated by “terminal” in the drawing) connected by wiring is selected, and the position of the pin is extracted. The position is extracted with reference to, for example, the cell information D43 and a library storing information related to the physical shape of each cell. The process proceeds to step S33 after the position is extracted.

  In step S33, it is determined whether or not the pin whose position has been extracted is connected to another block. If it can be confirmed from the netlist D61 that the pin is connected to the pin of a cell existing in another block, the determination is yes and the process proceeds to step S34. If it is confirmed that the pin is connected to a pin of a cell in the same block, the determination is no, the process returns to step S32, another wiring is selected, and the pin connected by the wiring is selected. Extract position.

  When the process proceeds from step S33 to step S32, it is not always possible to select another target wiring. For this reason, although not particularly illustrated, in step S32, if there is no remaining target wiring, the section length calculation process is terminated here.

  In step S34, another pin (indicated as “terminal” in the figure) connected by wiring is selected. In the next step S35, a rectangle connecting two pins is assumed, the frame information D41 is referred to, the lengths Lv and Lh are calculated as the section length from the rectangle, and the section length calculated together with the wiring information indicating the wiring is calculated. Saved as net section length information D62. By the storage, a series of processes relating to the calculation of the length of one section is completed. Actually, after saving the section length, it is determined whether or not there is another target wiring. If there is another target wiring and the determination is Yes, the process returns to step S32. Conversely, if the determination is No because there is no other target wiring, the net section length calculation process is terminated here.

  The allocation order determination unit 56 determines the processing order of the block terminals from the lengths Lv and Lh calculated by the wiring length prediction unit 55 as the section length. Since the target position is preferentially assigned to the first processing, the determination of the processing order corresponds to the setting of the priority order.

  The processing order is made faster as the length Lv is shorter and the length Lh is longer. These two lengths Lv and Lh are both important indexes for determining the processing order. For this reason, the processing order uses, for example, a table in which priority is defined for each combination of lengths Lv and Lh, a table in which a range in which one of lengths Lv and Lh should be emphasized, or lengths Lv and Lh are used. Formulas for calculating the priority are prepared and determined using a table or formula.

  The terminal allocation unit 57 arranges block terminals on the block boundaries according to the processing order determined by the allocation order determination unit 56. In the present embodiment, with reference to the terminal position control table as shown in FIG. 13, the layer (wiring layer) targeted for wiring of the length Lh calculated by the wiring length predicting unit 55, and nearby wiring The assigned pitch, which is the target interval, is determined, and a place where the block terminal can be arranged is selected.

  In the terminal position control table, as shown in FIG. 13, a target wiring layer of wiring (arrangement of block terminals) and an assigned pitch are defined for each wiring length (range). The range of wiring length and the assigned pitch are defined by values expressed by the number of grid points. The wiring layer is expressed by L1-8. The higher the number following L, the higher the upper layer. The assigned pitch assumes wirings having the same wiring length range. Between wirings having different wiring lengths (length Lv), an allocation pitch with a smaller wiring length is applied. For example, for a wiring having a wiring length exceeding 1001 grid and a wiring having a wiring length in the range of 501 to 1000, 3 grids are applied as the assigned pitch. This is because the influence of noise varies depending on the length of the parallel portions. Since the terminal position control table requires a larger assigned pitch as the length of the parallel portion becomes longer, the arrangement position of the block terminals can be controlled so that no error occurs.

  In the terminal position control table, the higher the wiring length, the more the wiring in the upper layer is required. This is because the wiring delay generally decreases as the upper layer is reached.

  FIG. 14 is an explanatory diagram of an arrangement example of block terminals. In FIG. 14, the hatched rectangles all indicate the wiring of the same wiring layer.

  As described above, a higher priority is assigned as the length Lh is longer. For this reason, an arrangement position is assigned from a wiring having a longer wiring length. As a result, wirings having a long wiring length are arranged at a large allocation pitch, and wirings having a short wiring length are allocated to vacant places. As a result, even in a situation where wiring crossing the boundary is arranged at a high density, an arrangement in which wiring delay and the length of the parallel part are optimized can be obtained as shown in FIG.

  FIG. 19 is a flowchart of the terminal position assignment process. This assignment process is a process for deciding the processing order of wiring (block terminals) and assigning the arrangement positions of the block terminals. The allocation order determination unit 56 and the terminal allocation unit 57 are realized by executing this allocation process. Next, this allocation process will be described in detail with reference to FIG.

  First, in step S41, the processing order is determined by referring to the net section length information D62 and sorting the wiring information (block terminals) in order of increasing section length for each block, for example. The order of processing depends on the method for obtaining the priority from the section length. For example, the highest priority is given to the length Lv that is equal to or shorter than the predetermined length, and the priority is given to the length Lh that is longer than the predetermined length as the length Lh increases. It may be determined by increasing the degree. After the processing order is determined, the process proceeds to step S42.

  In step S42, wiring information (block terminal) to be processed is selected according to the processing order, and a target wiring layer and assigned pitch are determined with reference to the terminal position control table D71. In the next step S43, referring to the prohibition information D44, a search is performed for a place where the block terminals can be arranged with the determined wiring layer and the assigned pitch. In the next step S44, it is determined whether or not the target wiring layer can be arranged. If there is a vacant place in the wiring layer and an appropriate allocation pitch can be secured at the place, the determination is yes and the process proceeds to step S46. If there is no vacant place in the target wiring layer or an appropriate allocation pitch cannot be secured, the determination is no, and after changing the target wiring layer in step S45, the process returns to step S43, Search for the changed wiring layer.

  In step S46, the position of the block terminal is determined from the searched place, and is stored as terminal position information D72 together with the wiring information, for example. In a succeeding step S47, it is determined whether there is another block terminal whose arrangement position is to be determined. If any of the wiring information sorted in step S41 is not processed, the determination is yes, the process returns to step S42, and the subsequent processing is executed in the same manner. If there is no unprocessed wiring information among the sorted wiring information, the determination is no and the terminal position assignment processing is terminated here.

  The module dividing unit 58 divides the flat data D10 according to the block division, and combines the sub-module data D20 together with the frame information D41, cell information D43, prohibition information D44, wire / via information D52, terminal position information D72, and the like. create. In FIG. 5, a total of three submodule data D20 are created.

  The sub-module detailed design unit 59 performs detailed design for determining cell arrangement and wiring for each small module data D20. The position assigned to the block terminal is reflected in the determination of wiring.

  The small module data D20 used for the detailed design has a data amount significantly smaller than the flat data D10 due to block division. The time required to determine the wiring becomes exponentially longer depending on the number of wirings. For this reason, the total time required for the detailed design is shorter than the time required for the detailed design performed using the flat data D10. Further, since the data D10 is divided, parallel (distributed) processing becomes possible, so that the time required for detailed design can be further shortened. By reflecting the result of the detailed design in the submodule data D20, submodule data D30 is created.

  The assignment of the position to the block terminal is performed in consideration of the suppression of the occurrence of detours to be avoided and the suppression of the occurrence of violations. For this reason, detailed design can be implemented more appropriately. Since the occurrence of defects on the wiring is suppressed, the route for wiring can be quickly searched, and the frequency of changing the cell arrangement or the like can be suppressed. As a result, the time required for detailed design can be shortened.

  The flattening processing unit 60 merges the submodule data D30 and performs flattening to eliminate the hierarchy generated by dividing the module into blocks. The flat data D10 obtained by the flattening can be used as input data for the region dividing unit 51 when any correction or design change is performed.

  In the support device having the above-described functional configuration, the process P2 is performed by the area dividing unit 51. The process P3 is performed by the existing wiring terminal conversion unit 52, the prohibition mapping unit 53, the terminal side setting unit 54, the wiring length prediction unit 55, the allocation order determination unit 56, and the terminal allocation unit 57. Steps P4 and P5 are performed by the submodule detailed design unit 59. Process P6 corresponds to merging flat data D10 that does not need to be corrected.

  FIG. 20 is a diagram illustrating an example of a hardware configuration of a computer to which the present invention is applicable. Here, with reference to FIG. 20, a configuration of a computer that can be used as a support apparatus will be described in detail.

  The computer shown in FIG. 20 includes a CPU 91, a memory 92, an input device 93, an output device 94, an external storage device 95, a medium drive device 96, and a network connection device 97, which are connected to each other via a bus 98. It has become. The configuration shown in the figure is an example, and the present invention is not limited to this.

The CPU 91 controls the entire computer.
The memory 92 is a memory such as a RAM that temporarily stores the program or data stored in the external storage device 95 (or the portable recording medium M during program execution, data update, and the like. The entire program is controlled by reading the program into the memory 92 and executing it.

  The input device 93 is an interface connected to an operation device such as a keyboard and a mouse. A user operation on the operation device is detected, and the detection result is notified to the CPU 91.

  The output device 94 is a display control device connected to, for example, a display device. The network connection device 97 is for communicating with an external device via a communication network such as an intranet or the Internet. The external storage device 95 is, for example, a hard disk device. Mainly used for storing various data and programs.

  The medium driving device 96 accesses a portable recording medium M such as an optical disk or a magneto-optical disk.

  The flat data D10 can be stored in the recording medium M via the external storage device 95 or the medium driving device 96, for example, when the CPU 81 executes a floor planner that is a program for a floor plan. It can also be acquired from an external device via the network connection device 97. Submodule data D20 and D30, frame information D41, cell extraction range information D42, cell information D43, prohibition information D44, prohibition extraction range information D52, terminal position control table D71, etc. are also stored in external storage device 95 or medium drive device 96. Through the recording medium M.

  The area dividing unit 51, the existing wiring terminal converting unit 52, the prohibited mapping unit 53, the terminal side setting unit 54, the wiring length predicting unit 55, the allocation order determining unit 56, the terminal allocation unit 57, the module dividing unit 58, the sub shown in FIG. The module detailed design unit 59 and the flattening processing unit 60 can be realized by causing the CPU 91 to execute one program. In this embodiment, since detailed design is performed using a well-known technique, the area dividing unit 51, the existing wiring terminal conversion unit 52, the prohibition mapping unit 53, the terminal side setting unit 54, the wiring length prediction unit 55, The allocation order determining unit 56, the terminal allocation unit 57, and the module dividing unit 58 are realized by one program (hereinafter referred to as “layout design support program”), and the sub-module detailed design unit 59 is realized by executing a tool for detailed design. I am letting. The layout design support program may be stored in the external storage device 95 or the recording medium M, but may be acquired from an external device via the network connection device 97 as needed.

  In the present embodiment, the setting of the boundary avoiding the grid points is performed for dividing the module into blocks. However, the boundary may be used for dividing into modules. Similarly, the block terminal position assignment method and the wiring prohibition range setting may be employed for division into modules.

The following additional notes are further disclosed with respect to the embodiment including the above modification.
(Appendix 1)
In a method for performing layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
A first step of dividing a first module obtained by dividing the semiconductor integrated circuit into a plurality of second modules;
A second step of carrying out a detailed design of a layout for determining the arrangement and wiring of cells in the second module for each second module divided by the first step;
A layout design method comprising:
(Appendix 2)
In the first step, the division into the second module sets a boundary with another adjacent second module, avoiding a grid point as a basic unit of the wiring.
The layout design method according to appendix 1, wherein:
(Appendix 3)
In the first step, when there is a wiring passing through the boundary, a module terminal having a width connecting two adjacent grid points on the boundary in the orthogonal direction of the boundary is disposed on the boundary. ,
The layout design method according to appendix 1, wherein:
(Appendix 4)
In the first step, when there is a wiring that passes through the boundary, on the basis of the location between the two pins connected by the wiring, the position of the module terminal arranged on the boundary is allocated for the wiring. Determine the priority, and assign the position of the module terminal for each wiring according to the priority;
In the second step, the detailed design is performed using a position assigned to the module terminal.
The layout design method according to appendix 1, wherein:
(Appendix 5)
The priority is determined based on a width connecting the two pins and a width of the rectangle intersecting the boundary and a width of the rectangle in a direction orthogonal to the boundary.
The layout design method according to appendix 4, characterized in that:
(Appendix 6)
In the first step, based on an obstacle on the wiring arranged in the vicinity of the boundary, a prohibited range in which the module terminal is not arranged is set on the boundary, and the module terminal is avoided by avoiding the prohibited range. Assign a position,
In the second step, the detailed design is performed using a position assigned to the module terminal.
The layout design method according to appendix 1, wherein:
(Appendix 7)
The obstacle includes a cell in which the arrangement is determined, an existing wiring, and a via hole.
The layout design method according to appendix 6, wherein:
(Appendix 8)
In a method for performing layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
When dividing the semiconductor integrated circuit, a first step of setting a boundary avoiding a grid point serving as a basic unit of the wiring;
A second step of dividing the semiconductor integrated circuit into a plurality of modules along the boundary set by the first step;
For each module divided in the second step, a third step of performing detailed design of a layout for determining the arrangement and wiring of cells in the module;
A layout design method comprising:
(Appendix 9)
In a method for performing layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
A first step of setting a boundary for dividing the semiconductor integrated circuit;
When there is a wiring that passes through the boundary set in the first step, the position of the module terminal to be arranged on the boundary is allocated for the wiring based on the two pins connected by the wiring. A second step of assigning a position of the module terminal for each wiring according to the priority;
Third step of performing detailed design of layout for determining the arrangement and wiring of the cells using the positions assigned to the module terminals for each module obtained by dividing the semiconductor integrated circuit along the boundary When,
A layout design method comprising:
(Appendix 10)
In a method for performing layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
A first step of setting a boundary for dividing the semiconductor integrated circuit;
A module for connection between two modules obtained by extracting an obstacle on the wiring arranged in the vicinity of the boundary set in the first step and dividing along the boundary based on the obstacle A second step of setting a prohibited range on which the terminal is not disposed on the boundary, and assigning the position of the module terminal while avoiding the prohibited range;
Third step of performing detailed design of layout for determining the arrangement and wiring of the cells using the positions assigned to the module terminals for each module obtained by dividing the semiconductor integrated circuit along the boundary When,
A layout design method comprising:
(Appendix 11)
In a layout design support apparatus for supporting layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
First dividing means for dividing a first module obtained by dividing the semiconductor integrated circuit into a plurality of second modules;
For each second module divided by the first dividing means, second dividing means for carrying out detailed design of a layout for determining the arrangement and wiring of cells in the second module;
A layout design support apparatus comprising:
(Appendix 12)
In a layout design support apparatus for supporting layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
When dividing the semiconductor integrated circuit, boundary setting means for setting a boundary avoiding a grid point as a basic unit of the wiring,
A dividing unit that divides the semiconductor integrated circuit into a plurality of modules along the boundary set by the boundary setting unit;
For each module divided by the dividing means, detailed design means for carrying out detailed design of a layout for determining the arrangement of cells and wiring in the module;
A layout design support apparatus comprising:
(Appendix 13)
In a layout design support apparatus for supporting layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
Boundary setting means for setting a boundary for dividing the semiconductor integrated circuit;
When there is a wiring that passes through the boundary set by the boundary setting means, the position of the module terminal arranged on the boundary is allocated for the wiring based on the two pins connected by the wiring. Position allocating means for determining priority and allocating the position of the module terminal for each wiring according to the priority;
Detailed design means for carrying out detailed design of a layout for determining the arrangement of cells and the wiring by using the position assigned to the module terminal for each module obtained by dividing the semiconductor integrated circuit along the boundary ,
A layout design support apparatus comprising:
(Appendix 14)
In a layout design support apparatus for supporting layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
Boundary setting means for setting a boundary for dividing the semiconductor integrated circuit;
A module terminal for connecting two modules obtained by extracting an obstacle on the wiring arranged in the vicinity of the boundary set by the boundary setting means and dividing along the boundary based on the obstacle A position allocating means for setting a prohibited range on the boundary and allocating the position of the module terminal while avoiding the prohibited range;
Detailed design means for carrying out detailed design of a layout for determining the arrangement of cells and the wiring by using the position assigned to the module terminal for each module obtained by dividing the semiconductor integrated circuit along the boundary ,
A layout design support apparatus comprising:
(Appendix 15)
In a layout design support program that realizes a layout design support device that supports layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit by installing in an information processing device,
In the information processing apparatus,
When dividing the semiconductor integrated circuit, setting a boundary avoiding a grid point as a basic unit of the wiring; and
Dividing the semiconductor integrated circuit into a plurality of modules along the boundary set by the setting step;
Layout design support program to execute.
(Appendix 16)
In a layout design support program that realizes a layout design support device that supports layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit by installing in an information processing device,
In the information processing apparatus,
Setting a boundary for dividing the semiconductor integrated circuit;
When there is a wiring that passes through the boundary set by the setting step, the position of the module terminal to be arranged on the boundary is allocated for the wiring on the basis of between the two pins connected by the wiring. Determining a priority and assigning the position of the module terminal for each wiring according to the priority;
Layout design support program to execute.
(Appendix 17)
In a layout design support program that realizes a layout design support device that supports layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit by installing in an information processing device,
In the information processing apparatus,
Setting a boundary for dividing the semiconductor integrated circuit;
Module terminals for connection between two modules obtained by extracting an obstacle on the wiring arranged in the vicinity of the boundary set by the setting step and dividing along the boundary based on the obstacle Setting a prohibited range on the boundary, and assigning the position of the module terminal avoiding the prohibited range; and
Layout design support program to execute.

REFERENCE SIGNS LIST 51 area division unit 52 device wiring terminal unit 53 prohibition mapping unit 54 terminal side setting unit 55 wiring length prediction unit 56 allocation order determination unit 57 terminal allocation unit 58 module division unit 59 submodule detailed design unit 60 flattening processing unit

Claims (5)

In a method for performing layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
On the computer,
When dividing the semiconductor integrated circuit, a first step of setting a boundary avoiding a grid point serving as a basic unit of the wiring;
A second step of dividing the semiconductor integrated circuit into a plurality of modules along the boundary set by the first step;
For each module divided in the second step, a third step of performing detailed design of a layout for determining the arrangement and wiring of cells in the module;
A layout design method characterized in that In a method for performing layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
On the computer,
A first step of setting a boundary for dividing the semiconductor integrated circuit;
When there is a wiring that passes through the boundary set in the first step, the position of the module terminal to be arranged on the boundary is allocated for the wiring based on the two pins connected by the wiring. A second step of assigning a position of the module terminal for each wiring according to the priority;
Third step of performing detailed design of layout for determining the arrangement and wiring of the cells using the positions assigned to the module terminals for each module obtained by dividing the semiconductor integrated circuit along the boundary When,
A layout design method characterized in that In a method for performing layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
On the computer,
A first step of setting a boundary for dividing the semiconductor integrated circuit;
A module for connection between two modules obtained by extracting an obstacle on the wiring arranged in the vicinity of the boundary set in the first step and dividing along the boundary based on the obstacle A second step of setting a prohibited range on which the terminal is not disposed on the boundary, and assigning the position of the module terminal while avoiding the prohibited range;
Third step of performing detailed design of layout for determining the arrangement and wiring of the cells using the positions assigned to the module terminals for each module obtained by dividing the semiconductor integrated circuit along the boundary When,
A layout design method characterized in that In a layout design support apparatus for supporting layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit,
When dividing the semiconductor integrated circuit, boundary setting means for setting a boundary avoiding a grid point as a basic unit of the wiring,
A dividing unit that divides the semiconductor integrated circuit into a plurality of modules along the boundary set by the boundary setting unit;
For each module divided by the dividing means, detailed design means for carrying out detailed design of a layout for determining the arrangement of cells and wiring in the module;
A layout design support apparatus comprising: In a layout design support program that realizes a layout design support device that supports layout design for determining the arrangement and wiring of cells constituting a semiconductor integrated circuit by installing in an information processing device,
In the information processing apparatus,
Setting a boundary for dividing the semiconductor integrated circuit;
When there is a wiring that passes through the boundary set by the setting step, the position of the module terminal to be arranged on the boundary is allocated for the wiring on the basis of between the two pins connected by the wiring. Determining a priority and assigning the position of the module terminal for each wiring according to the priority;
Layout design support program to execute.