JP2013222365A - Testing apparatus for semiconductor integrated circuit, test method for semiconductor integrated circuit, and test program for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic verification method, a verification circuit information extraction program, and a verification circuit modification apparatus, which allow a verification circuit to be applied for both a logic simulator and a format verification tool that support different languages so as to perform efficient testing.SOLUTION: A testing apparatus includes: a verification circuit information extraction unit that extracts verification circuit information from a first verification circuit that is a reuse source; and a verification circuit conversion unit that generates a second verification circuit in a programming language that is specified by using the extracted verification circuit information.

Description

  The present invention relates to a semiconductor integrated circuit test apparatus, a semiconductor integrated circuit test method, and a semiconductor integrated circuit test program.

  Generally, in the conventional logic verification method, a logic simulation as shown in FIG. 1 or a formal verification as shown in FIG. 2 is performed. In each case, a verification circuit composed of checkers such as assertions to check the correctness of the circuit is input to a dedicated logic simulator and format verification tool, and violations are automatically detected and output as verification results. ing. This verification circuit is created in a programming language for creating a verification circuit.

JP 2008-47053 A

However, there are a plurality of verification circuit creation programming languages, and only a specific verification circuit creation programming language may be used depending on the logic simulator and format verification tool used. For example, when it is desired to use a design asset created in the past, it may be created in a language that is not supported by currently distributed logic simulators. Therefore, there has been a problem that the verification circuit created as shown in FIGS. 3 and 4 cannot be diverted with another logic simulator or a format verification tool.

Patent Document 1 describes that an assertion used in a lower level concept (RTL) is generated from a higher level concept (ESL) in the same programming language, but there is no description about conversion to a different language.

  The present invention provides a logic verification method, a verification circuit information extraction program, and a verification circuit for a semiconductor integrated circuit that can be used even between logic simulators and formal verification tools that support different languages and can perform an efficient test. An object is to provide a changing device.

In order to achieve the above object, a semiconductor integrated circuit test apparatus according to the present invention uses a verification circuit information extraction unit that extracts verification circuit information from a first verification circuit as a diversion source, and the extracted verification circuit information. A verification circuit conversion unit that generates a second verification circuit in a designated programming language.

  According to the present invention, since a verification circuit can be used between logic simulators and format verification tools that support different languages, an efficient test can be performed.

It is a conventional logic simulation execution flowchart. It is a conventional format verification implementation flowchart. It is a figure which shows diversion of the verification circuit in the conventional logic simulation. It is a figure which shows diversion of the verification circuit in the conventional format verification. It is a block diagram of the test apparatus based on the Example of this invention. It is an operation | movement diagram of the verification circuit information extraction program based on the Example of this invention. It is operation | movement explanatory drawing of the logic simulation in embodiment. It is operation | movement explanatory drawing of the format verification tool in embodiment. It is operation | movement explanatory drawing which concerns on a 2nd Example. It is operation | movement explanatory drawing which concerns on a 3rd Example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 5 is a configuration diagram of the test apparatus 10 according to the present invention, which is realized by using an information center apparatus such as a personal computer or a server. The CPU 11 executes various programs (verification circuit information extraction program 12, verification circuit conversion 13, logic simulator 14, and format verification tool 15) that are read from a ROM or the like (not shown) and expanded in the memory 11. Realize the function.

  As shown in FIG. 6, the verification circuit information extraction program 12 receives, for example, sampling event information, disable information, trigger information, temporal information, function event information, a verification circuit created in a specific verification circuit creation programming language, The verification direction information is extracted.

  The verification circuit conversion program 13 generates a verification circuit using the information extracted by the verification circuit information extraction program 12 using another specified verification circuit creation programming language. The generated verification circuit and the verification circuit to be extracted are stored in the memory 12.

  The logic simulator 14 performs a simulation using a verification circuit, circuit data, and a test pattern. If a location that violates the contents of the verification circuit is not found in the circuit data, the verification result is determined to be Pass, and if a location that violates is found, it is determined to be Fail. After confirming the waveform or the like, the circuit that has been determined to be “Fail” is corrected by using an editor, and the test is performed by repeating the logic simulation and correction until it is determined to be “Pass”.

  The format verification tool 15 performs format verification using a verification circuit and circuit data. If a location that violates the contents of the verification circuit is not found in the circuit data, the verification result is determined to be Pass, and if a location that violates is found, it is determined to be Fail. After confirming the waveform or the like, the part circuit determined to be “Fail” is corrected by using an editor, and the test is performed by repeating the form verification and correction until it is determined to be “Pass”.

  Next, the logic simulation operation in this embodiment will be described using the logic simulation operation explanatory diagram shown in FIG.

  First, circuit data 16 is created by describing circuit specifications using an arbitrary program language. Subsequently, a verification scenario is described based on the circuit specifications, and a test pattern 17 is created. Sampling event information, disable information, trigger information, temporal information, function event information, verification direction information, etc. using the verification circuit information extraction program 12 from the original verification circuit 19 used in other logic simulations to be diverted The verification circuit information is extracted. Using the verification circuit conversion program 13 and the extracted verification circuit information, a new verification circuit 18 for the logic simulator used this time is created using a programming language designated by the operator.

  Verification is performed by inputting the created circuit data 16, test pattern 17, and new verification circuit 18 converted for the current logic simulation to the logic simulator 14. When Fail (warning) is reported in the logic simulation, the circuit data 16 is corrected. On the other hand, when Pass is reported, the logic simulation is terminated.

  Next, the operation of the format verification tool according to the present embodiment will be described with reference to the operation explanatory diagram of the format verification tool shown in FIG.

  First, circuit data 16 is created by describing circuit specifications using an arbitrary program language. Next, sampling event information, disable information, trigger information, temporal information, function event information, using the verification circuit information extraction program 12 from the original verification circuit 19 used in another format verification tool to be diverted, Verification circuit information such as verification direction information is extracted. Using the verification circuit conversion program 13 and the extracted verification circuit information, a new verification circuit 18 is created using a programming language designated by the operator.

  The created circuit data 16 and the new verification circuit 18 converted for the current formal verification tool are input to the formal verification tool 15, and comprehensive verification is performed based on the properties of the verification circuit. If a “Fail” is reported by the formal verification tool, the circuit data is corrected. On the other hand, if Pass is reported, the format verification tool is terminated.

As described above, according to the first embodiment, a common verification circuit can be easily diverted regardless of the programming language supported by the logic simulator or format verification tool used. The effect of improving work efficiency can be obtained. In addition, since a verification circuit that has already been used can be used, the reliability of the verification result can be improved.

[Second Embodiment]
The operation according to the second embodiment is shown in FIG. In the second embodiment, in addition to the verification circuit information extraction program 12 and the verification circuit conversion program 13 described in the first embodiment, an information confirmation program 20 is provided. The information confirmation program 20 detects and reports missing information by comparing the verification circuit information extracted from the verification circuit to be diverted with the extraction omission check list. If the shortage information is reported from the information confirmation program 20, based on the reported contents, a correction for adding a portion that was lacking in the original verification circuit is performed on the verification circuit. If insufficient information is not reported, a verification circuit in another programming language designated by the operator is generated using the verification circuit conversion program 13. Then, a test using a logic simulator or a verification tool is performed using the verification circuit in the same manner as in the first embodiment.

As described above, according to the second embodiment, by providing the information confirmation program 20 that reports the missing information, it becomes possible to find and correct the deficiencies of the original verification circuit. The quality of the verification circuit can be expected to be improved by other programming languages.

[Third Embodiment]
An operation according to the third embodiment is shown in FIG. The third embodiment is an example using a verification circuit conversion program 21 in which a verification circuit information changing function is added to the verification circuit conversion program 13 described in the second embodiment. By using the verification circuit conversion program 21 in this way, it is possible to add or change the function of the new verification circuit 22 converted from the diversion source verification circuit 19 using another programming language. Therefore, the contents of verification by the logic simulation 14 and the format verification tool 15 can be changed from those of the previous logic simulator using the original verification circuit 19 and controlled.

The verification circuit information can be changed by inputting the verification circuit conversion program 22 into a change information format in which the verification item name to be changed, the verification circuit information name, and the value of the verification circuit information after the change are described. As a result, the verification circuit 23 is generated in another programming language in which the verification content is changed.

As described above, according to the third embodiment, the verification circuit information changing function of the new verification circuit 23 is provided in the verification circuit conversion program 22, so that the verification circuit can be verified by using another programming language whose contents are changed. A circuit can be generated. Thereby, even when the circuit data of the diversion destination is changed, the verification circuit can be diverted, and the efficiency of the verification work can be expected.

For example, when a new function is added in addition to the function that has been supported by the updated standard, according to this method, the conventional function part is verified by the diverted verification circuit part. In addition to being able to do so, the lack of the original verification circuit 19 for verifying the added function can be found and added, so that the verification operation can be performed efficiently.

1 Test apparatus 10 CPU
11 Memory 12 Verification Circuit Information Extraction Program 13 Verification Circuit Conversion Program 14 Logic Simulator 15 Format Verification Tool 16 Circuit Data 17 Test Pattern 18 New Verification Circuit 19 Diversion Source Verification Circuit 20 Information Verification Program 21 New Verification Circuit 22 Verification Circuit Conversion Program 23 New Verification circuit

Claims (8)

In semiconductor integrated circuit testing equipment,
A verification circuit information extraction unit that extracts verification circuit information from the first verification circuit to be diverted;
A test apparatus comprising: a verification circuit conversion unit that generates a second verification circuit in a specified programming language using the extracted verification circuit information. 2. The semiconductor integrated circuit testing device according to claim 1, further comprising a verification processing unit that performs verification processing on a verification target circuit using the second verification circuit.   3. The semiconductor integrated circuit according to claim 1, further comprising a verification information confirmation unit that compares the verification circuit information confirmation information with the verification circuit information to detect an insufficient portion of the verification circuit information. Circuit testing equipment.   4. The semiconductor according to claim 1, wherein the verification circuit conversion unit generates the second verification circuit using verification circuit information change information and the verification circuit information. 5. Integrated circuit testing equipment.   The verification processing unit performs the verification process by determining whether or not a verification result using the input test data matches between the second verification circuit and the verification target circuit. The test apparatus for a semiconductor integrated circuit according to any one of claims 2 to 4.   5. The semiconductor integrated circuit according to claim 2, wherein the verification processing unit performs verification processing of the verification target circuit based on attribute information of the second verification circuit. 6. Testing equipment. In a test method of a semiconductor integrated circuit,
A verification circuit information extraction step for extracting verification circuit information from the first verification circuit to be diverted;
A test method for a semiconductor integrated circuit, comprising: a verification circuit conversion step of generating a second verification circuit in a specified programming language using the extracted verification circuit information. A program for causing a computer to test a semiconductor integrated circuit,
A verification circuit information extraction function for extracting verification circuit information from the first verification circuit to be diverted;
A test program for a semiconductor integrated circuit for causing a computer to realize a verification circuit conversion function for generating a second verification circuit in a designated programming language using extracted verification circuit information.