JP2013222255A - Method of evaluating use period of flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dynamically correct, detect, and evaluate the ideal use period of a flash memory.SOLUTION: The method of evaluating the use period of a flash memory includes: a step 11, in which the capacity of a memory block, a memory page, and a memory cell provided in the flash memory are detected and an ideal use period is calculated based on the structural form of the flash memory; a step S12, in which a spare area is formed in at least any one of the flash memory and a control center; a step S13, in which the control center generates a test command to transfer it to the flash memory, the flash memory performs a test based on the test command, and the flash memory performs feedback of test results to the spare area to form a corrected parameter; and a step S14, in which the control center obtains the corrected parameter of the spare area to selectively correct the ideal use period by using the corrected parameter.

Description

  The present invention relates to a flash memory usage period evaluation method, and more particularly, a control center dynamically corrects, detects, and evaluates an ideal lifetime of a flash memory in an electronic device. It is related to the method.

  Currently, NAND flash memories are widely applied to various electronic products such as tablet computers, smartphones, desktop computers, and notebook computers. In addition to having a function of storing data, a flash memory in an electronic product can also be used as a system boot code storage area such as an eMMC (embedded Multi Media Card) or an iSSD (integrated Solid State Drive).

  The flash memory stores data by holding charges by a floating gate. Generally, the flash memory executes commands such as erase, write, and read on the memory based on the command of the control chip, and the flash memory is subjected to an intense method using high piezoelectric impact. Changes the data storage state in the floating gate.

  Hereinafter, a multi-level cell flash memory (MLC flash memory) flash memory having a storage capacity of 4 GB will be described as an example. This multi-level cell flash memory uses a wear leveling technique because normal memory operations (for example, commands such as erasing, writing, and reading are performed on memory data) are performed nearly 3000 times. In this case, the used capacity of the flash memory is about 12,000 GB (4 GB × 3,000). Therefore, if 1G capacity is used every day, 12,000 days (12,000G / 1G) can be used, and if one year is calculated as 365 days, 32.87 years (12,000 days / 365 days) ) Can be used. That is, an ideal lifetime of the flash memory is 32.87 years.

  Further, when the flash memory is not used for a long period of time, it may deteriorate naturally and the data may spontaneously evaporate.

  The flash memory has advantages such as low manufacturing cost, low power consumption, and high reading speed. However, there is a drawback that the number of times of reading and writing is limited depending on the structure and operation method of the flash memory itself. For example, the above calculation is performed under optimum conditions. In practice, the period in which the flash memory can be used is ideal depending on conditions such as a difference in the usage habits of the user's flash memory and changes in the environment. May vary significantly from period of use.

  Therefore, there has been a need for a flash memory usage period evaluation method that solves the problems of the prior art that the flash memory usage period cannot be accurately predicted, and that accurately predicts the flash memory usage period.

  The object of the present invention is to dynamically modify, detect and evaluate the ideal lifetime of built-in or expanded flash memory of an electronic device by a control center. An object of the present invention is to provide a flash memory usage period evaluation method that accurately corrects an ideal usage period and accurately calculates a usable period of the flash memory.

  In order to solve the above problems, according to the first aspect of the present invention, the control center dynamically corrects, detects, and evaluates the ideal usage period of the built-in or expandable flash memory of the electronic device. The flash memory usage period evaluation method detects the capacity of memory blocks, memory pages and memory cells provided in the flash memory, and is ideal based on the structure of the flash memory. Calculating a spare area in at least one of the flash memory and the control center, the control center generating a test command and sending the test command to the flash memory, The flash memory performs the test based on the test command. A step of feeding back test results to an area and forming a correction parameter; and the control center acquiring the correction parameter of the spare area and selectively correcting the ideal use period according to the correction parameter. A method for evaluating the usage period of a flash memory is provided.

  Further, it is preferable that the formula for correcting the ideal use period is a multiplication result of the correction parameter and the ideal use period.

  Further, it is preferable that the modification parameter records the number of times of use of the read command, the write command, and the erase command individually executed by the memory block, the memory page, and the memory cell in each flash memory.

  The correction parameter preferably records an average wear state of the memory block, the memory page, and the memory cell in the flash memory based on a wear leveling algorithm.

  The correction parameter is preferably recorded by feeding back the corrected bit corrected in the flash memory by a correction code engine.

  The correction parameter detects whether the ready / busy pin voltage state of the flash memory is always a fixed potential before the correction code engine feeds back the correction bit of the flash memory. It is preferable.

  Further, it is preferable that after the test command is executed in the flash memory, the number of damages of the memory block, the memory page, and the memory cell is detected and recorded in the correction parameter.

  In addition, it is preferable that the test command is continuously executed in the flash memory, and the increase in the number of damaged memory blocks, the memory pages, and the memory cells and the damage speed are compared with the previous time and the current time.

  In addition, after executing a read command a plurality of times for the specific memory block, the memory page, and the memory cell of the flash memory, the correction parameter includes the specific memory block, the memory page, and the memory cell. It is preferable that an unstable fluctuation state generated in the number of correction code bits in the middle is recorded.

  The correction parameter includes a read command for the specific memory block, the memory page, and the memory cell of the flash memory, and then adjacent to the specific memory block, the memory page, and the memory cell. Preferably, the correction states of the other memory blocks, memory pages and memory cells are recorded and monitored.

  The correction parameter records that the test result fed back by the flash memory is unstable after the electronic device executes a read command, a write command, and an erase command to the flash memory. It is preferred that

  Further, the correction parameter records that the voltage state of a pin in the flash memory is abnormal after the electronic device executes a read command, a write command, and an erase command to the flash memory. It is preferable.

  The correction parameter includes an unstable voltage generated in the specific memory block, the memory page, and the memory cell when the flash memory operates the specific memory block, the memory page, and the memory cell. Preferably, the state of change is recorded.

  Further, the correction parameter may be that after the flash memory executes an erase command, a chip enable pin of the flash memory is used for a chip having the memory block, the memory page, and the memory cell based on the erase command. It is preferable to record that the data cannot be erased.

  Moreover, it is preferable that the control center controls a control drive device or a remote monitoring server of the flash memory.

  Further, it is preferable that the control center dynamically corrects, detects, and evaluates the ideal usage period for the built-in or extended flash memory of the electronic device via the Internet.

  The flash memory is preferably a single-level cell or multi-level cell NOR or NAND flash memory.

  The flash memory usage period evaluation method of the present invention executes an erase command or a program command (for example, a write command) on a flash memory by a control center (for example, a control drive device, a remote monitoring server, etc.) as compared with the prior art. Or, by changing the charge data stored in the floating gate in the flash memory by the high piezoelectric impact method by the read command), the parameters such as the bit of the correction code or the electrical characteristics related to the flash memory are obtained and the ideal use period To correct.

  Furthermore, these parameters can be stored in a memory block, memory page and memory cell in the flash memory, or stored in a spare area designated by the remote monitoring server. By using these parameters, the usage period of the flash memory can be accurately calculated.

3 is a flowchart showing a method of evaluating a usage period of a flash memory according to an embodiment of the present invention. 2 is a flowchart for obtaining the correction parameters of FIG. 2 is a flowchart for obtaining the correction parameters of FIG. 2 is a flowchart for obtaining the correction parameters of FIG. 2 is a flowchart for obtaining the correction parameters of FIG. 2 is a flowchart for obtaining the correction parameters of FIG. 2 is a flowchart for obtaining the correction parameters of FIG. 2 is a flowchart for obtaining the correction parameters of FIG. 2 is a flowchart for obtaining the correction parameters of FIG. 2 is a flowchart for obtaining the correction parameters of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited thereby.

  Please refer to FIG. As shown in FIG. 1, the flash memory usage period evaluation method according to an embodiment of the present invention dynamically corrects the ideal usage period of a built-in or extended flash memory in an electronic device by a control center. Detect, detect and evaluate. Here, the control center is a drive device that drives the flash memory or a remote monitoring server that controls the flash memory by communicating with an electronic device via the Internet.

  In this flash memory usage period evaluation method, first, in step S11 of FIG. 1, the capacities of memory blocks, memory pages, and memory cells in the flash memory are detected, and an ideal usage is based on the structure of the flash memory. Calculate the period. The structure form of the flash memory may be a single-level cell (SLC) or multi-level cell (MLC) NOR or NAND flash memory. In this step S11, an ideal use period is calculated based on the structure form used for the capacity of the flash memory. For example, when the capacity of a multi-level cell flash memory is 4 GB, the ideal period of use is 32.87 years.

  In step S12, a spare area is formed in at least one of the flash memory and the control center. This spare area is a storage space used for storing correction parameters.

  In step S13, the control center generates a test command and sends it to the flash memory. The flash memory tests the memory based on the test command, and stores an amend parameter in the spare area based on the test result fed back by the flash memory. In step S13, the control center generates a test command and sends it to the flash memory. The flash memory tests the memory based on the test command and generates a test result. This test result is a correction parameter used to correct the ideal period of use. The correction parameter generation method includes the following (1) to (9).

  (1) Use of read command (write command), write command (write command) and erase command (erase command) executed individually by each memory block, memory page and memory cell in each flash memory as this correction parameter The number of times is recorded. Reference is also made to FIG. 2, which is a flow chart for obtaining correction parameters.

  As shown in FIG. 2, first, in step S21 of the flowchart, the control center generates a test command. Subsequently, in step S22, the flash memory determines whether each of the memory block, the memory page, and the memory cell is used by the command based on the test command. Subsequently, in step S23, it is determined whether or not the command is a write command, a read command, or an erase command, and each memory block, memory page, and memory cell receives the write command, read command, or erase command, respectively. Record. In step S24, when none of the memory block, the memory page, and the memory cell are used, the process returns to step S21, and the use count is repeatedly recorded.

  In other words, when the control center generates a command that records the number of times the flash memory is used, the flash memory issues commands such as an erase command, a write command, and a read command to the memory block, memory page, and memory cell. The number of uses of each memory block, memory page, and memory cell is recorded, and the number of uses is recorded in the spare area.

  (2) Based on a wear-leveling algorithm, an average wear state of a memory block, a memory page, and a memory cell in the flash memory is recorded in the correction parameter. Reference is also made to FIG. 3, which is a flow chart for obtaining correction parameters.

  Please refer to FIG. As shown in FIG. 3, first, in step S31, the control center generates a test command. Subsequently, in step S32, it is determined whether each memory block, memory page, and memory cell in the flash memory uses a wear leveling algorithm, and if it is determined that the flash memory uses a wear leveling algorithm, step S32 is performed. S321 is executed, the average wear state is recorded as a correction parameter, and if the opposite is true, step S322 is executed. If it is determined in step S322 that the flash memory does not use the wear level algorithm, the determination is terminated.

  (3) In the correction parameter, a correction bit (bit) corrected in the flash memory is fed back and recorded by the correction code engine (error correction code engine). Reference is also made to FIG. 4 which is a flowchart for obtaining the correction parameters.

  Please refer to FIG. As shown in FIG. 4, first, in step S41, the control center generates a test command and converts a low potential to a high potential based on the test command by a ready / busy pin of the flash memory. . Subsequently, in step S42, it is confirmed whether or not a bit (bit) of the correction code (ECC) has been generated. If a bit of the correction code has been generated, step S421 is executed. In step S421, the number of bits that need to be corrected is recorded in the spare area and the determination is finished.

  (4) After executing the test command in the flash memory, the correction parameter detects and records the number of memory blocks, memory pages and memory cells damaged. Reference is also made to FIG. 5, which is a flow chart for obtaining correction parameters.

  Please refer to FIG. As shown in FIG. 5, first, in step S51, the control center generates a test command (for example, an erase command), and the states of the memory block, the memory page, and the memory cell are all set to 0 × FF or 0 × OO. Subsequently, in step S52, it is determined whether a damaged portion exists in the memory block, the memory page, and the memory cell. If there is a damaged portion, step S521 is executed. In this step S521, the number of damaged parts is recorded. In the opposite case, step S522 is executed to end the determination.

  In another embodiment of the present invention, step S51 and step S52 may be executed again, and then step S521 may be executed before step S53. In step S53, the test command is continuously executed in the flash memory, and the number of damages of the memory block, memory page, and memory cell after the previous test and the current test are compared, and the increase number and the damage speed are determined.

  (5) After executing the read command for a specific memory block, memory page and memory cell of the flash memory a plurality of times, the correction parameter is the number of correction code bits in the specific memory block, memory page and memory cell. Record the unstable fluctuation state. Reference is also made to FIG. 6 which is a flowchart for obtaining the correction parameters.

  Please refer to FIG. As shown in FIG. 6, first, in step S61, the control center generates a test command (for example, a read command), and then in step S62, whether or not the number of bits of the current and previous correction codes has changed. to decide. If it is determined that the number of bits has changed, step S621 is executed. In step S621, the change in the number of bits of the correction code is recorded, and in the opposite case, the determination is made by executing step S622.

  (6) The correction parameter records a state in which the test result fed back from the flash memory after the electronic device executes a read command, a write command, and an erase command to the flash memory is unstable. Reference is also made to FIG. 7 which is a flowchart for obtaining the correction parameters.

  Please refer to FIG. As shown in FIG. 7, first, in step S71, the control center generates a test command and acquires the ready / busy pin state of the flash memory. Subsequently, in step S72, it is determined whether the voltage state of the ready / busy pin is stable. If the voltage state of the ready / busy pin is not stable. (For example, a state in which the potential is always fixed at a high potential or a low potential), step S721 is executed to record an unstable state, and in the opposite case, the determination is made by executing step S722. .

  (7) In the correction parameter, after executing a read command for a specific memory block, memory page and memory cell of the flash memory, the other memory block and memory adjacent to the specific memory block, memory page and memory cell The page and memory cell correction code states are recorded and monitored. Reference is also made to FIG. 8 which is a flowchart for obtaining the correction parameters.

  Please refer to FIG. As shown in FIG. 8, first, in step S81, the control center generates a test command, and displays the correction code states of a specific memory block, memory page, and other memory blocks adjacent to the memory cell, memory page, and memory cell. Monitor. Subsequently, in step S82, it is determined whether the correction state of the other adjacent memory block, memory page, and memory cell is affected by the specific memory block, memory page, and memory cell. If the memory block, the memory page, and the memory cell are affected, step S821 is executed to record the unstable state, and otherwise, step S822 is executed to end the determination.

  (8) The correction parameter records that the voltage state of the pin in the flash memory is abnormal after the electronic device executes a read command, a write command, and an erase command to the flash memory. Reference is also made to FIG. 9 which is a flowchart for obtaining the correction parameters.

  Please refer to FIG. As shown in FIG. 9, first, in step S91, the control center generates a test command and monitors the voltage state of a specific memory block, memory page, and memory cell. Subsequently, in step S92, it is determined whether or not the voltage state is stable. If the voltage state is unstable, step S921 is executed and the fact that the voltage is unstable is recorded. In that case, the step S922 is executed to finish the determination.

  (9) In the correction parameter, after the flash memory executes the erase command, a chip enable pin (CE pin) of the flash memory has a memory block, a memory page, and a memory cell based on the erase command. A state in which erasing cannot be executed is recorded. Reference is also made to FIG. 10 which is a flowchart for obtaining the correction parameters.

  Please refer to FIG. As shown in FIG. 10, first, in step S101, the control center generates a test command, and executes an erase command for a chip having a memory block, a memory page, and a memory cell. Subsequently, in step S102, it is determined whether or not the chip has received an erase command and the memory block, memory page, and memory cell in the chip have been erased. When the chip unit receives the erase command, step S1021 is executed to record a state in which the chip cannot be erased. In the opposite case, step S1022 is executed to end the determination.

  Subsequently, Step S14 is executed. In step S14, the control center acquires a correction parameter for the spare area, and selectively corrects the ideal use period by the correction parameter.

  As can be seen from the above description, the flash memory usage period evaluation method is performed by a control center (for example, a control drive device or a remote monitoring server) using an erase command or a program command (for example, a write command or a read command) to the flash memory. After the flash memory is applied with a high-voltage hammering method, the charge data stored in the floating gate in the flash memory is changed), and the parameters such as the bit of the correction code or the electrical characteristics are obtained to correct the ideal use period. .

  Furthermore, these parameters are stored in memory blocks, memory pages and memory cells in the flash memory, or stored in a spare area designated by the remote monitoring server. By using these parameters, the usage period of the flash memory can be accurately calculated.

  While the preferred embodiments of the present invention have been disclosed above, as may be appreciated by those skilled in the art, they are not intended to limit the invention in any way. Various changes and modifications can be made without departing from the spirit and scope of the present invention. Accordingly, the scope of the claims of the present invention should be construed broadly including such changes and modifications.

Claims (17)

A flash memory usage period evaluation method that dynamically corrects, detects, and evaluates an ideal usage period of a built-in or expandable flash memory of an electronic device by a control center,
Detecting the capacity of memory blocks, memory pages and memory cells provided in the flash memory, and calculating an ideal use period based on the structure of the flash memory;
Forming a spare area in at least one of the flash memory and the control center;
The control center generates a test command and sends it to the flash memory, the flash memory performs a test based on the test command, and the flash memory forms a correction parameter by feeding back the test result to the spare area. And steps to
The control center includes a step of acquiring the correction parameter of the spare area and selectively correcting the ideal usage period according to the correction parameter.   2. The flash memory usage period evaluation method according to claim 1, wherein the formula for correcting the ideal usage period is a product of the correction parameter and the ideal usage period.   The number of uses of a read command, a write command, and an erase command individually executed by the memory block, the memory page, and the memory cell in each flash memory is recorded in the correction parameter. Item 2. A method for evaluating a use period of a flash memory according to Item 1.   The flash memory according to claim 1, wherein the correction parameter records an average wear state of the memory block, the memory page, and the memory cell in the flash memory based on a wear leveling algorithm. Usage period evaluation method.   2. The flash memory usage period evaluation method according to claim 1, wherein the correction parameter includes a correction code engine in which a corrected bit corrected in the flash memory is fed back and recorded.   The correction parameter detects whether the voltage state of the ready / busy pin of the flash memory is always a fixed potential before the correction code engine feeds back the correction bit of the flash memory. 6. The method for evaluating a usage period of a flash memory according to claim 5, wherein:   The number of damages of the memory block, the memory page, and the memory cell is detected and recorded in the correction parameter after the test command is executed in the flash memory. The usage period evaluation method of the described flash memory.   8. The test command is continuously executed in the flash memory, and the increase number and the damage speed of the number of damage of the memory block, the memory page, and the memory cell are compared with the previous time and the current speed. The flash memory usage period evaluation method described in 1.   After executing a read command for the specific memory block, the memory page, and the memory cell of the flash memory a plurality of times, the correction parameter includes the specific memory block, the memory page, and the memory cell. 2. The method according to claim 1, wherein an unstable fluctuation state generated in the number of correction code bits is recorded.   The correction parameter includes a read command for the specific memory block, the memory page, and the memory cell of the flash memory, and then the other adjacent to the specific memory block, the memory page, and the memory cell. 2. The flash memory usage period evaluation method according to claim 1, wherein the correction status of the memory block, memory page and memory cell is recorded and monitored.   The correction parameter records that the test result fed back by the flash memory is unstable after the electronic device executes a read command, a write command, and an erase command to the flash memory. The method of evaluating a usage period of a flash memory according to claim 1.   The correction parameter records that the voltage state of a pin in the flash memory is abnormal after the electronic device executes a read command, a write command, and an erase command to the flash memory. The method of evaluating a usage period of a flash memory according to claim 1.   The correction parameter includes an unstable voltage change generated in the specific memory block, the memory page, and the memory cell when the flash memory operates the specific memory block, the memory page, and the memory cell. 2. The method of evaluating a use period of a flash memory according to claim 1, wherein the state is recorded.   According to the correction parameter, after the flash memory executes an erase command, a chip enable pin of the flash memory erases the chip having the memory block, the memory page, and the memory cell based on the erase command. 2. The method for evaluating a period of use of a flash memory according to claim 1, wherein it is recorded that the state cannot be executed.   The method of claim 1, wherein the control center controls a control drive device or a remote monitoring server for the flash memory.   The control center dynamically corrects, detects, and evaluates the ideal usage period for the built-in or expandable flash memory of the electronic device via the Internet. 15. A method for evaluating a use period of a flash memory according to 15.   The flash memory usage period evaluation method according to claim 1, wherein the flash memory is a single-level cell or multi-level cell NOR or NAND flash memory.

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