JP2013214655A - Optical semiconductor element - Google Patents

Optical semiconductor element Download PDF

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JP2013214655A
JP2013214655A JP2012084889A JP2012084889A JP2013214655A JP 2013214655 A JP2013214655 A JP 2013214655A JP 2012084889 A JP2012084889 A JP 2012084889A JP 2012084889 A JP2012084889 A JP 2012084889A JP 2013214655 A JP2013214655 A JP 2013214655A
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stress
semiconductor element
optical semiconductor
insulating film
sio
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Takayuki Yamanaka
孝之 山中
Kenji Kishi
健志 岸
Hiroaki Sanjo
広明 三条
Masaki Kamitoku
正樹 神徳
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Nippon Telegraph and Telephone Corp
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Abstract

PROBLEM TO BE SOLVED: To provide an optical semiconductor element which solves a problem in the past technology that it is difficult to control stress accumulated at a boundary surface depending on a deposition condition due to increase in the number of boundary surfaces because occurrence of residual stress is inhibited by stacking a plurality of layers of depositing insulation films.SOLUTION: An optical semiconductor element of the present embodiment having an active layer or a light absorption layer, and having a function of a laser or an optical modulator or an optical amplifier comprises a mesa structure part for waveguiding light to an opposite side to a substrate on which the element is formed. On a part of or the whole of a surface on the side having the mesa structure part, an insulation film is formed. The insulation film is composed of a compound of a silicon oxide (SiO) film and a silicon nitride (SiN).

Description

本発明は、絶縁膜の形成の工程を有する光半導体素子に関する。   The present invention relates to an optical semiconductor element having a step of forming an insulating film.

光半導体素子は、光の発生、変調、増幅などの機能を有し、現代の高度情報社会を支える光通信技術には、必要不可欠なデバイスである。光半導体素子は、(1)InPなどの半導体基板上に、組成の異なる混晶化合物をMOCVD(Metal−Organic Chemical Vapor Deposition)法によるエピタキシャル結晶成長、(2)光の導波路パターン形成のためのエッチング、(3)エッチング部分を部分的に埋め込むための再度の結晶成長、(4)電気的な絶縁や水分や空気から半導体表面を保護するための絶縁膜形成、さらには(5)電極形成のため蒸着による金属膜の形成など、非常に複雑なプロセスを経て作製される。   An optical semiconductor element has functions such as generation, modulation, and amplification of light, and is an indispensable device for optical communication technology that supports a modern advanced information society. An optical semiconductor device includes (1) epitaxial crystal growth of MOC (Metal-Organic Chemical Vapor Deposition) on mixed crystal compounds having different compositions on a semiconductor substrate such as InP, and (2) optical waveguide pattern formation. Etching, (3) re-growth of crystals to partially fill the etched portion, (4) formation of an insulating film to protect the semiconductor surface from electrical insulation, moisture and air, and (5) electrode formation Therefore, it is manufactured through a very complicated process such as formation of a metal film by vapor deposition.

上記(1)〜(5)までの工程で使用される材料は、当然ながら、それぞれ物質の性質が異なる。これらを原子や分子レベルのオーダーで積層や蒸着といった作製する工程は、一般に工程ごとに異なる温度で行われる。工程後、温度は室温に戻るが、物質は温度によって膨張や収縮を起こすので、作製工程での温度変化を繰り返すことによって、異なる物質の界面とその周辺には大きな応力や歪みが発生することになる。   As a matter of course, the materials used in the steps (1) to (5) have different substance properties. The process of stacking or vapor depositing these at the atomic or molecular level order is generally performed at a different temperature for each process. After the process, the temperature returns to room temperature, but the substance expands and contracts depending on the temperature, so that repeated stress changes in the manufacturing process generate large stresses and strains at the interface between the different substances and the surrounding area. Become.

応力や歪みの発生やその分布は、積層材料の種類、結晶組成や形状などによって様々である。上記(1)〜(5)のうち、本発明に関わるのは、(4)の絶縁膜形成である。従来使用されてきた絶縁膜の代表的なものとしては、二酸化シリコンSiO2や窒化物Si34がある。SiO2を半導体表面上に成膜し室温に戻した場合には、半導体側は圧縮応力を受け、SiO2膜は引張応力を受ける。一方、Si34を半導体表面上に成膜し室温に戻した場合には、半導体側は引張応力を受け、Si34膜は圧縮応力を受ける。応力が内在した状態で、光半導体素子を動作させると、素子の信頼性を劣化させることが知られており、SiO2とSi34を2層以上積層させることにより、界面で互いに各向きの応力をキャンセルする手法が提案されている(特許文献1参照。)。 The generation and distribution of stress and strain vary depending on the type of laminated material, crystal composition and shape. Of the above (1) to (5), the present invention relates to the formation of the insulating film of (4). Typical examples of the insulating film conventionally used include silicon dioxide SiO 2 and nitride Si 3 N 4 . When SiO 2 is formed on the semiconductor surface and returned to room temperature, the semiconductor side receives compressive stress and the SiO 2 film receives tensile stress. On the other hand, when Si 3 N 4 is formed on the semiconductor surface and returned to room temperature, the semiconductor side receives tensile stress and the Si 3 N 4 film receives compressive stress. It is known that when an optical semiconductor element is operated in a state where stress is inherent, the reliability of the element is deteriorated. By laminating two or more layers of SiO 2 and Si 3 N 4 , it is possible to face each other at the interface. A method for canceling the stress is proposed (see Patent Document 1).

性質の異なる材料を積層させるのであるから、そこに応力や歪みが内在してしまうことは、ある程度避けられない。特に、SiO2やSi34といった絶縁膜材料は、半導体と機械的物性の違いが大きい。そのような中で、従来の手法では、2層以上の絶縁体を使用して界面付近の応力をキャンセルするアプローチをとってきた。界面に生じる応力は、圧縮と引張という互いに反対符号の応力が生じ得るから、1+(−1)+1+(−1)=0といった考え方で薄膜を複数層重合形成することにより、見掛け上応力をキャンセルすることができる。しかしながら、界面や絶縁膜の種類が増えるほど、絶縁体薄膜の成膜条件によって界面に蓄積する応力を安定的に制御するのは難しいという問題があった。絶縁膜の厚みは、サブミクロンオーダーであり、極薄膜の安定的な制御といった現実的な観点から言えば、単層の絶縁膜の適用が最も望ましい。 Since materials having different properties are laminated, it is inevitable that stress and strain are inherent therein. In particular, insulating film materials such as SiO 2 and Si 3 N 4 have a large difference in mechanical properties from semiconductors. Under such circumstances, the conventional method has taken an approach of canceling stress in the vicinity of the interface by using two or more insulators. As stress generated at the interface, stresses of opposite signs of compression and tension can occur, so apparent stress can be canceled by forming multiple layers of thin films with the concept of 1 + (-1) +1 + (-1) = 0. can do. However, as the types of interfaces and insulating films increase, there is a problem that it is difficult to stably control the stress accumulated at the interface depending on the film forming conditions of the insulator thin film. The thickness of the insulating film is on the order of submicrons, and from the practical viewpoint of stable control of the ultrathin film, it is most desirable to use a single-layer insulating film.

特許第4090768号明細書Japanese Patent No. 4090768

山寺秀哉、『薄膜の熱応力測定と制御』、豊田中央研究所R&Dレビュー、Vol.34、No.1(1999.3)Hideya Yamadera, “Measurement and Control of Thermal Stress in Thin Films”, Toyota Central R & D Review, Vol. 34, no. 1 (1999.3) 『Quartz Single Crystals (SiO2)』、株式会社ネオトロン 2011年12月28日検索、インターネットURL<http://www.neotron.co.jp/crystal/11/SiO2.html>“Quartz Single Crystals (SiO 2)”, Neotron Co., Ltd. December 28, 2011 search, Internet URL <http://www.neotron.co.jp/crystal/11/SiO2.html>

上述の背景技術の項目で述べた通り、従来の方法では、成膜する絶縁膜を複数層積層することにより、残留応力の発生を抑制していた。界面が増えることにより成膜条件によって界面に蓄積する応力の制御が難しいという問題があった。   As described in the above item of the background art, in the conventional method, the generation of residual stress is suppressed by stacking a plurality of insulating films to be formed. Due to the increase in the number of interfaces, there is a problem that it is difficult to control the stress accumulated at the interface depending on the film formation conditions.

上記の課題を解決するために、本発明の請求項1に記載された光半導体素子は、活性層、または、光吸収層を有するレーザもしくは光変調器もしくは光増幅器の機能を有する光半導体素子において、素子を形成する基板とは反対側に光を導波させるためのメサ構造部を有し、メサ構造部を有する側の表面において、表面の一部または全部が絶縁膜を備えており、その絶縁膜が、シリコン酸化膜(SiO2)と窒化シリコン(Si34)の化合物からなることを特徴とする。 In order to solve the above problems, an optical semiconductor device according to claim 1 of the present invention is an optical semiconductor device having a function of a laser, an optical modulator, or an optical amplifier having an active layer or a light absorption layer. , Having a mesa structure for guiding light on the side opposite to the substrate on which the element is formed, and a part or all of the surface is provided with an insulating film on the surface on the side having the mesa structure, The insulating film is characterized by comprising a compound of a silicon oxide film (SiO 2 ) and silicon nitride (Si 3 N 4 ).

また、請求項2に記載された発明は、請求項1に記載の半導体素子において、さらに、絶縁膜の上に電極を取るための金属層が形成されていることを特徴とする。   According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a metal layer for taking an electrode is further formed on the insulating film.

また、請求項3に記載された発明は、請求項1または2に記載の半導体素子において、前記活性層、または、光吸収層は、In(z)Ga(1−z)As(1−w)P(w)やIn(1−z−w)Al(z)Ga(w)Asなどの4元混晶化合物半導体(ここで、z、wは、混結晶の組成比である。)であることを特徴とする。   Further, the invention described in claim 3 is the semiconductor device according to claim 1 or 2, wherein the active layer or the light absorption layer is In (z) Ga (1-z) As (1-w ) A quaternary mixed crystal compound semiconductor such as P (w) or In (1-zw) Al (z) Ga (w) As (where z and w are the composition ratio of the mixed crystal). It is characterized by being.

本発明の光半導体素子によれば、一種類の材料で絶縁膜と接する半導体や金属の界面及び絶縁膜内部の残留応力も少ない半導体素子を作製することができる。   According to the optical semiconductor element of the present invention, it is possible to manufacture a semiconductor element with less residual stress inside a semiconductor or metal interface and in the insulating film in contact with the insulating film with one kind of material.

本発明の第1の実施形態に係る光半導体素子の構造を示す図である。It is a figure which shows the structure of the optical semiconductor element which concerns on the 1st Embodiment of this invention. 図1及び図5の実施形態の構造に対する応力分布のシミュレーションにおいて、絶縁膜(SiO2)x(Si34)yの組成(x、y)に対する線膨張係数及びヤング率の特性を示す図である。FIG. 5 is a diagram showing characteristics of linear expansion coefficient and Young's modulus with respect to the composition (x, y) of the insulating film (SiO 2 ) x (Si 3 N 4 ) y in the simulation of stress distribution for the structure of the embodiment of FIGS. It is. 本発明の第1の実施形態に係る光半導体素子の構造において中心対称面と奥行き方向を示した図である。It is the figure which showed the center symmetry plane and the depth direction in the structure of the optical semiconductor element which concerns on the 1st Embodiment of this invention. 本発明の第1の実施形態に係る光半導体素子に関するフォン・ミーゼス応力のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the von Mises stress regarding the optical semiconductor element which concerns on the 1st Embodiment of this invention. 本発明の第2の実施形態に係る光半導体素子の構造を示す図である。It is a figure which shows the structure of the optical semiconductor element which concerns on the 2nd Embodiment of this invention. 本発明の第2の実施形態に係る光半導体素子に関するフォン・ミーゼス応力のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the von Mises stress regarding the optical semiconductor element which concerns on the 2nd Embodiment of this invention.

以下、図面を参照して、本発明の実施形態について詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図1は、本発明の第1の実施形態に係る光半導体素子100の構造を示す図である。
図1において、光半導体素子100は、リッジ型と呼ばれる半導体光導波路構造を有している。光半導体素子100は、n型InPウェハ基板101上に積層された半導体活性層または吸収層102の上に、p型InP層を積層し、エッチングにより、突起状のメサ形状103を形成し、最後に半導体表面を単層の絶縁膜104で覆った構造を有している。
FIG. 1 is a diagram showing a structure of an optical semiconductor device 100 according to the first embodiment of the present invention.
In FIG. 1, an optical semiconductor element 100 has a semiconductor optical waveguide structure called a ridge type. In the optical semiconductor device 100, a p-type InP layer is stacked on a semiconductor active layer or absorption layer 102 stacked on an n-type InP wafer substrate 101, and a protruding mesa shape 103 is formed by etching. The semiconductor surface is covered with a single insulating film 104.

半導体活性層または吸収層102は、In(z)Ga(1−z)As(1−w)P(w)やIn(1−z−w)Al(z)Ga(w)Asなどの4元混晶化合物半導体などが考えられる。ここで、z、wは、混結晶の組成比である。   The semiconductor active layer or absorption layer 102 is made of 4 such as In (z) Ga (1-z) As (1-w) P (w) and In (1-z-w) Al (z) Ga (w) As. An original mixed crystal compound semiconductor can be considered. Here, z and w are composition ratios of mixed crystals.

絶縁膜104は、本発明に関わる単層膜(SiO2)x(Si34)yであり、xは、二酸化ケイ素SiO2の組成比、yは、窒化ケイ素Si34の組成比である。 The insulating film 104 is a single layer film (SiO 2 ) x (Si 3 N 4 ) y according to the present invention, where x is a composition ratio of silicon dioxide SiO 2 and y is a composition ratio of silicon nitride Si 3 N 4 . It is.

図1の3次元構造を計算機上に構築し、各部分にかかる応力分布を数値計算(有限要素法)により求めた。計算にあたっては、活性層(吸収層)102の部分は、InPで置き換えた。4元混晶の機械的物性は、InPのそれと同様であるため、一般性を失うことなく、効率的に計算を行うことができる。   The three-dimensional structure shown in FIG. 1 was constructed on a computer, and the stress distribution applied to each part was obtained by numerical calculation (finite element method). In the calculation, the active layer (absorbing layer) 102 was replaced with InP. Since the mechanical properties of the quaternary mixed crystal are similar to those of InP, the calculation can be performed efficiently without losing generality.

本発明にかかわる材料設計において、重要な物性データは、線膨張係数、ヤング率、およびポアソン比である。SiO2の線膨張係数は、SiO2を成膜したInPウェハを実際に作成し、ウェハの反りを測定したニュートンリングの間隔から算出し、反りと線膨張係数の関係式を使用して求めた。Si34の線膨張係数についても同様の実験を行い、算出した。SiO2、Si34のこれらの算出値を線形補間することにより、絶縁膜(SiO2)x(Si34)yの任意の組成比x、yに対する線膨張係数を得た。その結果を図2の200に示す。図からわかるように、線膨脹係数は組成によって正の膨張と負の膨張の両方をとり、一種類の材料であっても多様な応力分布に対応できる可能性を示唆している。 In material design according to the present invention, important physical property data are linear expansion coefficient, Young's modulus, and Poisson's ratio. Linear expansion coefficient of the SiO 2 actually create the InP wafer was deposited SiO 2, is calculated from the interval of Newton rings was measured warpage of the wafer was determined using the relationship of the warp and the linear expansion coefficient . A similar experiment was performed to calculate the linear expansion coefficient of Si 3 N 4 . By linearly interpolating these calculated values of SiO 2 and Si 3 N 4 , linear expansion coefficients were obtained for arbitrary composition ratios x and y of the insulating film (SiO 2 ) x (Si 3 N 4 ) y. The result is shown at 200 in FIG. As can be seen from the figure, the coefficient of linear expansion takes both positive and negative expansion depending on the composition, suggesting that even one type of material can cope with various stress distributions.

図2の210は、絶縁膜(SiO2)x(Si34)yの任意の組成比x、yに対するヤング率の特性を示す図である。これは、よく知られている文献データから線形補間により算出した。Si34に対する最近の数値として、非特許文献1の22頁のTable2の実験値があげられる。また、SiO2に対しては、非特許文献2で公開されている特性表の値(76.5GPa、Z軸に対して垂直)をあげておく。ポアソン比については、材料による変動幅が小さいので0.2で一定とした。 210 in FIG. 2 is a graph showing the Young's modulus characteristics with respect to an arbitrary composition ratio x, y of the insulating film (SiO 2 ) x (Si 3 N 4 ) y. This was calculated by linear interpolation from well-known literature data. As a recent numerical value for Si 3 N 4 , there is an experimental value of Table 2 on page 22 of Non-Patent Document 1. For SiO 2 , the values in the characteristic table (76.5 GPa, perpendicular to the Z axis) disclosed in Non-Patent Document 2 are listed. The Poisson's ratio was constant at 0.2 because the fluctuation range depending on the material was small.

図4に、図3の構造のシミュレーション結果を示す。図3の構造は、図1の構造と同一である。図3に示すように、導波路構造は点線で囲った面(中心対称面)に対して左右対称である。ただし、左右対称構造であるか否かは、本発明の効果と無関係である。図4は、その左右対称面内で、深さ方向が活性層の中心付近(図3に白矢印で示す。)、奥行き方向が端面から5ミクロンの位置でのフォン・ミーゼス応力と組成比x、yの関係を計算した結果である。組成比x、yを横軸にとり、SiO2,Si34いずれか一方のみの組成の場合の結果も含めてある。 FIG. 4 shows a simulation result of the structure of FIG. The structure of FIG. 3 is the same as the structure of FIG. As shown in FIG. 3, the waveguide structure is bilaterally symmetric with respect to a plane (center symmetry plane) surrounded by a dotted line. However, whether or not the structure is symmetrical is irrelevant to the effect of the present invention. FIG. 4 shows the von Mises stress and the composition ratio x when the depth direction is near the center of the active layer (indicated by a white arrow in FIG. 3) and the depth direction is 5 microns from the end face. , Y are calculated results. The composition ratios x and y are taken on the horizontal axis, and the results in the case of the composition of only one of SiO 2 and Si 3 N 4 are also included.

図4から、絶縁膜(SiO2)x(Si34)yの組成比x、yをx=0.1、y=0.9にすることにより、SiO2単層やSi34単層では得られない低い応力が得られていることが分かる。このカーブの形状は、(SiO2)x(Si34)yの厚さによっても多様に変化する。 From FIG. 4, by setting the composition ratios x and y of the insulating film (SiO 2 ) x (Si 3 N 4 ) y to x = 0.1 and y = 0.9, the SiO 2 single layer or Si 3 N 4 It can be seen that a low stress that cannot be obtained with a single layer is obtained. The shape of this curve varies depending on the thickness of (SiO 2 ) x (Si 3 N 4 ) y.

ここで、図4の縦軸のフォン・ミーゼス応力について説明する。フォン・ミーゼスの応力の単位は、MPaである。そもそも、応力σは、9つの成分を有するテンソル(tensor)量である。例えば、σxyは、x軸に垂直な面内におけるy軸方向の応力成分を表す。すなわち、3次元空間において、これらの成分は、 Here, the von Mises stress on the vertical axis in FIG. 4 will be described. The unit of von Mises stress is MPa. In the first place, the stress σ is a tensor amount having nine components. For example, σ xy represents a stress component in the y-axis direction in a plane perpendicular to the x-axis. That is, in a three-dimensional space, these components are

Figure 2013214655
Figure 2013214655

といった行列形式で表現される。   It is expressed in the matrix form.

そこで、9つの成分を有するテンソル量を応力の主軸上に投影し、1つのスカラー値に変換したものをフォン・ミーゼス応力σVMと呼び、以下のような式で定義されている。 Thus, a tensor amount having nine components is projected onto the principal axis of the stress and converted into one scalar value, which is called von Mises stress σ VM and is defined by the following equation.

Figure 2013214655
Figure 2013214655

フォン・ミーゼス応力は、σVM方向を有する量を1つの値で定量的に表現できるので便利な指標として使用されている。ただし、ルートを取っているため、符号は必ず正になるので、これだけでは圧縮か引張かはわからない。圧縮にしろ、引張にしろ、応力が存在することは好ましくないという点において、フォン・ミーゼス応力σVMは便利だけでなく応力評価における強力な評価指標である。 The von Mises stress is used as a convenient index because the quantity having the σ VM direction can be quantitatively expressed by one value. However, since the route is taken, the sign is always positive, so it is not possible to know whether it is compression or tension. The von Mises stress σ VM is not only convenient, but also a powerful evaluation index in stress evaluation in that it is not preferable that stress is present, whether compression or tension.

σVMは、せん断応力(shear stress)による歪みエネルギーの密度に相当する。破壊工学では、この値が降伏点(弾性変形の限界点)に達したら、その構造はそこから降伏(塑性変形状態に移行)すると考える。この値が最も大きい部位が、力学的には最も脆い部位と判断される。 σ VM corresponds to the density of strain energy due to shear stress. In fracture engineering, when this value reaches the yield point (limit of elastic deformation), the structure is considered to yield (transition to plastic deformation state) from there. The part with the largest value is determined to be the most brittle part in terms of dynamics.

以上、説明したように、応力はテンソル量であり、方向や符号を有する複雑な量であるが、フォン・ミーゼス応力という正値のみをとるスカラー量によって議論することにより、応力の大小がどのように分布しているかを簡便かつ的確にとらえることができる。   As described above, the stress is a tensor amount and is a complex amount having a direction and a sign. However, by discussing with a scalar amount that takes only a positive value called von Mises stress, how does the magnitude of the stress change? Can be easily and accurately grasped.

図5は、本発明の第2の実施形態に係る光半導体素子500の構造を示す図である。   FIG. 5 is a diagram showing a structure of an optical semiconductor element 500 according to the second embodiment of the present invention.

図5において、光半導体素子500は、図1と類似のリッジ型と呼ばれる半導体光導波路構造を有する。図1に示す構造との相違点は、絶縁膜504の上面に電極用の金505が1ミクロン蒸着されている点である。図5に示すように、導波路構造は点線で囲った面(中心対称面)に対して左右対称である。繰り返しになるが、左右対称構造であるか否かは、本発明の効果と無関係である。   In FIG. 5, an optical semiconductor element 500 has a semiconductor optical waveguide structure called a ridge type similar to FIG. A difference from the structure shown in FIG. 1 is that gold 505 for electrodes is deposited on the upper surface of the insulating film 504 by 1 micron. As shown in FIG. 5, the waveguide structure is bilaterally symmetric with respect to a plane (center symmetry plane) surrounded by a dotted line. Again, whether or not the structure is symmetrical is irrelevant to the effect of the present invention.

図6に、図5の構造のシミュレーション結果を示す。図6は、左右対称面内で、深さ方向が活性層の中心付近(図5に白矢印で示す。)、奥行き方向が端面から5ミクロンの位置でのフォン・ミーゼス応力と組成比x、yの関係を計算した結果である。組成比x、yを横軸にとり、SiO2、Si34いずれか一方のみの組成の場合の結果も含めてある。 FIG. 6 shows a simulation result of the structure of FIG. FIG. 6 shows the von Mises stress and the composition ratio x at a position where the depth direction is near the center of the active layer (indicated by a white arrow in FIG. 5) and the depth direction is 5 microns from the end face in the left-right symmetry plane. It is the result of calculating the relationship of y. The composition ratios x and y are taken on the horizontal axis, and the results for the composition of only one of SiO 2 and Si 3 N 4 are also included.

図4と図6の差異は、金電極505が蒸着されたことにより、単層絶縁膜(SiO2)x(Si34)yが上下左右方向から複雑な応力を受けることにある。本実施形態の場合、x=0.2〜0.3、y=0.8〜0.7を選択することにより、応力を最小化できている。金電極蒸着の条件・形状に基づき、SiO2とSi34の組成を適切に選択することにより、端面のみならず構造全体に対して応力を最小化できる。さらに、(SiO2)x(Si34)yという単層の絶縁膜であるがゆえに絶縁膜内に界面がなく転位などによる破壊の起こるリスクがさらに低くなる。 The difference between FIG. 4 and FIG. 6 is that the single-layer insulating film (SiO 2 ) x (Si 3 N 4 ) y is subjected to complex stress from the top, bottom, left, and right directions by depositing the gold electrode 505. In the case of the present embodiment, the stress can be minimized by selecting x = 0.2 to 0.3 and y = 0.8 to 0.7. By appropriately selecting the composition of SiO 2 and Si 3 N 4 based on the conditions and shape of gold electrode deposition, stress can be minimized not only on the end face but also on the entire structure. Further, since it is a single-layer insulating film of (SiO 2 ) x (Si 3 N 4 ) y, there is no interface in the insulating film, and the risk of breakdown due to dislocation is further reduced.

応力の集中や増加がどこで生じるかについては、半導体の構造、電極の形状や厚さに依存する。したがって、それに応じた最適な単層絶縁膜組成x、yも変化する。複数の絶縁膜の最適値を探すことなく、応力の少ない堅牢な構造を実現できる長所は大きい。   Where the stress concentration or increase occurs depends on the structure of the semiconductor and the shape and thickness of the electrodes. Accordingly, the optimum single-layer insulating film composition x, y corresponding to the change also changes. There is a great advantage that a robust structure with less stress can be realized without searching for an optimum value of a plurality of insulating films.

以上、本発明の光半導体素子によれば、1種類の材料(x、y)故に、破壊や故障の起点となる界面がより少なく、また、組成比を変更することにより、メサ型構造や上部電極の影響に対して強い素子を作成することができる。   As described above, according to the optical semiconductor device of the present invention, since there is one kind of material (x, y), there are fewer interfaces that are the starting points of breakdown or failure, and by changing the composition ratio, the mesa structure or the upper part can be obtained. An element that is strong against the influence of electrodes can be created.

101,301,501 InP半導体基板
102,302,502 半導体活性層または吸収層
103,303,503 InP半導体メサ
104,304,504 絶縁膜
505 電極
101, 301, 501 InP semiconductor substrate 102, 302, 502 Semiconductor active layer or absorption layer 103, 303, 503 InP semiconductor mesa 104, 304, 504 Insulating film 505 Electrode

Claims (3)

活性層、または、光吸収層を有するレーザもしくは光変調器もしくは光増幅器の機能を有する半導体素子において、
素子を形成する基板とは反対側に光を導波させるためのメサ構造部を有し、メサ構造部を有する側の表面の一部または全部が絶縁膜を備えており、
その絶縁膜が、シリコン酸化膜(SiO2)と窒化シリコン(Si34)の化合物からなることを特徴とする光半導体素子。
In a semiconductor element having a function of an active layer or a laser or light modulator or optical amplifier having a light absorption layer,
Having a mesa structure for guiding light on the side opposite to the substrate on which the element is formed, and part or all of the surface on the side having the mesa structure has an insulating film;
An optical semiconductor element characterized in that the insulating film is made of a compound of a silicon oxide film (SiO 2 ) and silicon nitride (Si 3 N 4 ).
さらに、絶縁膜の上に電極を取るための金属層が形成されていることを特徴とする請求項1に記載の光半導体素子。   2. The optical semiconductor element according to claim 1, further comprising a metal layer for forming an electrode on the insulating film. 前記活性層、または、光吸収層は、In(z)Ga(1−z)As(1−w)P(w)やIn(1−z−w)Al(z)Ga(w)Asなどの4元混晶化合物半導体(ここで、z、wは、混結晶の組成比である。)であることを特徴とする請求項1または2に記載の光半導体素子。   The active layer or the light absorption layer includes In (z) Ga (1-z) As (1-w) P (w), In (1-z-w) Al (z) Ga (w) As, and the like. The optical semiconductor element according to claim 1, wherein the quaternary mixed crystal compound semiconductor (wherein z and w are the composition ratio of the mixed crystal) is used.
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