JP2013211838A - Photoelectric conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion device capable of suppressing color shifting in a sub-scanning direction through simple control over control pulses while suppressing an increase in circuit scale of the whole system.SOLUTION: A photoelectric conversion device includes a plurality of pixel arrays including a plurality of pixels such that when a document is scanned relatively in a sub-scanning direction, pixel arrays of different colors are arranged in the sub-scanning direction and the respective pixel arrays perform photoelectric conversion, and a pulse control section which controls pulse positions of control pulses controlling operations of pixels. The pulse control section controls the pulse positions of the control pulses of the pixel arrays of respective colors according to color shifting amounts of the pixel arrays of the respective colors in the sub-scanning direction.

Description

  The present invention relates to a photoelectric conversion device used for a copying machine or an image scanner.

  The image reading apparatus uses a line sensor in which red (R), green (G), and blue (B) pixel arrays are arranged at predetermined intervals in a direction perpendicular to the array direction, and the line sensor is relative to the document. The image is read by moving it in the sub-scanning direction. As a means for electrically reducing the color shift in the sub-scanning direction that occurs in this image reading apparatus, a technique as disclosed in Patent Document 1 is disclosed. Patent Document 1 describes a method of correcting color misregistration by correction means at the latter stage of the sensor based on a correction coefficient calculated in advance for each pixel position.

JP-A-5-122542

  However, in Patent Document 1, a correction coefficient corresponding to the amount of color misregistration is held in an external memory, and when a signal from the sensor is output, the misregistration correction unit calls the correction coefficient in the external memory to perform correction. Yes. However, in this case, there is a problem that the signal processing unit becomes complicated by performing the correction process in the subsequent circuit, and the circuit scale increases.

  An object of the present invention is to provide a photoelectric conversion device capable of reducing color misregistration in the sub-scanning direction by simple control pulse control while suppressing an increase in circuit scale of the entire system.

  In the photoelectric conversion device of the present invention, when a document is relatively scanned in the sub-scanning direction, pixel arrays of different colors are arranged in the sub-scanning direction, and each pixel array includes a plurality of pixels that perform photoelectric conversion. A pixel array, and a pulse control unit that controls a pulse position of a control pulse that controls the operation of the pixel, the pulse control unit according to the amount of color shift in the sub-scanning direction of the pixel array of each color, The pulse position of the control pulse of the pixel array of each color is controlled.

  According to the present invention, it is possible to acquire a good image with reduced color misregistration in the sub-scanning direction by controlling the control pulse of the pixel array of each color according to the color misregistration amount. Moreover, the expansion of the circuit scale of the whole system can be suppressed.

It is a block diagram which shows the structural example of the photoelectric conversion apparatus which concerns on embodiment of this invention. It is a circuit diagram which shows the structural example of the pixel in the block diagram of FIG. It is a circuit diagram which shows the structural example of the holding | maintenance part in the block diagram of FIG. It is a timing chart which shows operation | movement of the photoelectric conversion apparatus of FIG. It is a figure which shows the example of arrangement | positioning of the pixel array of each color of the photoelectric conversion apparatus of FIG. It is a timing chart which shows operation | movement of the photoelectric conversion apparatus of FIG. It is a timing chart which shows operation | movement of the photoelectric conversion apparatus of FIG. It is a timing chart which shows operation | movement of the photoelectric conversion apparatus of FIG. It is a figure which shows the structural example of the pulse control part in the block diagram of FIG. It is a figure which shows the structural example of the pulse control part in the block diagram of FIG. It is a block diagram which shows the structural example of the photoelectric conversion apparatus which concerns on embodiment of this invention. It is a circuit diagram which shows the structural example of the holding | maintenance part in the block diagram of FIG. 12 is a timing chart illustrating an operation of the photoelectric conversion apparatus in FIG. 11. It is a figure which shows the system configuration example of the photoelectric conversion apparatus which concerns on embodiment of this invention. It is a circuit block diagram which shows the example of a connection of the power supply wiring of FIG. It is a circuit block diagram of the pixel of FIG. FIG. 16 is a circuit configuration diagram of the bias source circuit of FIG. 15. It is a figure which shows the example of light-shielding of the OB pixel of FIG. It is a figure which shows the example of supply of the power supply voltage of FIG.

  FIG. 1 shows a configuration example of a photoelectric conversion apparatus according to an embodiment of the present invention. The pixel 100 is configured by the circuit shown in FIG. As shown in FIG. 2, the pixel 100 is controlled by control pulses pres and ptx. The photodiode PD converts light into electric charge by photoelectric conversion and accumulates the converted electric charge. The floating diffusion FD accumulates electric charges. The reset pulse pres is applied to the gate of the reset transistor M1, thereby controlling the reset operation of the photodiode PD and the floating diffusion FD in the pixel 100. That is, the reset pulse pres is a control pulse for controlling the reset operation of the pixel 100. The transfer pulse ptx is applied to the gate of the transfer transistor M2, thereby controlling the charge transfer operation from the photodiode PD to the floating diffusion FD. The amplification transistor M3 is an input unit of a source follower circuit that operates by a current source Iref for outputting an output corresponding to the potential of the floating diffusion FD to the output terminal out.

  In FIG. 1, reference numeral 110 denotes an R pixel array that includes a plurality of pixels 100, and an optical filter that transmits light in the red wavelength region is disposed on the upper surface. Reference numeral 120 denotes a G pixel array that includes a plurality of pixels 100 and has an optical filter that transmits light in the green wavelength region disposed on the upper surface. Reference numeral 130 denotes a B pixel array composed of a plurality of pixels 100 and having an optical filter that transmits light in the blue wavelength region disposed on the upper surface. The R pixel array 110, the G pixel array 120, and the B pixel array 130 are arranged at a constant interval d, as shown in FIG. Hereinafter, the array direction of the R pixel array 110, the G pixel array 120, and the B pixel array 130 in FIG. 5 is referred to as a main scanning direction, and a direction perpendicular to the main scanning direction is referred to as a sub scanning direction.

  Reference numeral 200 denotes a holding unit for holding an output signal from the pixel 100, and has a circuit configuration as shown in FIG. In FIG. 3, ctn is a capacitor for holding an output signal when the pixel 100 is reset by the reset pulse pres, and the sample and hold operation is controlled by opening and closing the switch sw1n by the read pulse ptn. cts is a capacitor for holding a signal when the pixel 100 is not reset, and the sample and hold operation is controlled by opening and closing the switch sw1s by the readout pulse pts. The signals held in the capacitors cts and ctn are output to the output terminals outn and outs when the pulse phs goes high and the switches sw2n and sw2s are turned on.

  Reference numeral 300 denotes a pulse control unit that generates a control pulse for controlling the operation of the pixel 100 and a pulse for controlling the sample / hold operation of the output signal from the pixel 100 in the holding unit 200. In response to the external control pulse, the pulse control unit 300 includes each of the R pixel array 110 and the corresponding holding unit 200, the G pixel array 120 and the corresponding holding unit 200, the B pixel array 130, and the corresponding holding unit 200. The pulse position of the control pulse is controlled. Hereinafter, pres_r, ptx_r, ptn_r, and pts_r, which are control pulses of the R pixel array 110 and the holding unit 200 corresponding thereto, will be referred to as R control pulses. Further, pres_g, ptx_g, ptn_g, and pts_g, which are control pulses of the G pixel array 120 and the holding unit 200 corresponding thereto, are used as G control pulses. Similarly, pres_b, ptx_b, ptn_b, and pts_b, which are control pulses of the B pixel array 130 and the holding unit 200 corresponding thereto, are set as B control pulses. Here, the pulses pres_r, pres_g, and pres_b correspond to the pulse pres in FIG. 2, and the pulses ptx_r, ptx_g, and ptx_b correspond to the pulse ptx in FIG. Further, the pulses ptn_r, ptn_g, and ptn_b correspond to the pulse ptn in FIG. 3, and the pulses pts_r, pts_g, and pts_b correspond to the pulse pts in FIG.

  The horizontal shift register 400 sequentially outputs pulses phs to the plurality of holding units 200. The signals of the output terminals outn and outs of the holding unit 200 corresponding to the R pixel array 110 are output to the output terminals Voutn_r and Vouts_r. The signals of the output terminals outn and outs of the holding unit 200 corresponding to the G pixel array 120 are output to the output terminals Voutn_g and Vouts_g. The signals of the output terminals outn and outs of the holding unit 200 corresponding to the B pixel array 130 are output to the output terminals Voutn_b and Vouts_b.

  Hereinafter, the circuit operation and the color misregistration reduction method of FIG. 1 will be described. First, as shown in FIG. 5, the intervals between the R pixel array 110, the G pixel array 120, and the B pixel array 130 are a constant interval d. Image scanning is performed by scanning (moving) a line sensor (including the R pixel array 110, the G pixel array 120, and the B pixel array 130) in the sub-scanning direction relative to the document. In that case, the line sensor may be moved, or the document may be moved. In the plurality of pixel arrays 110, 120, and 130, pixel arrays of different colors are arranged in the sub-scanning direction. Each pixel array 110, 120, 130 has a plurality of pixels 100 that perform photoelectric conversion. Image reading characteristics using the line sensor are affected by a physical shift (fixed interval d) of an imaging position on the original image of each pixel 100 of the R pixel array 110, the G pixel array 120, and the B pixel array 130. Due to the shift d, an image sampling position shift (color shift phenomenon) occurs between the outputs of the R pixel array 110, the G pixel array 120, and the B pixel array 130. Therefore, in this type of photoelectric conversion device, it is essential to perform level difference correction, that is, color misregistration correction among the outputs of the R pixel array 110, the G pixel array 120, and the B pixel array 130. During the movement of the photoelectric conversion device or the original in the sub-scanning direction, the positional relationship between the pixels 100 of the R pixel array 110, the G pixel array 120, and the B pixel array 130 is maintained constant. The imaging position of each color is shifted by an amount corresponding to the interval d. Accordingly, an appropriate image can be obtained by finally combining the color signals of the R pixel array 110, the G pixel array 120, and the B pixel array 130 in consideration of this deviation. However, due to factors such as chromatic aberration of the optical member provided between the original image and the photoelectric conversion device, a deviation occurs in the relationship between the sampling positions of the respective colors, which should be the constant interval d. If the shifted color signals are combined as they are to create an image, color misregistration will occur. Therefore, first, before starting reading of the original image, the correction pattern image prepared in advance is read. Subsequently, as illustrated in FIG. 14, the R signal, the G signal, and the B signal output from the photoelectric conversion device 1 are converted from analog to digital by the analog-to-digital converter 2. Thereafter, the signal processing process 3 performs predetermined processing such as shading correction on the digital signal, and outputs the R signal, the G signal, and the B signal to the output terminals Rout, Gout, and Bout, and a color shift amount calculation unit. Output to 4. The color misregistration amount calculation unit 4 calculates the color misregistration amount of the R signal, the G signal, and the B signal in the sub-scanning direction based on the correction pattern image, and generates an external control pulse based on the color misregistration amount. To the pulse controller 300 (FIG. 1) in the photoelectric conversion device 1. That is, the color misregistration amount calculation unit 4 calculates the color misregistration amount in the sub-scanning direction when the plurality of pixel arrays 110, 120, and 130 scan the correction pattern image. The calculated color misregistration amount is the color misregistration amount in the sub-scanning direction of the pixel arrays 110, 120, and 130 for each color. The pulse control unit 300 controls the pulse positions of the R control pulse, the G control pulse, and the B control pulse according to the input external control pulse data. That is, the pulse control unit 300 controls the pulse positions of the control pulses of the pixel arrays 110, 120, and 130 for each color according to the color shift amount calculated by the color shift amount calculation unit. These control pulses are pulses for controlling the charge accumulation period by photoelectric conversion of the pixel 100, and changing these pulse positions is synonymous with changing the charge accumulation period. Changing the charge accumulation period is the same as changing the sampling position.

  As an example, the amount of deviation of the imaging positions of the G pixel array 120 and the B pixel array 130 with respect to the imaging position of the R pixel array 110 from the color deviation amount calculation result in the sub-scanning direction in the color deviation amount calculation unit 4 of FIG. A case where the values are expressed as trg and trb in terms of temporal numerical values will be described. In this case, the G control pulse is set so that the pulse position shifts with respect to the R control pulse by the shift amount trg, and the B control pulse by the shift amount trb. As a result, the charge accumulation periods of the G pixel array 120 and the B pixel array 130 are shifted from the R pixel array 110 by the shift amounts trg and trb, respectively. The imaging positions of the G pixel array 120 and the B pixel array 130 are moved by an amount corresponding to the deviation of the charge accumulation period, and the shift amount of the imaging positions of the G pixel array 120 and the B pixel array 130 with respect to the R pixel array 110 is reduced.

  It should be noted that a series of processes from reading the correction pattern image and calculating the color misregistration amount therefrom need not be performed every time before reading the original image. For example, an operation up to calculation of a color misregistration amount at the time of shipping inspection at a factory may be performed, and thereafter, the value may be retained in an external memory or the like and used continuously.

  FIG. 4 is a timing chart showing the operation of FIG. 1. Hereinafter, the detailed circuit operation of FIG. 1 will be described with reference to FIG. In FIG. 4, before the time t1, the reset pulses pres_r, pres_g, and pres_b are at the high level, the reset transistor M1 is turned on, and the floating diffusions FD of all the pixels 100 are reset to the power supply potential. Before that, the transfer pulse ptx_r becomes high level, the transfer transistor M2 is turned on, and the photodiode PD of the R pixel array 110 is also reset. Thereafter, as described later, the transfer pulse ptx_r becomes low level, the transfer transistor M2 is turned off, and the charge accumulation period of the photodiode PD of the R pixel array 110 starts. Thereafter, when the reset pulse pres_r becomes low level at time t1, the reset transistor M1 is turned off, and the reset of the floating diffusion FD of each pixel 100 of the R pixel array 110 is released. When the read potential ptn_r becomes high level during the period from time t2 to t3, the switch sw1n is turned on, and the reset potential is sampled and held in the capacitor ctn of the holding unit 200 corresponding to the R pixel array 110. The readout pulse ptn_r is a control pulse that controls the sample and hold operation of the signal of the pixel 100.

  Subsequently, during a period from time t4 to t5, the transfer pulse ptx_r becomes high level, so that the transfer transistor M2 is turned on, and the signal charge accumulated in the photodiode PD of each pixel 100 of the R pixel array 110 is It is transferred to the floating diffusion FD. This time t5 is the end position of the charge accumulation period of the R pixel array 110. The switch sw1s is turned on by a pulse pts_r that becomes high level during a period from time t4 to t6, and the signal potential based on this signal charge is sampled and held in the capacitor cts of the holding unit 200 corresponding to the R pixel array 110. The readout pulse pts_r is a control pulse that controls the sample and hold operation of the signal of the pixel 100.

  Next, at time t7, the pulses pres_r and ptx_r are set to a high level, the transistors M1 and M2 are turned on, the photodiode PD and the floating diffusion FD are reset, and charge accumulation in the next row is started. Therefore, the transfer pulse ptx_r first becomes low level after time t7, and the time when the transfer transistor M2 is turned off is the start position of the charge accumulation period of the R pixel array 110. The transfer pulse ptx_r is a control pulse for controlling the charge transfer operation that determines the charge accumulation period of the pixel 100.

  The circuit operation performed on the R pixel array 110 and the holding unit 200 corresponding to the R pixel array 110 has been described above. The circuit operation is similarly performed on the G pixel array 120, the B pixel array 130, and the holding units 200 corresponding to the G pixel array 120 and the B pixel array 130 at timings shifted by the color misregistration amounts trg and trb, respectively. . The operation timing of the G pixel array 120 is delayed by the color misregistration amount trg with respect to the operation timing of the R pixel array 110, and the operation timing of the B pixel array 130 is delayed by the color misregistration amount trb with respect to the operation timing of the R pixel array 110.

  That is, when the reset pulse pres_g becomes low level, the reset transistor M1 is turned off, and the reset of the floating diffusion FD of each pixel 100 of the G pixel array 120 is released. When the pulse ptn_g becomes high level, the switch sw1n is turned on, and the reset potential is sampled and held in the capacitor ctn of the holding unit 200 corresponding to the G pixel array 120. Next, when the transfer pulse ptx_g becomes a high level, the transfer transistor M2 is turned on, and the signal charge accumulated in the photodiode PD of each pixel 100 of the G pixel array 120 is transferred to the floating diffusion FD. When the pulse pts_g becomes a high level, the switch sw1s is turned on, and the signal potential based on this signal charge is sampled and held in the capacitor cts of the holding unit 200 corresponding to the G pixel array 120. Next, the pulses pres_g and ptx_g are set to the high level, the transistors M1 and M2 are turned on, the photodiode PD and the floating diffusion FD are reset, and then charge accumulation in the next row is started.

  When the reset pulse pres_b becomes low level, the reset transistor M1 is turned off, and the reset of the floating diffusion FD of each pixel 100 of the B pixel array 130 is released. When the pulse ptn_b becomes a high level, the switch sw1n is turned on, and the reset potential is sampled and held in the capacitor ctn of the holding unit 200 corresponding to the B pixel array 130. Next, when the transfer pulse ptx_b becomes high level, the transfer transistor M2 is turned on, and the signal charge accumulated in the photodiode PD of each pixel 100 of the B pixel array 130 is transferred to the floating diffusion FD. When the pulse pts_b becomes a high level, the switch sw1s is turned on, and the signal potential based on this signal charge is sampled and held in the capacitor cts of the holding unit 200 corresponding to the B pixel array 130. Next, the pulses pres_b and ptx_b are set to the high level, the transistors M1 and M2 are turned on, the photodiode PD and the floating diffusion FD are reset, and then charge accumulation in the next row is started.

  As described above, the pulse control unit 300 controls the amount of change in pulse position such as the reset pulse pres_g and the like, the transfer pulse ptx_g and the read pulses ptn_g and pts_g by the uniform color misregistration amounts trg and trb for each color. At the time when the read operation from the pixel 100 of each color of R, G, and B to the holding unit 200 is completed, control represented by a period from time t8 to time t9 is performed. In the period from time t8 to t9, the reading operation from the holding unit 200 to the outside is performed by the pulses phs_r, phs_g, and phs_b from the horizontal shift register 400. The signals of the respective colors output at this time are signals in a state where the color deviation in the sub-scanning direction has already been reduced. For this reason, it is not necessary to provide an arithmetic circuit or the like for performing complex calculations in the subsequent circuit, and it becomes possible to suppress an increase in the circuit scale of the entire system, and color shift without deteriorating signal characteristics. It is possible to obtain a corrected good image.

  In addition, the position setting of the control pulse of each color in this embodiment is not limited to the above content. The color misregistration in the sub-scanning direction depends on the orientation in the sub-scanning direction and the color arrangement order as shown in FIG. For this reason, if the direction in the sub-scanning direction changes, the relationship between the color misregistration amounts of the respective colors also changes. For example, when the direction of the sub-scanning direction is reversed from that in FIG. 5, the control pulses of the R pixel array 110 and the G pixel array 120 are set to the color shift amount tbr and the B pixel array 130 as a reference as shown in FIG. 6. A setting that is moved by tbg is an optimal setting that reduces color misregistration. For this reason, the position setting of the control pulse for each color is determined according to the conditions to be used and the amount of generated color misregistration, and is not limited to the form shown in FIGS. Therefore, when there is no color misregistration amount (a level that is so small that it cannot be detected), the control pulse positions of the R pixel array 110, the G pixel array 120, and the B pixel array 130 may be aligned as shown in FIG.

  Note that the positional relationship between the control pulses pres and ptx and the control pulses pts and ptn is not necessarily limited to the relationships shown in FIGS. 4, 6, and 7. However, in order to prevent a difference in the amount of noise due to the color, as described above, it is uniform for all the pulses in units of color without breaking the relationship of the pulse positions of the control pulses pres, ptx, pts, and ptn. A control method in which the amount of deviation is set is preferable.

  Further, in the present embodiment, the holding unit 200 is configured by two sample and hold circuits (FIG. 3) for holding the reset signal and the accumulated charge signal. However, the present embodiment is not limited to this. Absent. For example, the holding unit 200 may be configured by a circuit having a clamp function or an amplification function that detects a difference between the reset signal and the accumulated charge signal. FIG. 11 is a configuration diagram of the photoelectric conversion apparatus according to the present embodiment when the holding unit 200 is configured by a circuit having a clamp function and an amplification function. The holding unit 200 corresponding to the R pixel array 110 outputs the difference between the reset signal and the accumulated charge signal to the output terminal Vout_r. The holding unit 200 corresponding to the G pixel array 120 outputs the difference between the reset signal and the accumulated charge signal to the output terminal Vout_g. The holding unit 200 corresponding to the B pixel array 130 outputs a difference between the reset signal and the accumulated charge signal to the output terminal Vout_b. A pixel signal from which the reset component is removed can be obtained based on the above difference. The holding unit 200 in FIG. 11 includes the circuit in FIG.

  The circuit shown in FIG. 12 is a switched capacitor amplifier including an operational amplifier opamp, capacitors cc and cf, a reference voltage vref, and a reset switch sw1, and a sample and hold circuit including switches sw2 and sw3 and a capacitor ct. In FIG. 12, a capacitor cc is an input capacitor of the switched capacitor amplifier and a clamp capacitor for detecting a difference between the reset signal from the pixel 100 and the accumulated charge signal. The clamping operation to the capacitor cc is controlled by opening / closing the switch sw1 with the reference voltage vref and the pulse ptn. The capacitor ct is a capacitor that holds the differential signal amplified by the switched capacitor amplifier. The sampling operation to the capacitor ct is controlled by opening / closing the switch sw2 by the pulse pts. The signal held in the capacitor ct is output to the subsequent circuit when the pulse phs goes high and the switch sw3 is turned on.

  FIG. 13 is a timing chart showing the operation of FIG. FIG. 13 shows an example in which the shift amount of the control pulse for each color corresponds to that in FIG. In FIG. 13, when the pulse ptn_r becomes high level during the period from time t1 to t2, the switch sw1 is turned on, the capacitor cf is reset, and the sampling operation of the reset signal of the R pixel array 110 to the capacitor cc is performed. Is done. At time t2, the pulse ptn_r becomes low level and the switch sw1 is turned off. Thereafter, at time t3, the difference signal between the accumulated charge signal of the R pixel array 110 and the reset signal detected by the capacitor cc is multiplied by cc / cf and held in the capacitor ct.

  Similarly, the circuit operation performed on the holding unit 200 corresponding to the R pixel array 110 described above also applies to the color shift amount trg and the holding unit 200 corresponding to the G pixel array 120 and the B pixel array 130, respectively. This is performed at a timing shifted by trb. When the read operation from the respective pixels 100 of the R pixel array 110, the G pixel array 120, and the B pixel array 130 to the holding unit 200 is completed, the control represented by the period from time t4 to time t5 is performed. During the period from time t4 to t5, the reading operation from the holding unit 200 to the outside is performed by the pulses phs_r, phs_g, and phs_b from the horizontal shift register 400. Each color signal output at this time is a signal in which the color misregistration in the sub-scanning direction has already been reduced, so that the same effect as in the case where the above-described holding unit 200 is a sample hold circuit as shown in FIG. 3 can be obtained. Is possible.

  Further, in the present embodiment, as described above, the reading operation to the outside is performed when the reading operation from the pixels 100 of all colors to the holding unit 200 is completed, but the present embodiment is limited to this. There is nothing. For example, as illustrated in FIG. 8, reading to the outside is performed in order from the color for which the reading operation to the holding unit 200 has been completed. That is, the read operation after the holding unit 200 is controlled by the pulses phs_r, phs_g, and phs_b of the horizontal shift register 400 in accordance with the pulse positions of the control pulses for the respective colors.

  In addition, it is necessary to prevent crosstalk via the power supply wiring caused by the operation timing being different for each color. Therefore, the power supply wirings connected to the pixel arrays 110, 120, and 130 for each color and the holding unit 200 can separate the power supply wirings between the pixel arrays 110, 120, and 130 for different colors and reduce the common impedance. desirable.

  FIG. 15 is a configuration diagram illustrating a preferable connection relationship between the power supply potential vdd and the ground potential gnd of each circuit in FIG. 1, and FIG. 16 is a circuit diagram illustrating a configuration example of the pixel 100 in FIG. The circuit of FIG. 16 is obtained by adding nodes of the power supply potential vdd and the ground potential gnd to the circuit of FIG. In FIG. 16, a transistor M4 corresponds to the current source Iref of FIG. 2, and is a current source transistor that allows a predetermined drain current to flow according to the voltage difference between the bias voltage vb and the ground potential gnd. The node of the power supply potential vdd is connected to the drains of the transistors M1 and M3. The node of the ground potential gnd is connected to the anode of the photodiode PD and the source of the transistor M4.

  In FIG. 15, reference numerals 501, 502, and 503 denote bias source circuits for generating the bias voltage vb applied to the pixels 100 of the respective colors. FIG. 17 is a diagram illustrating a configuration example of each of the bias source circuits 501 to 503 in FIG. The bias source circuits 501 to 503 have a current mirror circuit configured by the transistor M0 and the current source I0. The current source I0 is connected between the node of the power supply potential vdd and the node of the bias voltage vb. The transistor M0 has a drain and a gate connected to the node of the bias voltage vb, and a source connected to a node of the ground potential gnd.

  15 has the configuration shown in FIG. In FIG. 15, the power supply voltage is supplied to the R pixel array 110 and the holding unit 200 and the bias source circuit 501 corresponding to the R pixel array 110 by the power supply wiring of the red circuit power supply potential VDD_R and the ground potential GND_R. Similarly, the power supply voltage is supplied to the green circuits through the power supply wiring of the green circuit power supply potential VDD_G and the ground potential GND_G. Similarly, the power supply voltage is also supplied to the blue circuits by the power supply wiring of the blue circuit power supply potential VDD_B and the ground potential GND_B. The power supply wirings of the power supply potentials VDD_R, VDD_G, and VDD_B preferably have a higher impedance relationship than within the respective wirings, and this also applies to the power supply wirings of the ground potentials GND_R, GND_G, and GND_B.

  As described above, by separating the power supply wirings of the power supply potential and the ground potential according to colors, it is possible to reduce crosstalk between different colors. For example, in FIG. 4, immediately after the transfer operation of the R pixel array 110 is performed at time t7, the reset potential of the G pixel array 120 is sampled. At this time, the power supply potential VDD_R, the ground potential GND_R, and the bias potential vb are changed by the transfer operation of the R pixel array 110. However, since the power supply wiring and the bias line are separated, the red power supply fluctuation does not directly affect the green power supply potential, the ground potential, and the bias voltage. As a result, noise superimposed on the reset potential of the G pixel array 120 due to fluctuations in the power supply potential, ground potential, and bias voltage is sufficiently reduced, and good signal characteristics with little crosstalk between colors can be obtained. . In addition, the power supply separation eliminates the need to wait for the transient power supply fluctuations generated in the other colors described above to settle, which is advantageous for speeding up reading.

  FIG. 18 is a diagram for explaining a preferable light shielding method for optical black pixels (OB pixels) when power source separation is performed for each color. FIG. 18 is a top plan view of the pixel portion of FIG. 15, and the pixel arrays 110, 120, and 130 for each color are divided into regions of OB pixels, invalid pixels, and effective pixels. The pixel portion includes a top metal 1801, a photodiode 1802, and a transfer gate 1803. A metal opening formed by a top metal 1801 is provided on the upper surface of a part of the invalid pixel, the photodiode 1802 and the transfer gate 1803 of the effective pixel. In addition, incident light is blocked (shielded) by a top metal 1801 on a part of the invalid pixels and the upper surface of the photodiode 1802 of the OB pixel. In general, a metal wiring used for light shielding is often a power supply wiring of a pixel. However, when performing power source separation for each color, the power source wires for each color cannot be easily connected to relatively increase the impedance between the power source wires for each color. For this reason, a gap is formed between the pixel arrays of the respective colors, and incident light leaks from the gap, so that the light shielding performance of the OB pixel is deteriorated. In addition, when a light shielding metal on an OB pixel is formed with a power supply wiring of a specific color, there is a possibility that signal characteristics are deteriorated due to capacitive coupling between the power supply wiring that does not correspond to the color and the floating diffusion FD. Is not desirable because Therefore, the wiring of the power supply potential VDD_X in FIG. 18 is a metal wiring used for light shielding of the OB pixel. In addition, the power supply potential VDD_X is different from the power supply potentials VDD_R, VDD_G, and VDDB for each color, and it is preferable to use a power supply wiring having a relatively high impedance for the power supply potentials VDD_R, VDD_G, and VDD_B.

  Ideally, it is desirable that the power supply lines for each color be completely separated, but depending on the layout configuration and required performance, for example, as shown in FIG. 19, by separating the power supply lines immediately after the pad PAD, However, the same effect can be obtained. FIG. 19 is a diagram showing a wiring layout of power supply potentials VDD_R, VDD_G, VDD_B or ground potentials GND_R, GND_G, GND_B connecting the pad PAD of the power supply potential VDD or the ground potential GND and the pixel arrays 110, 120, 130 of each color. It is. In FIG. 19, the wirings of the power supply potentials VDD_R, VDD_G, VDD_B, and VDD_X are the power supply wirings of the same node supplied with power from the common pad PAD. However, by separating the wirings immediately after the pad PAD, the common impedance R0 Is lowered.

  The wiring of the power supply potential VDD_R or the reference potential GND_R has a parasitic resistance R1, the wiring of the power supply potential VDD_G or the reference potential GND_G has a parasitic resistance R2, and the wiring of the power supply potential VDD_B or the reference potential GND_B has a parasitic resistance R3. The wiring of the power supply potential VDD_X has a parasitic resistance R4. The parasitic resistances R1, R2, R3, and R4 are set so that the impedance between the power supply wirings of the power supply potentials VDD_R, VDD_G, VDD_B, and VDD_X is as high as possible. This makes it difficult for noise generated in each power supply line to be transmitted to other power supply lines. The same applies to the wiring of the ground potentials GND_R, GND_G, and GND_B. Note that the power supply wiring is not limited to the metal wiring, but can be obtained even in a substrate structure such as a well, thereby obtaining a higher noise reduction effect.

  In addition, the structural example of the pulse control part 300 in this embodiment is shown in FIG. In FIG. 9, an R counter 310, a G counter 320, and a B counter 330 are counters that count the clock signal clk, and the start of each count is controlled by an external control pulse trg_r, trg_g, trg_b. A pulse generation circuit 340 generates control pulses for each color according to the clock signal clk and the count values of the R counter 310, the G counter 320, and the B counter 330. When the count values of the R counter 310, the G counter 320, and the B counter 330 reach predetermined values, the pulse generation circuit 340 changes the control pulse of each color from the high level to the low level in synchronization with the clock signal clk. Change state from level to high level. The pulse generation circuit 340 subsequent to the R counter 310 generates control pulses pres_r, ptx_r, pts_r, and ptn_r according to the count value of the R counter 310. A pulse generation circuit 340 subsequent to the G counter 320 generates control pulses pres_g, ptx_g, pts_g, and ptn_g according to the count value of the G counter 320. The pulse generation circuit 340 at the subsequent stage of the B counter 330 generates control pulses pres_b, ptx_b, pts_b, and ptn_b according to the count value of the B counter 330.

  When the color misregistration occurs, the external control pulses trg_r, trg_g, trg_b are input so as to have a pulse position relationship corresponding to the color misregistration amount. Thereby, the count start positions of the counters 310, 320, and 330 are changed, and the positions of the control pulses of the respective colors can be controlled independently.

  As described above, in FIG. 9, the circuit configuration for adjusting the position of the control pulse for each color by providing the counters 310, 320, and 330 independently for each color has been described. However, the configuration of the pulse control unit 300 in this embodiment is the same. It is not limited to. For example, you may make it comprise the pulse control part 300 shown in FIG. The register group 360 can rewrite data stored by an external control pulse. One counter 350 starts counting the clock signal clk in response to the external control pulse trg. The data add_r, add_g, and add_b in the register group 360 are added to the count value of the counter 350 and output to the three pulse generation circuits 340 for each color. The three pulse generation circuits 340 for each color receive the above added values and generate control pulses for each color.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

100 pixels, 110 R pixel array, 120 G pixel array, 130 B pixel array, 200 holding unit, 300 pulse control unit, 400 horizontal shift register

Claims (7)

A plurality of pixel arrays each having a plurality of pixels in which different pixel arrays are arranged in the sub-scanning direction and each pixel array performs photoelectric conversion when the document is relatively scanned in the sub-scanning direction;
A pulse control unit for controlling a pulse position of a control pulse for controlling the operation of the pixel;
The photoelectric control apparatus, wherein the pulse control unit controls a pulse position of a control pulse of the pixel array of each color according to a color shift amount of the pixel array of each color in a sub-scanning direction.   The photoelectric conversion apparatus according to claim 1, wherein the pulse control unit generates a control pulse for controlling a charge accumulation period by photoelectric conversion of the pixel.   The control pulse includes a reset pulse for controlling a reset operation of the pixel, a transfer pulse for controlling a charge transfer operation for determining a charge accumulation period of the pixel, and a readout pulse for controlling a sample hold operation of the signal of the pixel. The photoelectric conversion device according to claim 1, comprising:   The photoelectric conversion apparatus according to claim 3, wherein the pulse control unit controls a change amount of a pulse position of the reset pulse, the transfer pulse, and the readout pulse with a uniform color shift amount for each color. And a color shift amount calculation unit that calculates a color shift amount in the sub-scanning direction when the plurality of pixel arrays scan the correction pattern image.
The said pulse control part controls the pulse position of the control pulse of the pixel array of each said color according to the color shift amount calculated by the said color shift amount calculation part, The any one of Claims 1-4 characterized by the above-mentioned. Item 1. The photoelectric conversion device according to item 1. And a power supply wiring for supplying a power supply voltage to the plurality of pixel arrays,
The photoelectric conversion device according to claim 1, wherein the power supply wiring is separated between the different color pixel arrays. The plurality of pixel arrays have optical black pixels that block incident light by metal,
The photoelectric conversion device according to claim 6, wherein the metal is separated from the power supply wiring.

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