JP2013206369A - Power supply controller, information processor and power supply control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply controller capable of easily resetting a PMU (Power Management Unit) even in a device in which a battery is not detachable.SOLUTION: The power supply controller includes: a power supply circuit 11 for supplying power to a CPU of an information processor; an MPU 32 for controlling the power supply circuit 11; and a power switch 2 for supplying an ON or OFF instruction of power supply to the MPU 32. The MPU 32 controls ON or OFF of the power supply supplied by the power supply circuit 11 on the basis of a prescribed program on condition that the ON or OFF instruction supplied from the power switch 2 is inputted, or turns OFF the power supply supplied by the power supply circuit 11 by the input of a prescribed reset signal, and further includes a depression time T2 detection circuit 4 for generating reset signals RST on condition that a prescribed input signal is in a prescribed state when the supply of the ON or OFF instruction from the power switch 2 continues for prescribed reference time.

Description

  The present invention relates to a power supply control device, an information processing device, and a power supply control method suitable for controlling power supplied to a CPU (Central Processing Unit) using a PMU (Power Management Unit) or the like.

  In an information processing apparatus that uses a battery as a power source and operates a CPU or the like according to a predetermined program, when the CPU runs away, the runaway of the CPU is stopped as follows. That is, the CPU is reset by supplying a predetermined reset signal, or the power of the CPU is shut off by removing the battery to stop the operation of the CPU. For example, in the in-vehicle computer described in Patent Literature 1, when the CPU cannot run out due to runaway, the car battery is prevented from rising as follows. That is, the in-vehicle computer described in Patent Document 1 includes a hardware timer that starts when the accessory switch is turned off, and a power supply control unit that turns off the power supplied to the CPU when the hardware timer times out. Have. When the CPU is not runaway, when the accessory switch is turned off, the CPU is shifted to a suspended state before the hardware timer times out, and current consumption is reduced. On the other hand, when the CPU is running out of control, the hardware timer activated when the accessory switch is turned off will time out. In this case, the power supplied to the CPU is turned off when the hardware timer times out.

JP 2000-228829 A

  Incidentally, a power supply control unit as described in Patent Document 1 may be configured using a power management semiconductor device called a PMU or the like. The PMU is a semiconductor device for managing power supplied to the CPU, etc., and is sometimes called a PMIC (Power Management IC) etc. The PMU is, for example, a battery voltage input into the PMU. A power supply circuit that converts the power into a predetermined voltage, a power supply control circuit that controls off / off of the power supply circuit, and the like. There is a case where control is performed to supply power by turning on / off the power supply or to supply power corresponding to various operation modes to an external CPU, etc. Therefore, the power supply control circuit includes CPU, MPU ( Micro Processing Unit) etc. Here, CPU and MPU are today In this application, the central processing unit in the PMU will be described as an MPU, and the central processing unit to which power is supplied from the PMU will be described as a CPU. The internal MPU operates by executing a predetermined program called firmware or the like stored in an internal ROM (Read Only Memory) etc. In the configuration using the PMU, a forced shutdown, that is, a personal computer ( Hereinafter, forced shutdown due to long pressing of a power switch (that is, power switch) in an information processing apparatus such as a PC) for a certain period of time or more may be performed under the control of the PMU.

  As described above, when the power supply to the CPU or the like is controlled using the PMU having the MPU, both the CPU and the MPU execute the program, so that the CPU may run out of control. There is a possibility that the operation of the PMU becomes abnormal due to the runaway of the MPU. The CPU runaway can be dealt with by forcibly shutting down the PMU by pressing and holding the power switch described above. However, if the PMU itself goes out of control, the forced shutdown by pressing and holding the power switch will not work. When the PMU itself runs out of control, for example, a notebook PC has to be forcibly shut down by cutting off the power supply to the PMU by detaching a battery and a desktop PC by removing an AC (alternating current) cord. Therefore, for example, in a device in which the battery cannot be detached, there is a problem that forced shutdown or the like when the PMU runs away cannot be easily performed.

  The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a power supply control device, an information processing device, and a power supply control method capable of solving the above-described problems.

  In order to solve the above problems, the present invention provides a power supply circuit that supplies power to a CPU of an information processing apparatus, a power supply control circuit that controls the power supply circuit, and an instruction to turn on or off the power supply to the power supply control circuit. The power supply control circuit controls the power supply on or off based on a predetermined program on condition that an input of an on or off command supplied from the switch is input, or The power is turned off by the input of a reset signal, and further, provided that the predetermined input signal is in a predetermined state when the supply of the on or off command from the switch continues for a predetermined reference time. And a reset signal generation circuit for generating the reset signal.

  According to the present invention, a power supply control circuit (for example, PMU) can be easily reset even in a device in which a battery is not removable.

It is the block diagram which showed the example of a structure of one Embodiment of this invention. 3 is a flowchart illustrating an operation example of the information processing apparatus 10 illustrated in FIG. 1. It is the block diagram which showed the structural example of other embodiment of this invention. It is the block diagram which showed the basic structural example of embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration example of an information processing apparatus 10 as an embodiment of the present invention. The information processing apparatus 10 shown in FIG. 1 includes a battery 1, a power switch 2, a PMU 3, a pressing time T2 detection circuit 4, a memory 5, a CPU 6, a chip set 7, an external I / F (interface) 8, and a peripheral module 9. doing. The information processing device 10 is, for example, a device such as a notebook PC, a portable information terminal device, or a mobile phone.

  The battery 1 is a rechargeable battery, and is provided in a form that cannot be easily detached from the information processing apparatus 10, for example. However, it may be provided in a detachable form.

  The power switch 2 is, for example, a push button switch, and is a switch that closes (or opens) the contacts only while being pressed by the user. The power switch 2 is used as a switch for turning on or off the power (that is, the power source) of the information processing apparatus 2. In the present embodiment, an on or off command signal PWSW that is in an active state while the power switch 2 is pressed is generated. Here, the active state of the signal PWSW may be high level or low level.

  The PMU 3 is a semiconductor device for managing power supplied to the CPU 6 and the like, and has an MPU 32. The power supply circuit 11 receives the terminal voltage of the battery 1, generates a plurality of direct current power supplies, and turns them on or off and outputs them under the control of the MPU 32. A plurality of systems of power output from the power supply circuit 11 are supplied to each unit in the information processing apparatus 10 such as the CPU 6, the memory 5, and the chip set 7. The MPU 32 includes a storage device such as a ROM 33, and by turning on or off each power output from the power supply circuit 11 according to various conditions by executing a predetermined program (ie, firmware) stored in the ROM 33. Control. For example, the MPU 32 controls each power supply output from the power supply circuit 11 to be turned on or off based on a predetermined program on condition that an on or off command signal PWSW supplied from the power switch 2 is input. The ROM 33 may be configured using a rewritable nonvolatile memory.

  The MPU 32 also outputs an on / off command to the power supply circuit 11 at a predetermined timing when the power switch 2 is kept pressed for a predetermined time T1 (for example, 4 seconds), and the CPU 6, the chipset 7, etc. Turn on or off the power supplied to the. At this time, the MPU 32 resets the CPU 6 and the chipset 7 after outputting or outputting the on / off command to the power supply circuit 11 when the power switch 2 is kept pressed for a predetermined time T1. The signal RESET or the shutdown signal SHDN may be output. Further, the MPU 32 controls to turn on or off the power of at least some of the plurality of systems output from the power supply circuit 11 or change the voltage based on the control signal CNTR input from the CPU 6. May be performed.

  The MPU 32 is further reset and restarted when the reset signal RST is input from the pressing time T2 detection circuit 4. The pressing time T2 detection circuit 4 outputs a reset signal RST when the power switch 2 is continuously pressed for a predetermined time T2, as will be described later. The time T2 is set longer than the time T1, for example, 15 seconds.

  When the reset signal RST is input from the pressing time T2 detection circuit 4 and the MPU 32 is restarted, the MPU 32 executes a predetermined program stored in the ROM 33, thereby executing all the systems output from the power supply circuit 11. The power supply or the power supply of at least a part of the plurality of systems is turned off to shift to a standby state. Next, the MPU 32 maintains this standby state until the power switch 2 continues to be pressed for a predetermined time (for example, time T1), and when a long press is performed for a predetermined time (for example, time T1), the CPU 6 and the chipset 7 Is supplied with power (and a reset signal RESET is further supplied), and the CPU 6 and the chip set 7 are activated. That is, when the power switch 2 is pressed for a long time in the power-on state (in the case of a long press of T1 or more and less than T2), the PMU 3 turns off the power supplied to the CPU 6 and the like and shuts down the information processing apparatus 10. On the other hand, when the power switch 2 is pressed for a long time in the power-off state (in the case of a long press of T1 or more and less than T2), the PMU 3 turns on the power supplied to the CPU 6 and activates the CPU 6 and the like. On the other hand, when the power switch 2 is pressed for a long time in the power-on state, such as when the PMU 3 is running out of control (in the case of a long press of T2 or more), the PMU 3 receives the reset signal RST from the pressing time T2 detection circuit 4. Reset. When reset by the reset signal RST, the PMU 3 restarts, turns off the power supplied to the CPU 6 and the like, and shifts to a standby state (that is, a state of waiting for a power-on instruction by long pressing of the power switch 2).

  When the supply of the on / off command signal PWSW from the power switch 2 continues for a predetermined reference time T2 (for example, 15 seconds), the pressing time T2 detection circuit 4 generates the reset signal RST under the following conditions. . That is, when the on / off command signal PWSW continues for the reference time T2, the pressing time T2 detection circuit 4 has a predetermined input signal (in this case, the same on or off command signal PWSW) in a predetermined state (in this case, the on Alternatively, the reset signal RST is generated on condition that the off command signal PWSW is active). In the example shown in FIG. 1, the pressing time T2 detection circuit 4 includes a T2 timer 41, a reference value generation circuit 42, and a comparator 43. The T2 timer 41 measures the time during which the on / off command signal PWSW is supplied from the power switch 2 and outputs a signal representing the measured value. The reference value generation circuit 42 generates a signal having a value (reference value) corresponding to the reference time T2 when a predetermined input signal (in this case, the ON or OFF command signal PWSW) is in a predetermined state (ie, active). . The comparator 43 compares the output of the T2 timer 41 and the output of the reference value generation circuit 42, and generates and outputs a reset signal RST when the outputs match.

  The memory 5 includes a nonvolatile memory and a volatile memory, and stores a program executed by the CPU 6 in the nonvolatile memory.

  The CPU 6 operates using a predetermined power source supplied from the PMU 3 and executes a predetermined program stored in the memory 5. The CPU 6 transmits / receives data to / from a predetermined external device via the external I / F 8, controls the peripheral module 9 via the chip set 7, and transmits / receives data to / from the peripheral module 9. The CPU 6 restarts when the reset signal RESET is input from the PMU 3. In addition, the CPU 6 outputs a predetermined control signal CNTR to the PMU 3 when each unit is put into a suspended state or an off state, and controls the power supplied from the PMU 3 to an on or off state.

  The chip set 7 mediates the flow of data input / output between the CPU 6 and the external I / F 8 or between the peripheral modules 9.

  The external I / F 8 includes, for example, a serial interface and a predetermined cable connection terminal, and is connected between the CPU 6 and a predetermined external device or between the CPU 6 and the predetermined external device via the chip set 7. Mediates signal input and output.

  The peripheral module 9 represents a plurality of types of peripheral devices. When the information processing apparatus 10 is, for example, a notebook PC, the peripheral module 9 includes, for example, a display module including a liquid crystal display device, a voice input / output device, a voice input / output module including a speaker and a microphone, and an operation input including a keyboard and a touch panel. Includes modules etc. Further, when the information processing apparatus 10 is, for example, a mobile phone or a portable information terminal device, a communication module including a wireless communication device or the like, a display module including a liquid crystal display device or the like, a voice input / output device including a speaker, a microphone, or the like. It includes modules, operation input modules consisting of keyboards and touch panels.

  Next, an operation example of the information processing apparatus 10 illustrated in FIG. 1 will be described with reference to FIG. Now, it is assumed that the user presses and holds down the power switch 2 to shut down the information processing apparatus 10. If the power switch 2 continues to be pressed, the ON or OFF command signal PWSW continues and becomes active. In this case, the MPU 32 starts (or continues) measuring the duration time of the active state after the on or off command signal PWSW becomes active (step S1). In parallel, the T2 timer 41 also starts (or continues) measuring the duration of the active state after the on / off command signal PWSW becomes active (step S1). On the other hand, the reference value generation circuit 42 outputs a reference value indicating the value of the time T2 after the ON or OFF command signal PWSW becomes active.

  If the power switch 2 continues to be pressed (“Yes” in step S2), the MPU 32 determines whether or not the pressing duration time matches the time T1 (step S3), and if not, returns to step S1. , MPU 32 continues to count the active state (from step S3, “(= T1 or = T2) is not” to step S1). When the power switch 2 continues to be pressed (in the case of “Yes” in step S2), the comparator 43 compares the output of the T2 timer with the output of the reference value generation circuit 42 in parallel. (That is, it is determined whether or not the pressing duration is equal to T2) (step S3). If they do not match, the process returns to step S1, and the T2 timer 41 continues to count the active state (from step S3, “(= T1 or = T2) is not” to step S1).

  On the other hand, when the power switch 2 is not continuously pressed in step S2 (“No” in step S2), the MPU 32 and the T2 timer 41 reset the time count value in the active state (step S4). In parallel, the reference value generation circuit 42 stops outputting the reference value of the value corresponding to the time T2 after the ON or OFF command signal PWSW is no longer in the active state (step S4). Then, it returns to step S1.

  Now, assuming that the pressing duration of the power switch 2 coincides with the time T1, if the MPU 32 does not run out of control, the MPU 32 determines that the depression duration coincides with T1 (“= T1” in step S3). In this case, the MPU 32 outputs the shutdown signal SHDN to the CPU 6 and the like, and then shuts down the CPU 6 and the like by turning off the predetermined power supply of the power supply circuit 11 (step S5). Thereby, the shutdown by the PMU 3 main body is completed.

  On the other hand, when the MPU 32 runs away, the MPU 32 determines that the pressing duration time has coincided with T1 (“= T1” in step S3), and the shutdown process cannot be performed mainly by the PMU 3 in step S5. In this case, the MPU 32 remains uncontrollable at the time when the pressing duration time T1 matches, and then the comparator 43 determines that the pressing duration time matches T2 when the pressing duration time matches time T2. ("= T2" in step S3). In this case, the comparator 43 generates the reset signal RST and forcibly resets the MPU 32 (step S6). Thereby, the MPU 32 shuts down the CPU 6 and the like by forcibly turning off the predetermined power supply of the power supply circuit 11 as an operation after reset (step S7).

  As described above, in the information processing apparatus 10 of this embodiment, the pressing time of the power switch 2 is monitored by both the PMU 3 and the pressing time T2 detection circuit 4. The pressing time T1 is monitored by the PMU 3, and the pressing time T2 is monitored by the pressing time T2 detection circuit 4. Here, T1 <T2, for example, T1 = 4 seconds and T2 = 15 seconds. When the CPU 6 or the like runs away, the information processing apparatus 10 is shut down in step S5 or step S6 by the user pressing and holding the power switch 2 for a long time. That is, when the PMU 3 is not running away, when the PMU 3 detects that the pressing time T1 has elapsed, a shutdown process by the PMU 3 main body is performed in step S5. On the other hand, when the PMU 3 runs away, the shutdown process by the PMU 3 cannot be performed even when the pressing time T1 elapses. In this case, when the pressing time T2 detection circuit 4 detects the pressing time T2, the PMU 3 itself is forcibly reset in step S6, and the PMU 3 performs a shutdown process in step S7.

  Therefore, according to the present embodiment, when the supply of the on / off command signal PWSW from the power switch 2 continues for the predetermined reference time T2, the on / off command signal PWSW from the power switch 2 is in the active state. As a condition, a reset signal RST for the MPU 32 of the PMU 3 is generated, and the power output from the power supply circuit 11 is turned off. Therefore, even if the information processing device 10 is a device that cannot be detached from the battery, the PMU 3 can be easily reset.

  Next, a modified example of the information processing apparatus 10 illustrated in FIG. 1 will be described with reference to FIG. 3, the same reference numerals are used for the same components as those in FIG. The information processing apparatus 10a illustrated in FIG. 3 is provided with a new stop switch 21 with respect to the information processing apparatus 10 illustrated in FIG. 1 and the input of the reference value generation circuit 42 is supplied from the stop switch 21. The stop command signal STSW is different. The stop switch 21 is, for example, a push button switch arranged at a position different from the power switch 2. In the information processing apparatus 10a, when the stop switch 21 is pressed, the reference value generation circuit 42 outputs a reference value of a value corresponding to the time T2. Therefore, if the stop switch 21 is pressed when the T2 timer 41 outputs a value corresponding to the time T2 by continuing to press the power switch 2, the comparator 43 outputs the reset signal RST. According to the information processing apparatus 10a, the user can reset the PMU 3 by continuously pressing the power switch 2 for T2 time and pressing the stop switch 21 when the T2 time elapses. The operation of the information processing apparatus 10a is the same as that shown in FIG. 2 except for the following points. That is, in the operation of the information processing apparatus 10a, the condition that step S6 of FIG. 2 is executed (that is, the determination condition of step S3) matches the T2 time, and the stop switch 21 is pressed down. It is changed to the condition that it has been.

  According to this embodiment, in addition to long-pressing the power switch 2, the PMU 3 is reset by long-pressing the stop switch 21 (or pressing at least when T2 time elapses). According to this, for example, when the user presses and holds down the power switch 2 in an attempt to turn off the power, an erroneous operation in which the PMU 3 is erroneously reset and the PMU 3 is erroneously reset is prevented. can do.

  The basic configuration of the embodiment of the present invention can be expressed as shown in FIG. The power supply control device 100 illustrated in FIG. 4 includes a power supply circuit 101, a switch 102, a power supply control circuit 103, and a reset signal generation circuit 104. Here, the power supply circuit 101 corresponds to the power supply circuit 11 of FIG. The switch 102 corresponds to the power switch 2 in FIG. The power supply control circuit 103 corresponds to the MPU 32 in FIG. The reset signal generation circuit 104 corresponds to the pressing time T2 detection circuit 4 in FIG.

  The power supply circuit 101 shown in FIG. 4 supplies power to a CPU (not shown). The switch 102 supplies a power supply control circuit 103 with a power on / off command supplied from the power supply circuit 101. The power supply control circuit 103 controls the power supply circuit 101. The power supply control circuit 103 controls the power supplied by the power supply circuit 101 to be turned on or off based on the input of an on or off command supplied from the switch 102, or a predetermined reset signal. The input is turned off. The reset signal generation circuit 104 is a reset input to the power supply control circuit 103 on condition that a predetermined input signal is in a predetermined state when the supply of an ON or OFF command from the switch 102 continues for a predetermined reference time. Generate a signal. Here, the predetermined input signal input to the reset signal generation circuit 104 may be supplied from the switch 102, or may further include a second switch (not shown) different from the switch 2, It may be supplied from a switch.

  According to the configuration shown in FIG. 4, when a switch 102 (for example, the power switch 2 in FIG. 1 or 3) continues to supply an on or off command for a predetermined reference time (for example, time T1), the predetermined input signal A reset signal (RST) for the power supply control circuit 103 (for example, the MPU 32 of the PMU 3 in FIG. 1) is provided on condition that the pressing signal of the power switch 2 in FIG. 1 or the pressing signal of the stop switch 21 in FIG. ) Is generated and the power is turned off. Therefore, the power supply control circuit 103 (for example, PMU 3) can be easily reset even in a device in which the battery cannot be removed.

  The embodiment of the present invention is not limited to the above, and for example, the following modifications can be made as appropriate. That is, the PMU 3 in FIG. 1 may further include a circuit that generates a clock signal, or the power supply circuit 11 may be divided into a plurality of blocks. The MPU 32 omits or increases some or all of the control signals transmitted to and received from the CPU 6 and the chip set 7 shown in FIG. Control signals and clock signals can be transmitted and received between them.

1 Battery 2 Power Switch 3 PMU
4 Pressing time T2 detection circuit 5 Memory 6 CPU
7 Chipset 8 External I / F
9 Peripheral module 10, 10a Information processing device 11 Power supply circuit 21 Stop switch 32 MPU
33 ROM
41 T2 Timer 42 Reference Value Generation Circuit 43 Comparator 100 Power Supply Control Device

Claims (6)

A power supply circuit for supplying power to the CPU of the information processing apparatus;
A power supply control circuit for controlling the power supply circuit;
A switch for supplying an instruction to turn on or off the power supply to the power supply control circuit,
The power supply control circuit controls the power supply to be turned on or off based on a predetermined program on condition of input of an on or off command supplied from the switch, or turns off the power supply by input of a predetermined reset signal. Is what
And a reset signal generation circuit that generates the reset signal on condition that a predetermined input signal is in a predetermined state when the supply of the ON or OFF command from the switch continues for a predetermined reference time. A power supply control device. The power supply control device according to claim 1, wherein the predetermined input signal is supplied from the switch. A second switch different from the switch;
The power supply control device according to claim 1, wherein the predetermined input signal is supplied from the second switch. The reset signal generation circuit includes:
A timer circuit for timing the time during which the on or off command is supplied from the switch;
A reference value generating circuit for generating a predetermined reference value corresponding to the predetermined reference time when the predetermined input signal is in the predetermined state;
4. The power supply control device according to claim 1, further comprising a comparison circuit that compares an output of the timer circuit and an output of the reference value generation circuit. 5. The CPU;
An information processing apparatus comprising: the power supply control device according to claim 1. A power supply circuit for supplying power to the CPU of the information processing apparatus;
A power supply control circuit for controlling the power supply circuit;
A switch for supplying an instruction to turn on or off the power supply to the power supply control circuit;
Using a reset signal generation circuit that generates a predetermined reset signal on condition that a predetermined input signal is in a predetermined state when the supply of the ON or OFF command from the switch continues for a predetermined reference time,
The power supply control circuit controls the power supply to be turned on or off based on a predetermined program on condition of input of an on or off command supplied from the switch, or turns off the power supply by input of the reset signal. And a power control method.

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