JP2013201479A - Encoding device, storage device and encoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an encoding device that has a degree of freedom in the order of data input to the encoding device.SOLUTION: The encoding device for encoding data to be encoded which comprises L (L is an integer of two or more) data blocks includes an encoding circuit for performing an encoding process on the data blocks, and L position adjustment circuits for generating parity depending on the position of the data blocks in the data to be encoded for the respective data blocks on the basis of parity generated by the encoding process.

Description

  The present embodiment relates to an encoding device, a storage device, and an encoding method.

  In a conventional encoding apparatus that performs BCH encoding or the like, data is input to the encoding apparatus and encoded in a predetermined order in order to match the input order to the decoding apparatus at the time of decoding. If the data input order to the encoding device is changed, the data input order of the decoding device is not matched and decoding cannot be performed.

JP 2009-212623 A JP 2009-211742 A

  Embodiments of the present invention provide an encoding device, a storage device, and an encoding method that have degrees of freedom in the order of data input to the encoding device.

  According to one aspect of the present invention, there is provided an encoding device that encodes encoding target data composed of L (L is an integer of 2 or more) data blocks, and performs encoding processing on the data blocks. An encoding circuit to perform, and L position adjustment circuits that generate a parity corresponding to the position of the data block in the data to be encoded for each data block based on the parity generated by the encoding process. .

FIG. 1 is a block diagram illustrating a configuration example of an encoding device according to the first embodiment. FIG. 2 is a diagram illustrating a data configuration example in a case where the encoding target data includes a plurality of data blocks. FIG. 3 is a diagram illustrating an example of a data input order in an encoding / decoding system using an encoding apparatus according to a comparative example. FIG. 4 is a diagram illustrating an example of the order of data input to the ECC decoding circuit. FIG. 5 is a diagram illustrating a configuration example of the ECC encoding processing circuit. FIG. 6 is a diagram illustrating a configuration example of the position adjustment circuit. FIG. 7 is a diagram illustrating a configuration example of the position adjustment circuit. FIG. 8 is a block diagram of a configuration example of the storage device according to the second embodiment. FIG. 9 is a diagram illustrating a configuration example of an encoding unit according to the second embodiment. FIG. 10 is a diagram illustrating an example of an encoding process procedure according to the second embodiment. FIG. 11 is a diagram illustrating a configuration example of the position adjustment circuit. FIG. 12 is a diagram illustrating a configuration example of the position adjustment circuit. FIG. 13 is a diagram illustrating a configuration example of the position adjustment circuit. FIG. 14 is a diagram illustrating a configuration example of the position adjustment circuit. FIG. 15 is a diagram illustrating an example of the intermediate result (parity #i ′) and the output parity #i. FIG. 16 is a diagram illustrating an example of input information and 0 input. FIG. 17 is a diagram illustrating specific examples of the intermediate result (parity #i ′) and the position-adjusted parity (parity #i) when the information in FIG. 16 is input. FIG. 18 is a diagram illustrating a configuration example of an encoding unit according to the third embodiment.

  Exemplary embodiments of an encoding device, a storage device, and an encoding method will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

  FIG. 1 is a block diagram illustrating a configuration example of an encoding device according to the first embodiment. As shown in FIG. 1, the encoding apparatus according to the present embodiment includes an ECC (Error Checking and Correction) encoding circuit (encoding circuit) 1 and a position adjustment circuit 2.

  In this embodiment, an example in which a BCH code is used as a code generated by the encoding device will be described. However, the code generated by the encoding device is another error correction code such as a Reed-Solomon code (RS code). It may be an error detection code such as CRC (Cyclic Redundancy Check), and is not limited to a BCH code.

  In the encoding device of the comparative example, data is input to the encoding device and encoded in a predetermined order in order to match the input order to the decoding device at the time of decoding. For example, when one encoding target data is composed of a plurality of data blocks, it is necessary to input the data blocks in a predetermined order. For this reason, when the arrival order of the data blocks is different from the input order to the encoding apparatus, the arrived data blocks are stored in the buffer, rearranged in the input order, and input to the encoding apparatus. For this reason, a buffer is required and the speed of the encoding process is also reduced.

  FIG. 2 is a diagram illustrating a data configuration example in a case where the encoding target data includes a plurality of data blocks. In the example of FIG. 2, the encoding target data includes NB + 1 data blocks from data block # 0 to data block #NB (NB is an integer equal to or greater than 1). When generating a codeword based on the data to be encoded shown in FIG. 2, generally, data block # 0, data block # 1, data block # 2,. Are input to the encoding device in a predetermined order. Even when data is not input to the encoding device in a predetermined order, since the decoding device inputs data in a predetermined order, the input order of data differs between encoding and decoding, and decoding cannot be performed correctly. It is conceivable that the input order of data to the encoding device is managed and the decoding device changes the input order for each encoding target data. However, in this case, the management data becomes enormous and the processing speed decreases.

  FIG. 3 is a diagram illustrating an example of a data input order in an encoding / decoding system using an encoding apparatus according to a comparative example. FIG. 3 is a diagram illustrating an example of a data input order in the ECC encoding circuit 101 which is an encoding apparatus according to a comparative example. In FIG. 3, for simplification of the figure, NB = 3, and the data input order (data block # 0, data block # 1, data block # 2, An example of the order of data block # 3 is shown. The ECC decoding circuit 102 performs a decoding process based on the data and the parity generated by the ECC encoding circuit 101. At this time, the input order of the data input to the ECC decoding circuit 102 is the same as the input order to the ECC encoding circuit 101. FIG. 4 is a diagram illustrating an example of the order in which data is input to the ECC decoding circuit 102. FIG. 4 shows the input order of data to the ECC decoding circuit 102 when data is input in the input order shown in FIG. 3 in the encoding process.

  For example, in the data configuration example of FIG. 2, when it is determined that decoding is performed in the order of data block # 0, data block # 1, data block # 2, and data block # 3, data block # 3 is data Assume that the encoder arrives before the blocks # 0, # 1, and # 2.

  In the configuration example of the comparative example shown in FIG. 3, it is assumed that the data block # 3 arrives at the ECC encoding circuit 101 earlier than the data blocks # 1 and # 2. In this case, since the ECC encoding circuit 101 cannot input the data block # 3 before inputting the data blocks # 0, # 1, and # 2, the data blocks # 0, # 1, and # 2 arrive. Until the data block # 3 is held.

  On the other hand, if data block # 3 can be input and encoded before data blocks # 0, # 1, and # 2, it is not necessary to retain data block # 3, and the encoding process starts. There is no need to wait. For example, if the encoding process can be performed using a part of data at an arbitrary position in the encoding target data, the data block # 3 can be input first and it is necessary to wait for the start of the encoding process. Nor. However, if the encoding process is simply performed using the data block # 3, only the data word corresponding to the bits in the data is generated for the data block # 3. Therefore, by simply encoding data block # 3, data block # 0, # 1, and data block # 2, in order, NB + 1 code words respectively corresponding to NB + 1 data blocks in the encoding target data can be obtained. In other words, the ECC decoding circuit 102 that performs decoding on the assumption that the entire data to be encoded has been encoded cannot be decoded.

When there is no position adjustment function for performing encoding processing using a part of data at an arbitrary position, the following two problems occur depending on the implementation method.
(1) When encoding is performed for each of NB + 1 data blocks, NB + 1 codewords corresponding to NB + 1 data blocks are possible, and cannot be integrated into one codeword.
(2) Encoding NB + 1 data blocks in a certain order (using the parity of the data block input first to the encoding circuit as an intermediate result as the initial value for the parity calculation of the subsequent data block) In this case, since one code word corresponding to only this order of the NB + 1 data blocks is generated, the NB + 1 data blocks must be input to the decoding circuit in this order. On the contrary, there is a dependency relationship that if the data input order to the decoding circuit is determined, the data input order to the encoding circuit is also determined.

  In the present embodiment, the ECC encoding circuit 1 performs an encoding process using a part of data at an arbitrary position in the encoding target data. Then, the position adjustment circuit 2 applies the parity generated by the encoding process by the ECC encoding circuit 1 so that it can be correctly decoded when decoding is performed on the assumption that the entire encoding target data is encoded. Adjust the position. The position adjustment circuit 2, when performing encoding using a part of data in the encoding target data as an input, for the parity generated by the encoding process according to the position of the data in the encoding target data Adjust the bit position. As a result, even if encoding processing is performed in an order different from the input order in decoding processing, such as data block # 3, data block # 0, data block # 1, and data block # 2, position adjustment is performed. Using the parity of each subsequent data block, it is possible to generate a decodable parity by a decoding process on the assumption that the entire data to be encoded is encoded in a predetermined order. Hereinafter, a decoding process that assumes that the entire encoding target data has been encoded in a predetermined order is referred to as a prescribed decoding process.

  Specifically, the position adjustment circuit 2 corresponds to, for example, that 0 is input to a portion where no actual data exists in the encoding target data with respect to the codeword generated by the ECC encoding circuit 1. Processing (hereinafter referred to as 0 padding) is performed.

Here, it will be described that by performing the position adjustment as described above, it is possible to generate a decodable parity by the prescribed decoding process. Here, a description will be given assuming that the ECC encoding circuit 1 generates a cyclic code. When the k-bit information (corresponding to the data to be encoded in FIG. 2) is (d ₀ , d ₁ ,..., d _k-1 ), the n-bit cyclic code (c ₀ , c _{1 ,. −1} , d ₀ , d ₁ ,..., D _k-1 ). (C ₀ , c ₁ ,..., C _m−1 ) are check bits (parity), and n = m + k.

To create an n-bit cyclic code (c ₀ , c ₁ ,..., c _m−1 , d ₀ , d ₁ ,..., d _k− 1), as expressed by the following equation (1): Then, division by the generator polynomial G (x) is performed. P (x) is a polynomial corresponding to the information bits, and F (x) is a polynomial corresponding to the cyclic code (code word).

The remainder R (x) obtained by performing the division shown in the above equation (1) is a polynomial corresponding to the check bits (c ₀ , c ₁ ,..., C _m−1 ). By adding this check bit to the information bits (d ₀ , d ₁ ,..., D _k-1 ), n-bit cyclic codes (c ₀ , c ₁ ,..., C _m−1 , d ₀ , d _1). , ..., d _k-1 ).

  F (x), G (x), and R (x) can be represented by the following formula (2).

That is, when the quotient of the division in (1) is Q (x), F (x) can be expressed by the following equation (3).
F (x) = G (x) Q (x) = x ^nk P (x) + R (x) (3)

When k bits of information bits are divided into t data blocks, and the first data block, the second data block,... are sequentially from the bit position corresponding to the 0th order term, the first data block is i bits. The total number of bits of the first and second data blocks is j bits, and the total number of bits of the first to t−1th data blocks is l. At this time, P (x) is a polynomial P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x) corresponding to each data block as shown in the following equation (4). ) Is added.

As shown in the above equation (4), the polynomials P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x) corresponding to each data block correspond to each data block. The term corresponding to the bit position to be multiplied is multiplied by the value corresponding to the information, but 0 is multiplied in the other terms.

  From the above formulas (3) and (4), F (x) can be expressed by formula (5).

The check bit polynomials for P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x) are R ₁ (x), R ₂ (x), R ₃ (x), ..., R _t (x), the remainder of {R ₁ (x) + R ₂ (x) + R ₃ (x) + ... + R _t (x)} / G (x) is R (x )

Since Q (x) is the quotient of (1) above, and R (x) is the remainder of (1) above, the following equation (6) is obtained.
x ^nk P (x) / G (x) = Q (x) + R (x) / G (x) (6)
From the above formula (6) and the above formula (4), the following formulas (7) and (8) are obtained.
x ^nk {P ₁ (x) + P ₂ (x) +... + P _t (x)} / G (x)
= Q (x) + R (x) / G (x) (7)
x ^nk {P ₁ (x) + P ₂ (x) +... + P _t (x)} / G (x)
= X ^nk P ₁ (x) / G (x) + x ^nk P ₂ (x) / G (x) +... + X ^nk P _t (x) / G (x)
(8)

If the quotient of x ^nk P _i (x) / G (x) in the above equation (8) is Q _i (x) and the remainder is R _i (x), the following equation (9) is established.
_{^{x nk P i (x) /}} G (x) = Q i (x) + R i (x) / G (x) ... (9)

From the above formulas (7), (8), and (9), the following formulas (10) and (11) are derived.
Q ₁ (x) + R ₁ (x) / G (x) + Q ₂ (x) + R ₂ (x) / G (x) +
... + Q _t (x) + R _t (x) / G (x) = x ^nk P (x) / G (x)
= Q (x) + R (x) / G (x) (10)
{R ₁ (x) + R ₂ (x) +... + R _t (x)} / G (x)
_{= Q (x) -Q 1 (} x) -Q 1 (x) - ... -Q t (x) + R (x) / G (x) ... (11)
From the above equation (11), the remainder of {R ₁ (x) + R ₂ (x) + R ₃ (x) +... + R _t (x)} / G (x) is also R (x).

Since the highest order of R ₁ (x) + R ₂ (x) + R ₃ (x) +... + R _t (x) is the same m−1 order as R (x), R (x) is expressed by the following formula ( 12), R ₁ (x), R ₂ (x), R ₃ (x),..., R _t (x) are added (exclusive OR).
R ₁ (x) + R ₂ (x) + R ₃ (x) +... + R _t (x) = R (x) (12)

Thus, based on P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x), R ₁ (x), R ₂ (x), R ₃ (x) ,..., R _t (x), the check bit R (x) corresponding to k-bit information can be obtained. From the above, R ₁ (x), R ₂ (x), R ₃ (x),..., R _t (x) can be calculated in any order. For this reason, it is possible to perform calculation by performing encoding in the order of arrival of the data blocks or by parallel encoding of a plurality of data blocks.

In the present embodiment, first, the ECC encoding circuit 1 performs a normal encoding process based on the data length of each data block based on each data block, and obtains a check bit (parity) as an intermediate result. Then, the position adjustment circuit 2 is based on P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x) shown in the above equation (2) based on the intermediate result. Check bits corresponding to the generated check bits R ₁ (x), R ₂ (x), R ₃ (x),..., R _t (x) are generated. Specifically, the bit corresponding to the term multiplied by 0 in P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x) shown in the above equation (2). A process corresponding to the input of 0 is performed. This process may be realized by any specific circuit, and may be a process of inputting 0 to a bit corresponding to a term actually multiplied by 0, a process of shifting a bit, or the like. May be realized.

This implementation is also performed when only a part of information (data) corresponding to P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x) is finally obtained. Position adjustment in the form of can be applied. For example, this corresponds to a case where only data block # 3 arrives in FIG. 2 and data of other data blocks do not arrive. Also in this case, R ₁ (x), R ₂ based on P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x) corresponding to the data block from which information is obtained. (X), R ₃ (x), ..., R _t (x) are generated, and the generated R ₁ (x), R ₂ (x), R ₃ (x), ..., R _t (x) are added. Thus, R (x) is obtained (if the generated R ₁ (x), R ₂ (x), R ₃ (x),..., R _t (x) is one, it is used as it is). Thereby, for example, even if data is stored and transmitted only in some data blocks of the encoding target data for data compression or the like, it can be decoded by the normal decoding process as usual.

FIG. 5 is a diagram illustrating a configuration example of the ECC encoding processing circuit 1. FIG. 5 shows a configuration example of the ECC encoding processing circuit 1 when the generator polynomial G (x) = x ³ + x + 1 is used. As shown in FIG. 5, the ECC encoding processing circuit 1 includes registers (R) 11, 12, 13, adders 14, 18, 19, and gates 15, 16, 17. FIG. 5 is an example, and the configuration and generator polynomial of the ECC encoding processing circuit 1 are not limited to the example of FIG.

6 and 7 are diagrams illustrating a configuration example of the position adjustment circuit 2. In the above-described P ₁ (x), P ₂ (x), P ₃ (x),..., P _t (x), the higher-order bits (for example, P ₂ (x)) than the bit position where the actual information exists. in the x ^{j + 1} and bit) corresponding to the terms up to x ^k-1, the actual lower order than the bit position where information exists of bits (e.g., P ₂ (x) from the x ⁰ to x ^i-1 The bit corresponding to the above term is 0, but the result is the same regardless of whether or not 0 is input for bits of higher order than the bit position where the actual information exists. Therefore, in the configuration examples of FIGS. 6 and 7, a configuration is shown in which 0 is input to higher-order bits than the bit position where the actual information exists. FIG. 6 shows an example in which the parity is 3 bits.

  In the configuration example of FIG. 6, the position adjustment circuit 2 includes a selector 4, an XOR gate 5, and an FF (FlipFlop) 6. The position adjustment circuit 2 is controlled by an internal or external control unit 3 according to the number of repetitions (1, 2, or 3) according to the number of bits to be adjusted (the number of bits in which 0 is input in a higher order than the bit position where the actual information exists). Times) is controlled. The selector 4 selects and outputs either the input intermediate result (parity generated by the ECC encoding processing circuit 1) or the output of the FF 6 under the control of the control unit 3. In the first time, the selector 4 selects the inputted intermediate result, and thereby 1 bit 0 is inputted. In the second time and the third time, the selector 4 selects the output of the FF 6. Thereby, 2 bits can be input 2 times and 3 bits 0 can be input 3 times. Thus, the number of bits to be adjusted can be changed according to the number of repetitions.

  The configuration example of FIG. 7 includes, for example, an s-bit position adjustment circuit 8 capable of 0-input of s bits (3 bits in the case of FIG. 6), a selector 7 and an FF 9 as shown in FIG. When the control unit 3 controls the s bit position adjusting circuit 8 to input s bit 0, the control unit 3 performs s bit units such as s bit, 2 s bit, 3 s bit,. 0 can be input. The selector 7 selects the input intermediate result in the first iteration, and thereby inputs the s bit 0. In the second and third times, the selector 7 selects the output of the FF 9. As a result, 2s bits can be input 2 times, and 3s bits 0 can be input 3 times. 6 and 7 are examples, and the configuration of the position adjustment circuit 2 is not limited to these.

  As described above, in the present embodiment, the ECC encoding processing circuit 1 that performs encoding processing using a part of the data to be encoded, and the parity generated by the ECC encoding processing circuit 1 are used. And a position adjusting circuit 2 for generating a parity whose bit position has been adjusted. Accordingly, it is possible to perform decoding on the assumption that the entire data to be encoded has been encoded using the parity whose bit position has been adjusted. Therefore, the degree of freedom can be given in the order of data input to the encoding device, and the calculation speed can be improved and the number of buffers can be reduced.

(Second Embodiment)
FIG. 8 is a block diagram of a configuration example of the storage device 21 according to the second embodiment. As illustrated in FIG. 8, the storage device 21 includes a memory controller 22 and a semiconductor memory unit 23. The storage device 21 is connected to the host 24 via a communication interface and functions as an external storage medium for the host 24. Examples of the host 24 include a personal computer and a CPU (Central Processing Unit) core.

  The semiconductor memory unit 23 is configured by a nonvolatile semiconductor memory such as a NAND flash memory, for example, but may be a memory other than the NAND flash memory.

  The memory controller 22 includes an internal bus 30, a host I / F (interface) 31, a memory I / F (memory interface) 32, a control unit 33, an encoding / decoding processing unit 34, and a RAM (Random Access Memory). 37). The encoding / decoding processing unit 34 includes an encoding unit (encoding device) 35 and a decoding unit (decoding device) 36.

  The Host I / F 31 outputs the command, data, etc. received from the host 24 to the internal bus 30. The Host I / F 31 transmits data input via the internal bus 30, a response notification from the control unit 33 (such as a notification indicating the completion of execution of the command), and the like to the host 24.

  The control unit 33 is a control unit that comprehensively controls each component of the semiconductor memory device 21, and includes a CPU core, a RAM, a ROM (Read Only Memory), a DMA (Direct Memory Access) controller, and the like. When receiving a command from the host 24 via the Host I / F 31 and the internal bus 30, the control unit 33 performs control according to the command. For example, the control unit 33 instructs the memory I / F 32 to write data to the semiconductor memory unit 23 and read data from the semiconductor memory unit 23 in accordance with an instruction from the host 4. The control unit 33 also controls the encoding unit 35 to perform encoding processing on the write data when writing to the semiconductor memory unit 23, and based on the code word read from the semiconductor memory unit 23. The decryption unit 36 is controlled to perform the decryption process. The RAM 37 temporarily holds data received from the host and data to be transmitted to the host.

  In the present embodiment, data received from the host 24 is encoded and written to the semiconductor memory unit 23, and the encoding target data is NB + 1 data blocks as shown in FIG. 2 of the first embodiment. Assume that it is configured. The decoding unit 36 performs the decoding process on the assumption that the data blocks are input in the input order determined in advance in units of data to be encoded.

  Data received from the host 24 is temporarily stored in the RAM 37. The control unit 33 manages the correspondence between the logical address and the address on the semiconductor memory unit 23 for data received from the host 24 (hereinafter referred to as host data), and the host data constitutes the encoding target data. To decide. In addition, the control unit 33 stores the identification number of the data block in the data to be encoded (for example, the data block number of the data block #i (i = 1, 2,..., NB) is i) in the RAM 37. I manage what was done. The control unit 33 controls the encoding unit 35 according to the data block number stored in the RAM 37.

  Even when the decoding process is performed in a predetermined data block input order, if the encoding apparatus described in the first embodiment is used as the encoding unit 35, the data block input order can be freely set. it can. For example, the encoding device shown in FIG. 1 processes data blocks in an arbitrary order, holds the adjusted parity of each data block, and stores NB + 1 position-adjusted parity for the encoding target data. The final parity can be generated by taking the exclusive OR of the parity at the time when can be generated. On the other hand, in the first embodiment, the bit position where the information of the encoding target data exists can be changed without being fixed. However, as shown in FIG. In such a case, it is possible to increase the processing speed by providing a position adjustment circuit corresponding to each data block. In this embodiment, an example in which a position adjustment circuit is provided for each data block will be described.

  FIG. 9 is a diagram illustrating a configuration example of the encoding unit 35 of the present embodiment. As shown in FIG. 9, the encoding unit 35 according to the present embodiment includes a selector 41, an ECC encoding circuit 1, position adjustment circuits 2-1 to 2-L (L = NB + 1), an adder 43, . The ECC encoding circuit 1 is the same as the ECC encoding circuit 1 of the first embodiment. The position adjustment circuits 2-1 to 2-L are the same as the first position adjustment circuit 2, respectively, but the number of bits for inputting 0 may not be changeable, and a fixed number of 0s are input. Also good. In the configuration example of FIG. 9, L = NB + 2, and the position adjustment circuit 2-1 corresponds to the data block # 0, the position adjustment circuit 2-2 corresponds to the data block # 1,. -L corresponds to data block # (LB + 1). Therefore, for example, the position adjustment circuit 2-1 only needs to be able to adjust the bit position corresponding to the data block # 0, and the position adjustment circuit 2-2 should adjust the bit position corresponding to the data block # 1. If you can.

  Next, the encoding process of this Embodiment is demonstrated. FIG. 10 is a diagram illustrating an example of an encoding process procedure according to the present embodiment. FIG. 10 shows processing for generating parity of one piece of encoding target data. First, when receiving a write request from the host 24 via the Host I / F 31, the control unit 33 assigns an address of data constituting the encoding target data based on the address of the host data to be written.

  For example, when transmission from the host is performed in a predetermined first data unit, the predetermined data unit is further composed of a plurality of second data units, and actual data transfer is performed in the second data unit. And Then, transfer of data from the host 24 is managed for each first data unit, and arrives at the RAM 37 in the order of transmission from the host 24 between the first data units. It is assumed that the arrival order at the RAM 37 is not guaranteed to be the transmission order between the data units. For example, host data in three first data units, host data # 1, host data # 2, and host data # 3, are transmitted from host 24 in the order of host data # 1, host data # 2, and host data # 3. In this case, it is assumed that the arrival order to the RAM 37 is host data # 1, host data # 2, and host data # 3. On the other hand, for example, host data # 1 is composed of five second data units, host data # 1-1 to host data # 1-5, and the host data # 1-1 and host data # 1- 2,..., And host data # 1-5 are transmitted in the order, host data # 1-3 can be changed in arrival order so that it arrives before host data # 1-1.

  Here, it is assumed that there is no change in the arrival order in the first data unit, but a plurality of first data units are stored in the RAM 37 even when there is a change in the arrival order in the first data unit. If there is enough capacity, the same encoding process can be performed.

  Here, for the sake of simplicity, the first data unit is the encoding target data in FIG. 2, and the second data unit is the data block in FIG. The first data unit and the encoding target data may be different. For example, the encoding target data may be configured by a plurality of first data units. For example, when the encoding target data is composed of two first data units, and the first data unit is composed of five second data units (= data block), the encoding target data is 10 It consists of data blocks. The operation in this case is the same as that in the case where one first data unit constitutes encoding target data, except that the number of data blocks is different. Further, although the management of the arrival of the data block is complicated, the second data unit and the data block may be different.

  Returning to the description of FIG. When the control unit 33 recognizes that the data block (= first data unit) has been received (the data block is stored in the RAM 37) (step S1), the control unit 33 grasps the data block number of the data block. The data block number may be notified to the control unit 33 with reference to identification information (data address or the like) for identifying the data block number stored in the host data by the Host I / F 31, or the control unit 33 May directly extract the identification information of the host data and grasp the data block number.

  The control unit 33 selects a data block to be encoded based on the received data block number, transmits a data block selection signal to the encoding unit 35, and instructs the start of the encoding process. Encoding processing by the encoding circuit 1 is performed (step S3). At this time, the selector 41 selects a data block to be input based on a selection signal from the control unit 33 and inputs the data block to the ECC encoding circuit 1, and the selector 42 generates a parity (intermediate) generated by the ECC encoding circuit 1. The result is output to the position adjustment circuit (any one of the position adjustment circuits 2-1 to 2-L) selected based on the selection signal. Hereinafter, the parity that is an intermediate result corresponding to the data block #i is referred to as parity #i ′.

  The position adjustment circuit 2-i to which the parity #i ′ is input performs the position adjustment described in the first embodiment on the basis of the position in the data to be encoded of the data block #i and performs the parity #i. Is generated (step S4). Thereafter, the control unit 33 determines whether or not all data blocks in the encoding target data have been processed (parity has been generated) (step S5), and if not (step S5 No), step Return to S2.

When all the data blocks in the encoding target data have been processed (Yes in step S5),
The adder 43 calculates the exclusive OR of the parities # 0 to #L as the parity P of the encoding target data (step S6), and ends the process.

  The parity P is written into the semiconductor memory unit 23 together with the data to be encoded. At the time of reading from the semiconductor memory unit 23, the data to be encoded and the parity P are read, decoded by the decoding unit 36, and the decoded data is transmitted to the host 24.

  Here, the parity P is obtained after all the data blocks of the encoding target data are gathered. However, if it is known that only some data blocks of the encoding target data arrive, The parity P may be obtained by calculating the exclusive OR of the parity after the position adjustment for the data block of the part. Also, for example, if all the data blocks of the data to be encoded are not complete even after a predetermined time has elapsed since the last data block to be encoded was received, the unreceived data block was lost on the way Therefore, the parity P may be obtained using the received data block.

  A configuration example of the position adjustment circuits 2-1 to 2-L will be described. Here, as an example, an example in which the size of a data block is 1 bit, NB = 3 (the number of data blocks constituting one encoding target data is 4), and L = 4 is provided with four position adjustment circuits. To do. The parity is 3 bits, and the values of the bits of the parity (intermediate result) generated by the ECC encoding generation circuit 1 are r [0], r [1], and r [2], respectively.

  11 to 14 are diagrams illustrating configuration examples of the position adjustment circuits 2-1 to 2-4. 11 shows a configuration example of the position adjustment circuit 2-1, FIG. 12 shows a configuration example of the position adjustment circuit 2-2, FIG. 13 shows a configuration example of the position adjustment circuit 2-3, and FIG. These show a configuration example of the position adjustment circuit 2-4. FIG. 15 is a diagram illustrating an example of an intermediate result (parity #i ′) input and a parity #i output when the configurations of FIGS. 11 to 14 are assumed.

When the encoding target data is (d3 d2 d3 d0), each data block performs position adjustment by inputting 0 as follows.
(1) Data block # 0 (d0)
(2) Data block # 1 (d1 0)
(3) Data block # 2 (d2 0 0)
(4) Data block # 3 (d3 0 0 0)

  Since the position adjustment circuit 2-1 corresponding to the data block # 0 does not need to input 0 as shown in FIG. 11, it outputs r [0], r [1], r [2] as it is. . As shown in FIG. 12, the position adjustment circuit 2-2 corresponding to the data block # 1 includes an XOR gate 5. The position adjustment circuit 2-2 outputs r [2] as output bit # 0 (corresponding to the output of r [0] when position adjustment is not performed) as a process of inputting one 0, and outputs bit # 0. 1 (corresponding to the output of r [1] when position adjustment is not performed) r [0] ^ r [2] is output and output bit # 2 (output of r [2] when position adjustment is not performed) R [0] is output as a response. Note that ^ indicates an exclusive OR operation.

  As shown in FIG. 13, the position adjustment circuit 2-3 corresponding to the data block # 2 includes XOR gates 5-1 and 5-2. Position adjustment circuit 2-3 outputs r [1] as output bit # 0, outputs r [2] ^ r [1] as output bit # 1, and outputs two bits as a process of inputting two 0s. # 2r [1] is output.

  As shown in FIG. 14, the position adjustment circuit 2-4 corresponding to the data block # 3 includes XOR gates 5-1, 5-2, and 5-3. The position adjustment circuit 2-4 outputs r [0] ^ r [2] as output bit # 0 and r [0] ^ r [2] ^ as output bit # 1 as a process of inputting three zeros. r [1] is output, and r [2] ^ r [1] is output as output bit # 2.

  FIG. 16 is a diagram illustrating an example of input information and 0 input. FIG. 17 is a diagram illustrating specific examples of the intermediate result (parity #i ′) and the position-adjusted parity (parity #i) when the information in FIG. 16 is input. If the information is 1101 (d3 = 1: d2 = 1: d1 = 0: d0 = 1) as shown in the right column of FIG. 16, 0 is input according to the data block as shown in the left column of FIG. To do.

  As shown in FIG. 17, for the data block # 0, the parity # (Parity) 0 ′ generated by the ECC encoding circuit 1 is {r [2], r [1], r [0]} = { 0,1,1}. For the data block # 1, the parity # 1 ′ generated by the ECC encoding circuit 1 is {r [2], r [1], r [0]} = {0, 1, 1}. For the data block # 2, the parity # 2 ′ generated by the ECC encoding circuit 1 is {r [2], r [1], r [0]} = {0, 0, 0}. For the data block # 3, the parity # 3 ′ generated by the ECC encoding circuit 1 is {r [2], r [1], r [0]} = {0, 1, 1}.

  Further, by the processing described with reference to FIG. 15, parity # 0 becomes {1, 0, 0}, parity # 1 becomes {1, 1, 1}, and parity # 2 becomes {0, 0, 0}. Parity # 3 is {0, 1, 1}. The finally obtained parity P is {0, 0, 1}. Therefore, the parity P for the information 1101 is 001, and the code word is 1101001.

  Here, an example in which each data block size is the same has been described, but the data size of each data block may be different.

  As described above, in this embodiment, the position adjustment circuit is provided for each data block, and the position adjustment processing can be performed in parallel. For this reason, it is possible to arbitrarily set the position to start encoding in the data to be encoded in units of data blocks, and to simplify the configuration of the position adjustment circuit. Further, even when the arrival order of the data blocks is different from the predetermined order, the encoding process can be performed in the arrival order, so that the buffer amount can be reduced and the processing speed can be improved.

(Third embodiment)
FIG. 18 is a diagram illustrating a configuration example of the encoding unit 35a according to the third embodiment. The encoding unit 35a of the present embodiment is used in place of the encoding unit 35a in the storage device 21 described in the second embodiment. Constituent elements having the same functions as those of the second embodiment are denoted by the same reference numerals as those of the second embodiment, and redundant description is omitted.

  The encoding unit 35a deletes the selectors 41 and 42 from the encoding 25 of the second embodiment, and includes the ECC encoding circuits 1-1 to 1-L instead of the ECC encoding circuit 1. This is the same as the encoding unit 35 of the embodiment. In the second embodiment, the ECC encoding circuit 1 is shared by each data block. However, in this embodiment, the same number of ECC encoding circuits 1-1 to 1-L as the data blocks are provided, and the data block The encoding process is performed by a different ECC encoding circuit for each. Thereby, the encoding process can be performed in parallel, and the processing speed can be improved as compared with the second embodiment. As described above, the operation of this embodiment is the same as that of the second embodiment.

  For example, when the data size of each data block is the same, the encoding processing time is 1 / L of the encoding device of the comparative example. As described above, according to the present embodiment, the same effects as those of the second embodiment can be obtained, the encoding processing can be parallelized, and the encoding processing speed can be improved.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1, 1-1 to 1-L ECC encoding circuit, 2, 2-1 to 2-L position adjustment circuit, 3,33 control unit, storage device 21, semiconductor memory unit 23, 34 encoding / decoding unit, 35 encoding unit, 36 decoding unit, 41, 42 selector, 43 adder.

Claims (11)

An encoding device that encodes encoding target data composed of L (L is an integer of 2 or more) data blocks,
An encoding circuit for performing an encoding process on the data block;
L position adjustment circuits that generate parity according to the position of the data block in the data to be encoded for each data block based on the parity generated by the encoding process;
An encoding device comprising:   The encoding apparatus according to claim 1, wherein the position adjustment circuit performs a process of inputting 0 to a bit position other than the corresponding data block in the encoding target data.   The encoding apparatus according to claim 1, wherein the position adjustment circuit performs a process of inputting 0 to a bit position lower than a bit position of the corresponding data block in the encoding target data. .   The encoding apparatus according to claim 1, wherein the encoding circuit is provided for each data block, and the encoding processing for each data block is performed in parallel. An encoding device for encoding data to be encoded,
An encoding circuit that performs an encoding process on data having a specified length from a specified position in the encoding target data;
A position adjustment circuit that generates parity according to the position of the data in the encoding target data based on the parity generated by the encoding process;
An encoding device comprising:   6. The encoding apparatus according to claim 1, wherein the code is an error correction code or an error detection code.   6. The encoding apparatus according to claim 5, wherein the code is a BCH code.   The encoding apparatus according to claim 5, wherein the code is a Reed-Solomon code.   6. The encoding apparatus according to claim 5, wherein the code is a CRC. A memory section;
An encoding unit that generates a codeword by performing an encoding process using data of a predetermined data length stored in the memory unit as encoding target data;
A decoding unit that performs a decoding process based on a codeword read from the memory unit;
With
The encoding unit includes:
An encoding circuit that performs an encoding process on L (L is an integer of 2 or more) data blocks constituting the encoding target data;
L position adjustment circuits that generate parity according to the position of the data block in the data to be encoded for each data block based on the parity generated by the encoding process;
A storage device comprising: An encoding method in an encoding device that encodes encoding target data composed of L (L is an integer of 2 or more) data blocks,
Performing an encoding process on the data block;
Based on the parity generated by the encoding process, a step of generating a parity according to the position of the data block in the encoding target data for each data block by L position adjustment circuits;
The encoding method characterized by including.

Images