JP2013201215A - Nonvolatile semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of diffusing an impurity of a desired concentration into a desired region with good controllability.SOLUTION: According to an embodiment, there is provided a nonvolatile semiconductor memory device in which a memory cell array layer CA11 in which a memory cell is formed on a semiconductor layer 11 serving as an active region and a memory cell array layer CA12 in which a memory cell is formed on a semiconductor layer 21 serving as the active region are laminated. The semiconductor layer 11 is disposed on a diffusion source layer 101 including an impurity atom which imparts conductivity to the semiconductor layer 11 via an insulating film 102. The semiconductor layer 21 is disposed on one principal surface of a diffusion source layer 112 including an impurity atom via an insulating film 111.

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.

  A memory cell transistor of a conventional NAND flash memory device has a stack gate structure in which a charge storage layer, an inter-gate insulating film, and a control gate electrode are stacked on an active region via a tunnel insulating film. In recent years, the cell size has reached the physical limit as a result of the rapid miniaturization of the element size in order to reduce the cost by improving the bit density. Therefore, a stacked NAND flash memory device in which memory cells are three-dimensionally stacked is attracting attention as means for achieving a higher bit density.

  In a stacked NAND flash memory device, an insulating film containing impurities of a predetermined conductivity type is embedded between stacked bodies in which a stacked body of a semiconductor film and an interlayer insulating film is processed into a fin shape, and heat treatment is performed. A method for solid-phase diffusion of impurities in a semiconductor film of a fin-like laminate has been proposed.

  However, in the manufacturing method of the stacked NAND flash memory device, the diffusion of impurities proceeds even in a subsequent thermal process, and a technique for controlling the diffusion of a desired concentration of impurities in a desired region is a technique. It was not proposed. In addition, some stacked NAND flash memory devices have a structure in which a unit structure (for example, a memory cell array layer) is repeatedly stacked in the height direction. In such a case, after the solid phase diffusion is performed on the first layer semiconductor film by the above method, the second layer and subsequent semiconductor films are also solid phase diffused by the above method. In the case where an insulating film containing impurities is formed, a method for controlling the concentration of impurities diffused into each semiconductor film in the subsequent thermal process has not been proposed.

JP 2011-114235 A

  An object of one embodiment of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, which can diffuse impurities having a desired concentration into a desired region in a controlled manner.

  According to one embodiment of the present invention, a first memory layer in which a memory cell is formed on a first semiconductor layer that is an active region and a memory cell that is formed on a second semiconductor layer that is an active region. A nonvolatile semiconductor memory device in which two memory layers are stacked is provided. The main surface of the first semiconductor layer on the second memory layer arrangement side is provided on the first diffusion source layer containing impurity atoms via the first insulating film. The main surface of the second semiconductor layer on the first memory layer arrangement side is arranged on the second diffusion source layer containing the impurity atoms via a second insulating film.

FIG. 1 is a perspective view schematically showing an example of the structure of a nonvolatile semiconductor memory device used in the embodiment. FIG. 2 is a cross-sectional view along the extending direction of the active region of FIG. FIG. 3 is a cross-sectional view in a direction perpendicular to the extending direction of the active region. FIG. 4 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device. FIG. 5 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 6A is a cross-sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment (No. 1). FIG. 6B is a cross-sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment (No. 2). FIG. 6C is a cross-sectional view schematically showing one example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment (No. 3). 6-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 4). 6-5 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 5). 6-6 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 6). 6-7 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 7). FIGS. 6-8 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 8). FIG. 6-9 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment (No. 9). 6-10 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 10). FIGS. 6-11 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 11). FIG. 6-12 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment (No. 12). FIG. 6-13 is a sectional view schematically showing an example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment (No. 13). FIG. 7 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the second embodiment. FIG. 8 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the third embodiment.

  Exemplary embodiments of a nonvolatile semiconductor memory device and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. In addition, the cross-sectional views of the nonvolatile semiconductor memory devices used in the following embodiments are schematic, and the relationship between layer thickness and width, the ratio of the thickness of each layer, and the like may differ from the actual ones. . Furthermore, in the following, after describing the structure of the nonvolatile semiconductor memory device used in the embodiment, each embodiment will be described.

  FIG. 1 is a perspective view schematically showing an example of the structure of a nonvolatile semiconductor memory device used in the embodiment, and FIG. 2 is a cross-sectional view along the extending direction of the active region in FIG. 3 is a cross-sectional view in a direction perpendicular to the extending direction of the active region, (a) is a cross-sectional view along AA in FIG. 2, and (b) is a cross-sectional view along BB in FIG. (C) is CC sectional drawing of FIG. In the following description, the extending direction of the active region is the X direction, the height direction is the Z direction, and the direction perpendicular to the X direction and the Z direction is the Y direction.

  In the nonvolatile semiconductor memory device, sheet-like semiconductor layers 11 and 21 serving as bodies extend vertically in the X direction on the insulating film 30 serving as a base, form a channel, and a tunnel insulating film therebetween. The charge storage layer 13 disposed on the upper surface of the semiconductor layer 11 via 12 and the charge storage layer 23 disposed on the lower surface of the semiconductor layer 21 via the tunnel insulating film 22 are arranged vertically via the interlayer insulating film 31. Are stacked. These semiconductor layers 11, 21, tunnel insulating films 12, 22 and charge storage layers 13, 23 are formed via embedded insulating films 15, 25 extending in the X direction as shown in FIG. Insulated and separated from each other in the direction.

  A plurality of stacked structures of the charge storage layers 13 and 23 are formed at predetermined intervals in the X direction of the semiconductor layers 11 and 21 so as to form a NAND array. Control gates 33 extending in the Y direction via inter-gate insulating films 32 are formed on both sides in the X direction of the stacked structures of the charge storage layers 13 and 23. The control gate 33 is provided in common to the charge storage layers 13 and 23 so as to be coupled to the upper and lower charge storage layers 13 and 23 from the side. A mask film 33 m is provided between the control gate 33 and the tunnel insulating film 22. A pair of control gates 33 provided on both sides in the X direction of the lower semiconductor layer 11, the tunnel insulating film 12, the charge storage layer 13, the inter-gate insulating film 32, and the charge storage layer 13 are connected to the lower memory cell MC1. Included in the configuration. In addition, a pair of control gates 33 provided on both sides in the X direction of the upper semiconductor layer 21, the tunnel insulating film 22, the charge storage layer 23, the inter-gate insulating film 32, and the charge storage layer 23 form the configuration of the upper memory cell MC2. included.

  Select gate transistors ST11, ST12, ST21, and ST21 are arranged at positions adjacent to the control gates 33 at both ends of the stacked structure body of charge storage layers 13 and 23 arranged in the X direction via dummy memory cells DM1 and DM2. Select gates 16 and 26 forming ST22 are arranged. The selection gate 16 is disposed on the upper surface of the semiconductor layer 11 via the tunnel insulating film 12, and the selection gate 26 is disposed on the lower surface of the semiconductor layer 21 via the tunnel insulating film 22. The select gates 16 and 26 are stacked vertically with an interlayer insulating film 31 interposed therebetween. A selection gate line 17 extending in the Y direction is embedded in the selection gate 16 so as to penetrate the buried insulating film 15 disposed between the selection gates 16 adjacent in the Y direction, and the selection gate 26 is embedded in the Y direction. A selection gate line 27 and a mask film 27m extending in the Y direction are embedded so as to penetrate the buried insulating film 25 disposed between the adjacent selection gate lines 17. These select gate lines 17 and 27 are insulated from each other through an interlayer insulating film 34.

  As described above, the NAND string NS including the predetermined number of memory cells MC1 connected in series on the upper surface of the sheet-like semiconductor layer 11 extending in the X direction, and both ends of the NAND string NS in the X direction. NAND cell units NU11, NU12,... Having a pair of select gate transistors ST11, ST12 arranged via dummy memory cells DM1 are formed. .. Are arranged at a predetermined interval via the buried insulating film 15 in the Y direction, thereby forming the lower memory cell array layer CA11.

  Similarly, on the lower surface of the sheet-like semiconductor layer 21 extending in the X direction, a NAND string NS including a predetermined number of memory cells MC2 connected in series, and dummy strings at both ends of the NAND string NS in the X direction. NAND cell units NU21, NU22,... Having a pair of select gate transistors ST21, ST22 arranged via the memory cell DM2 are formed. Then, a plurality of NAND cell units NU21, NU22,... Are arranged at predetermined intervals in the Y direction via the buried insulating film 25, thereby forming the upper memory cell array layer CA21.

  The control gate 33 is shared between the memory cells MC arranged above and below via the interlayer insulating film 31, and the memory cell MC arranged adjacently via the buried insulating films 15 and 25 in the Y direction. The control gate 33 is shared between them.

  One end in the X direction of the semiconductor layers 11 and 21 of the NAND cell units NU11 and NU21 stacked up and down via the interlayer insulating films 31 and 34 extends vertically in common to these, and a bit (not shown) A bit line contact 35 connected to the line is formed. Similarly, at the other end in the X direction of the semiconductor layers 11 and 21 of the NAND cell units NU11 and NU21, there is formed a source line contact 36 extending vertically in common to them and connected to a source line (not shown). Has been. Note that the bit line contact 35 and the source line contact 36 are provided in the same manner in other NAND cell unit groups arranged above and below via the interlayer insulating films 31 and 34. Further, the control gate 33 and the selection gate lines 17 and 27 are formed to extend in the Y direction from the region where the memory cell array layers CA11 and CA12 are formed, and at one end thereof, a word line contact 37 and A selection gate line contact 38 is connected. Here, the upper selection gate line 27 and the lower selection gate line 17 have a structure in which they are stacked one above the other through the interlayer insulating film 34, so that the lower selection gate line 17 is exposed. It has a stepped structure.

  A combination of the upper and lower memory cell array layers CA11 and CA12 stacked via the interlayer insulating film 31 is hereinafter referred to as a memory cell array group CAG.

  Here, the material of the semiconductor layers 11 and 21 can be selected from, for example, Si, Ge, SiGe, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or InGaAsP. The semiconductor films 11 and 21 may be made of a single crystal semiconductor or a polycrystalline semiconductor.

As the tunnel insulating films 12 and 22, a silicon oxide film or the like can be used. As the charge storage layers 13 and 23, an amorphous silicon film doped with an impurity such as P or B, a polycrystalline silicon film, or a silicon oxide film / silicon nitride A film / silicon oxide film stack film (ONO film), a high-k film such as Al ₂ O ₃ or HfO, a silicon nitride film, or the like can be used. Further, a silicon oxide film or the like can be used as the inter-gate insulating film 32, and W, TaN, WN, TiAlN, TiN, WSi, CoSi can be used as the control gate 33, the selection gates 16, 26, and the selection gate lines 17, 27. , NiSi, PrSi, NiPtSi, PtSi, Pt, Ru, or the like, RuO ₂ , B-doped polycrystalline silicon film, P-doped polycrystalline silicon film, or a laminated film thereof can be used.

  In the nonvolatile semiconductor memory device having such a configuration, the charge storage layers 13 and 23 of the memory cells MC1 and MC2 corresponding to the upper and lower NAND cell units NU1 and NU2 are connected to the control gates 33 (word lines) on both sides. They are simultaneously driven by coupling and connected to a common bit line. On the other hand, the selection gate transistors ST11, ST12, ST21, and ST22 are provided independently for the upper and lower bit lines, and one of the selection gate transistors ST11, ST12, ST21, and ST22 is selected to select the NAND cell units NU1 and NU2. Can be activated actively.

  FIG. 4 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device. This figure shows a cross section at a position along the extending direction of the active region shown in FIG. This nonvolatile semiconductor memory device has a structure in which three memory cell array groups CAG described with reference to FIGS. 1 to 3 are stacked in the Z direction via interlayer insulating films 51 and 52. That is, the memory cell array group CAG2 including the memory cell array layers CA21 and CA22 is formed on the memory cell array group CAG1 including the memory cell array layers CA11 and CA12 via the interlayer insulating film 51, and the interlayer insulating film is formed on the memory cell array group CAG2. A memory cell array group CAG3 including memory cell array layers CA31 and CA32 is formed via 52. However, in this example, the upper memory cell array group is arranged such that the formation positions of the bit line contact and the source line contact are located inside. In this example, the case where three memory cell array groups CAG are stacked is illustrated, but the number of stacked layers is not limited to this.

  Thus, by stacking a plurality of memory cell array groups CAG1 to CAG3, it is possible to increase the storage density of the nonvolatile semiconductor memory device. In FIG. 4, STI (Shallow Trench Isolation) is formed on a semiconductor substrate such as a silicon substrate by forming an SOI structure using a semiconductor layer containing polysilicon in the channel (body) of the lowermost memory cell array layer CA11. However, the semiconductor layer serving as the channel of the lowermost memory cell array layer CA11 may be a semiconductor substrate.

(First embodiment)
FIG. 5 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the first embodiment. This nonvolatile semiconductor memory device has a stacked structure of the insulating film 30 and interlayer insulating films 51 and 52 provided between the memory cell array groups CAG1 to CAG3 in the nonvolatile semiconductor memory device of FIG. Specifically, the interlayer insulating film in contact with the semiconductor layer that becomes the active region constituting each of the memory cell array groups CAG1 to CAG3 is a diffusion source layer using an insulating film containing an impurity of a predetermined conductivity type diffused in the semiconductor layer ( An impurity-containing insulating layer) and a laminated film of an insulating film provided between the diffusion source layer and the semiconductor layer. Although it is desirable that the insulating film does not contain impurities, it is sufficient that the impurity concentration is lower than that of the diffusion source layer.

  For example, the interlayer insulating film provided below the semiconductor layer 11 of the memory cell array layer CA11 of the memory cell array group CAG1 includes a diffusion source layer 101 containing impurities and an insulating film 102 provided between the diffusion source layer 101 and the semiconductor layer 11. And a laminated film. Between the memory cell array groups CAG1 and CAG2, an interlayer insulating film having a structure in which an insulating film 111, a diffusion source layer 112, and an insulating film 113 are sequentially stacked is provided on the semiconductor layer 21 of the memory cell array layer CA12. On the film 113, the semiconductor layer 201 of the memory cell array layer CA21 is formed. Further, between the memory cell array groups CAG2 and CAG3, an interlayer insulating film having a structure in which an insulating film 121, a diffusion source layer 122, and an insulating film 123 are sequentially stacked is provided on the semiconductor layer 202 of the memory cell array layer CA22. On the film 123, the semiconductor layer 203 of the memory cell array layer CA31 is formed.

  The concentration of impurities of a predetermined conductivity type included in the diffusion source layers 101, 112, and 122 and the thicknesses of the insulating films 102, 111, 113, 121, and 123 are as follows. The semiconductor layer 11, 21, 201, 202, 203 in contact with each of the insulating films 102, 111, 113, 121, 123 is appropriately adjusted by the heat applied in the step so that impurities having a desired concentration are diffused. The In general, the upper memory cell array layer CA has less time to receive heat than the lower memory cell array layer CA, and therefore, the distance at which impurities are diffused from the diffusion source layer is shortened. Conversely, the lower the memory cell array layer CA, the longer it takes time to receive heat, and thus the longer the distance at which impurities diffuse from the diffusion source layer. Therefore, the diffusion of impurities from the lower diffusion source layer to the semiconductor layer is suppressed by reducing the thickness of the insulating film or increasing the impurity concentration contained in the diffusion source layer as it goes to the upper layer. It is desirable to promote diffusion of impurities from the diffusion source layer to the semiconductor layer. The insulating films 102, 111, 113, 121, and 123 have a function of controlling the diffusion of impurity atoms from the diffusion source layers 101, 112, and 122 to the semiconductor layers 11, 21, 201, 202, and 203.

  Here, as the diffusion source layers 101, 112, and 122, an insulating material such as BSG (Boron doped Silicate Glass), BPSG (Boron Phosphorus doped Silicate Glass), or PSG (Phosphorus doped Silicate Glass) can be used. As the insulating films 102, 111, 113, 121, and 123, an oxide film such as a silicon oxide film or a nitride film such as a silicon nitride film can be used. In the case of an oxide film, the depth at which impurities are diffused and the concentration of impurities in the depth direction can be controlled by controlling the thickness on the order of 1 nm. In the case of a nitride film, the insulating films 102, 111, 113, 121, and 123 are thinned so that impurities in the diffusion source layers 101, 112, and 122 are converted into semiconductor layers 11, 201, 201, 202, and 203. It can be used when diffusing.

  Next, a method for manufacturing the nonvolatile semiconductor memory device having such a structure will be described. 6A to 6C are cross-sectional views schematically showing an example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

First, as shown in FIG. 6A, a peripheral circuit (not shown) for driving the nonvolatile semiconductor memory device is formed on a semiconductor substrate (not shown) such as a silicon substrate. Next, a diffusion source layer 101 using, for example, BSG, BPSG, or PSG and an insulating film 102 using, for example, SiO ₂ are formed in order on the semiconductor substrate on which the peripheral circuit is formed, and a channel is formed thereon. A semiconductor layer 11 using polysilicon, a tunnel insulating film 12 using SiO _2, and a charge storage layer forming layer 13A using polysilicon are sequentially stacked. Since the tunnel insulating film 12 is formed on the semiconductor layer 11 using polysilicon, it can be formed not by a thermal oxide film but by a CVD (Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method. . In this example, the semiconductor layer 11 is formed by film formation, but a semiconductor substrate may be used as it is.

  Next, a not-shown trench extending in the X direction for forming an AA (active area) pattern in the semiconductor layer 11 is predetermined in the Y direction by using a lithography technique and an etching technique such as RIE (Reactive Ion Etching). Are formed in a laminate from the diffusion source layer 101 to the charge storage layer forming layer 13A. As a result, a stacked body including the line-and-space charge storage layer forming layer 13A, the tunnel insulating film 12, the semiconductor layer 11, the insulating film 102, and the diffusion source layer 101 is formed.

Next, the trench formed by AA pattern processing is filled with a buried insulating film (not shown) using SiO _2, and planarized by CMP (Chemical Mechanical Polishing) method using polysilicon forming the charge storage layer forming layer 13A as a stopper. And the upper surface of the buried insulating film is retreated by etch back.

Thereafter, an interlayer insulating film 31 for separating the upper and lower memory cell array layers is formed on the buried insulating film and the charge storage layer forming layer 13A, and a charge storage layer forming layer 23A using polysilicon is formed thereon. To do. Subsequently, mask films 43 and 44 made of different materials are formed on the charge storage layer forming layer 23A. For example, SiN can be used as the mask film 43, and SiO ₂ can be used as the mask film 44.

  Thereafter, using lithography technology and etching technology, the patterns 43a and 44a are formed so that the formation position of the control gate is opened in the area where the memory cell is formed, and the formation position of the selection gate is formed in the area where the selection gate is formed. Patterns 43b and 44b are formed so as to be covered. The patterns 43a, 43b, 44a, and 44b have shapes extending in the Y direction.

  Next, as shown in FIG. 6B, the stacked body from the charge storage layer formation layer 23A to the charge storage layer formation layer 13A is formed on the tunnel insulating film 12 by the RIE method using the mask films 43 and 44 as a mask. Etching is selectively performed until a control gate forming groove 55 is formed. As a result, the charge storage layer forming layer 13A becomes the charge storage layer 13 in the memory cell formation region, and becomes the selection gate formation layer 16A in the selection gate formation region. The charge storage layer formation layer 23A becomes the charge storage layer formation layer 23B in the memory cell formation region and the selection gate formation layer 26A in the selection gate formation region. In this etching, it is desirable to perform etching under a condition having a high selectivity with the lower tunnel insulating film 12 so that the lower semiconductor layer 11 is not etched.

Subsequently, as shown in FIG. 6-3, the intergate insulating film 32 using SiO ₂ is formed conformally on the stacked body in which the control gate forming groove 55 is formed, and then the control gate forming groove is formed. A control gate formation layer 33 A is embedded in 55. Polysilicon or metal (W or the like) can be used for the control gate formation layer 33A. Further, the control gate formation layer 33A is formed to be higher than the upper surface of the remaining mask film 43.

  Next, as shown in FIG. 6-4, the control gate 33 is formed by performing etch back on the control gate formation layer 33A using the RIE method. Here, the etch back is performed so that the upper surface of the control gate 33 is slightly lower than the upper surface of the charge storage layer forming layer 23B.

  Thereafter, as shown in FIG. 6-5, the mask film 33m using the CVD oxide film or the coating oxide film and the insulating film 39 are embedded in the etched back region, and the mask film 43 is used as a stopper by the CMP method. Flatten the top surface. Further, as shown in FIG. 6-6, the selection gate formation layers 16A and 26A have a selection gate formation layer 26B corresponding to an EI (Etching Inter Poly) trench, a selection gate reaching the interlayer insulating film 31 and the selection gate formation layer 16A. The line forming groove 17A is processed by an etching technique such as RIE. As a result, the selection gate formation layer 16 </ b> A becomes the selection gate 16. At this time, processing for forming a transistor of a row decoder portion (not shown) may be performed simultaneously.

  Next, as shown in FIG. 6-7, after the selection gate line 17 is formed so as to be embedded in the selection gate line formation groove 17A, the upper surface of the selection gate line 17 is formed on the interlayer insulating film 31 by a method such as RIE. Etch back so as not to be higher than the upper surface of the substrate. Subsequently, the interlayer insulating film 34 is formed so as to be embedded in the select gate line forming groove 17A, and then etched back by a method such as RIE. For example, the etch back can be performed so that the thickness of the interlayer insulating film 34 is substantially the same as the thickness of the interlayer insulating film 31. Further, the selection gate line 27 is buried in the selection gate line forming groove 17A, and etched back by a method such as RIE so as to be almost the same height as the upper surface of the selection gate formation layer 26A. At this time, polysilicon or metal (W or the like) can be used as the selection gate lines 17 and 27 as in the case of the control gate 33. Then, a mask film 27m and a cap insulating film 39A are embedded in the etched back portion of the select gate line forming groove 17A above the select gate line 27, and the upper surface thereof is a CMP method using the mask film 43 as a stopper. Is flattened.

Thereafter, as shown in FIGS. 6-8, planarization is performed by CMP using the charge storage layer formation layer 23B or the control gate 33 as a stopper, and a tunnel insulating film 22A using SiO ₂ is formed thereon, thereby forming a channel. A semiconductor layer 21A using polysilicon is sequentially formed.

After that, as shown in FIG. 6-9, the insulating film 111 using SiO ₂ and the BSG or BPSG containing B with a predetermined concentration or the PSG or BPSG containing P with a predetermined concentration are formed on the semiconductor layer 21A. A diffusion source layer 112 using etc. and an insulating film 113 using SiO ₂ are sequentially laminated by a film forming method such as a CVD method.

Note that here, the insulating film 111, the diffusion source layer 112 containing impurities at a predetermined concentration, and the insulating film 113 are sequentially stacked. However, an insulating film containing no impurities (for example, a SiO ₂ film) For example, the insulating film 111, the diffusion source layer 112 and the insulating film 113 shown in FIG. An atom may be introduced.

  Thereafter, through holes are formed at both ends in the X direction of the NAND cell unit composed of the memory cell row and select gate transistors arranged at both ends in the X direction of the memory cell row to form contacts. As the contact material, general polysilicon or metal (W or the like) can be used. As a result, a memory cell array group CAG1 having two memory cell array layers CA11 and CA12 is formed.

Next, as shown in FIG. 6-10, a second-layer memory cell array group CAG2 having memory cell array layers CA21 and CA22 is formed on the insulating film 113. Here, a semiconductor layer 201 using polysilicon serving as a channel, a tunnel insulating film 212 using SiO _2, and a charge storage layer forming layer 213A using polysilicon are sequentially stacked. Thereafter, the charge storage layer forming layer 213A, the tunnel insulating film 212, the semiconductor layer 201, the insulating film 113, the diffusion source layer 112, the insulating film 111, the semiconductor layer 21A, the tunnel are formed by using a lithography technique and an etching technique such as the RIE method. Trenchs (not shown) extending in the X direction for forming AA patterns in the semiconductor layers 21A and 201 are formed at predetermined intervals in the Y direction with respect to the insulating film 22A, the charge storage layer forming layer 23B, and the selection gate forming layer 26A. To do. As a result, the charge storage layer forming layer 23B becomes the charge storage layer 23, and the first tunnel insulating film 22 and the semiconductor layer 21 are formed in a self-aligned manner with respect to the charge storage layer 23. The selection gate formation layer 26 </ b> A becomes the selection gate 26. Thereafter, a buried insulating film (not shown) is buried in the trench. As shown in FIG. 6-11, the second-layer memory cell array group CAG2 having the memory cell array layers CA21 and CA22 is formed by a method similar to the method shown in FIGS. The However, the semiconductor layer 201 serving as an active region of the memory cell array layer CA21 is formed on the insulating film 113.

After that, as shown in FIG. 6-12, the insulating film 121 using SiO ₂ and B having a predetermined concentration are included on the semiconductor layer 202 which becomes the active region of the memory cell array layer CA22 in the upper layer of the memory cell array group CAG2. A diffusion source layer 122 using BSG or BPSG, or PSG or BPSG containing P at a predetermined concentration, and an insulating film 123 using SiO ₂ are sequentially stacked.

  Next, through holes are formed at both ends in the X direction of the NAND cell unit composed of the memory cell row and select gate transistors arranged at both ends in the X direction of the memory cell row to form contacts. As a material of the contacts 35 to 38, general polysilicon or metal (W or the like) can be used.

Thereafter, as shown in FIG. 6-13, a third-layer memory cell array group CAG3 having memory cell array layers CA31 and CA32 is formed on the insulating film 123. The method of forming the memory cell array group CAG3 is the same as the method shown in FIGS. Although not shown, an insulating film using SiO ₂ , BSG or BPSG containing a predetermined concentration of B, or a predetermined concentration is formed on the semiconductor layer 204 of the upper memory cell array layer CA32 of the third memory cell array group CAG3. A diffusion source layer using PSG or BPSG containing P is formed. Then, through holes are formed at both ends in the X direction of the NAND cell unit including the memory cell row and select gate transistors arranged at both ends in the X direction of the memory cell row to form contacts. As described above, the nonvolatile semiconductor memory device is manufactured.

  Due to the heat applied in the above processing steps, the impurity atoms in the diffusion source layer 101 formed in FIG. 6-1, the impurity atoms in the diffusion source layer 112 formed in FIG. 6-9, and FIG. The impurity atoms in the diffusion source layer 122 formed in (1) pass through the insulating films 102, 111, 113, 121, 123 and diffuse into the semiconductor layers 11, 21, 201, 202, 203. Impurity atoms in the diffusion source layer (that is, the lower diffusion source layer) that have passed a longer distance are diffused, and impurity atoms in the diffusion source layer (that is, the upper diffusion source layer) that have not undergone the thermal process more The diffusion distance is shortened. Therefore, the amount of impurity atoms diffused from each diffusion source layer to each semiconductor layer between the formation of each diffusion source layer and the end of the manufacturing process of the nonvolatile semiconductor memory device is obtained in advance by measurement. The impurity concentration in the diffusion source layer or the thickness of the insulating film can be determined so that the final impurity concentration of the semiconductor layer becomes a desired value.

  In the first embodiment, a nonvolatile memory in which a plurality of memory cell array groups having a structure in which memory cell array layers are arranged so that charge storage layers face each other with an interlayer insulating film interposed therebetween are stacked in the height direction via the interlayer insulating film In the semiconductor memory device, a diffusion source layer containing an impurity of a predetermined conductivity type to be introduced into a semiconductor layer serving as an active region is disposed on the semiconductor layer via an insulating film. This has an effect that a semiconductor layer that becomes an active region whose impurity concentration is controlled to a desired concentration can be obtained.

  In addition, since the diffusion source layer containing impurities is arranged in the semiconductor layer serving as the active region through the insulating film, the impurities in the diffusion source layer are formed at a desired concentration by the heat received in the manufacturing process of the nonvolatile semiconductor memory device. It also has the effect of being able to diffuse into the layer. Furthermore, by controlling the thickness of the insulating film formed in the upper layer and the impurity concentration in the diffusion source layer, there is an effect that the impurity can be diffused into each semiconductor layer with good controllability.

  Further, in the method of introducing impurities into the semiconductor layer serving as the active region by ion implantation, for example, when introducing impurities into the semiconductor layer 21 below the interlayer insulating film 51 in FIG. It is difficult to introduce impurities, which may damage the tunnel insulating film 22 and affect the operation of the memory cell. However, in the method according to the above-described embodiment, impurities can be introduced into the semiconductor layer 21 without damaging the tunnel insulating film 22.

  Furthermore, when processing a semiconductor layer containing impurities, if there is a region in which more impurities are introduced than the surroundings in the semiconductor layer, the processing conditions are disturbed during etching such as the RIE method, resulting in excessive etching. . However, in the method according to the above-described embodiment, the semiconductor layer not containing impurities is formed, and the impurities are diffused from the diffusion source layer into the semiconductor layer in the subsequent thermal process. Can do.

(Second Embodiment)
FIG. 7 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the second embodiment. This nonvolatile semiconductor memory device is the same as the nonvolatile semiconductor memory device of the first embodiment, with the diffusion source layers 101, 112, 122 having a constant impurity concentration, and the insulating films 102, 111, 113, 121, 123 thickness. The thickness is getting thinner as you go up. With such a configuration, the impurity concentration of each of the semiconductor layers 11, 21, 201, 202, 203 serving as the active region is made uniform (constant).

  Since the manufacturing method of such a nonvolatile semiconductor memory device is the same as that described in the first embodiment, the description thereof is omitted. However, as described above, the impurity concentration of the diffusion source layers 101, 112, and 122 at any height is the same, and the thicknesses of the insulating films 102, 111, 113, 121, and 123 become thinner from the lower layer to the upper layer. Like to do. This is because the lower memory cell array layer is subjected to higher temperature or longer heat treatment, so that the lower insulating film is thicker so that even if diffusion by higher temperature or longer heat treatment is performed, insulation is performed. The impurity is prevented from diffusing more than necessary to the semiconductor layer disposed through the film. That is, since the lower layer is subjected to heat treatment at a higher temperature or longer time due to the film formation and thermal process when forming the memory cell array layer on the upper layer side, the thickness of the insulating films 102, 111, 113, 121, and 123 is increased as the upper layer is increased. By reducing the thickness, the diffusion of impurity atoms into the final semiconductor layers 11, 21, 201, 202, 203 can be made uniform, and the impurity concentrations of the semiconductor layers 11, 21, 201, 202, 203 can be made the same. it can.

  The impurity concentration of each diffusion source layer 101, 112, 122 and the thickness of each insulating film 102, 111, 113, 121, 123 are determined by the final impurity concentration of each semiconductor layer 11, 21, 201, 202, 203. It is previously determined by experiment so as to be a predetermined value.

  According to the second embodiment, the impurity concentration contained in the diffusion source layers 101, 112, and 122 at each height is made constant, and the thicknesses of the insulating films 102, 111, 113, 121, and 123 are increased from the lower layer to the upper layer. Thus, the amount of impurities diffused into the semiconductor layers 11, 21, 201, 202, 203 can be made substantially the same by the thermal process received after the formation of the respective diffusion source layers 101, 112, 122. Finally, there is an effect that a nonvolatile semiconductor memory device having a uniform concentration can be obtained.

(Third embodiment)
FIG. 8 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the third embodiment. This non-volatile semiconductor memory device is the same as the non-volatile semiconductor memory device of the first embodiment, with the insulating films 102, 111, 113, 121, and 123 having a constant thickness and impurities in the diffusion source layers 101, 112, and 122. The concentration is increased as it goes up. With such a configuration, the impurity concentration of each of the semiconductor layers 11, 21, 201, 202, 203 serving as the active region is made uniform (constant).

  Since the manufacturing method of such a nonvolatile semiconductor memory device is the same as that described in the first embodiment, the description thereof is omitted. However, as described above, the thicknesses of the insulating films 102, 111, 113, 121, and 123 at the same height are the same, and the impurity concentration in the diffusion source layers 101, 112, and 122 increases as it goes from the lower layer to the upper layer. Like to do. This is because the lower memory cell array layer is subjected to a higher temperature or longer heat treatment, so that the lower diffusion source layer is subjected to diffusion by a higher temperature or longer heat treatment by lowering the impurity concentration. In this case, impurities are prevented from diffusing more than necessary to the semiconductor layer disposed via the insulating film. That is, the lower layer is subjected to heat treatment at a higher temperature or longer time due to the film formation and thermal process in forming the upper memory cell array layer, so that the impurity concentration in the diffusion source layers 101, 112, and 122 is increased toward the upper layer. By increasing the level, the diffusion of impurity atoms into the final semiconductor layers 11, 21, 201, 202, 203 can be made uniform, and the impurity concentrations of the semiconductor layers 11, 21, 201, 202, 203 can be made the same. it can.

  The impurity concentration of each diffusion source layer 101, 112, 122 and the thickness of each insulating film 102, 111, 113, 121, 123 are determined by the final impurity concentration of each semiconductor layer 11, 21, 201, 202, 203. It is previously determined by experiment so as to be a predetermined value.

  According to the third embodiment, the thicknesses of the insulating films 102, 111, 113, 121, and 123 at the respective heights are made constant, and the impurity concentration contained in the diffusion source layers 101, 112, and 122 is increased from the lower layer to the upper layer. Therefore, the amount of impurities diffused into the semiconductor layers 11, 21, 201, 202, and 203 can be made substantially the same by the thermal process received by the diffusion source layers 101, 112, and 122. Therefore, the nonvolatile semiconductor memory device having a uniform concentration can be obtained.

  In the above example, the nonvolatile semiconductor memory device having a structure in which a plurality of the memory cell array groups CAG shown in FIGS. 1 to 3 are stacked via an interlayer insulating film in which an insulating film, a diffusion source layer, and an insulating film are stacked. Explained. However, for example, the nonvolatile semiconductor memory device having a structure in which the memory cell array layer CA12 is disposed on the memory cell array layer CA11 without the charge storage layer 13 facing each other with the interlayer insulating film interposed therebetween. The embodiments described above can be applied. In other words, when the memory cell array layer CA11 is diffused into a semiconductor layer serving as an active region of a nonvolatile semiconductor memory device having a structure in which a plurality of memory cell array layers CA11 are stacked through an interlayer insulating film in which an insulating film, a diffusion source layer, and an insulating film are stacked. Also, the above-described embodiment can be applied. In the above example, the nonvolatile memory has a memory cell having a structure in which the charge storage layer is disposed on the semiconductor layer via the tunnel insulating film, and the control gate is disposed on both sides of the charge storage layer via the inter-gate insulating film. The nonvolatile semiconductor memory device has been described with reference to a structure in which a memory cell is formed on a semiconductor layer serving as an active region as a unit and a plurality of the units stacked in the height direction. Also, the above-described embodiment can be applied.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  11, 21, 21 A, 201, 202, 203, 204... Semiconductor layer, 12, 22, 22 A ... Tunnel insulating film, 13, 23... Charge storage layer, 13 A. Films 16, 26 ... selection gates, 16A, 26A, 26B ... selection gate formation layers, 17, 27 ... selection gate lines, 17A ... selection gate line formation grooves, 23A, 23B ... charge storage layer formation layers, 31, 34 ... Interlayer insulating film, 32 ... Intergate insulating film, 33 ... Control gate, 33A ... Control gate forming layer, 55 ... Control gate forming groove, 101, 112, 122 ... Diffusion source layer, 102, 111, 113, 121, 123... Insulating film, CA, CA11, CA12, CA21, CA22, CA31, CA32... Memory cell array layer, CAG, CAG1 to CAG3.

Claims (6)

A first memory layer in which a memory cell is formed on a first semiconductor layer serving as an active region, and a second memory layer in which a memory cell is formed on a second semiconductor layer serving as an active region are stacked,
The first memory layer is formed on the main surface of the sheet-like first semiconductor layer on the second memory layer arrangement side at a predetermined interval in the longitudinal direction of the first semiconductor layer via a first tunnel insulating film. A first charge storage layer provided;
The second memory layer corresponds to a formation position of the first charge storage layer on a main surface of the sheet-like second semiconductor layer on the first memory layer arrangement side via a second tunnel insulating film. A second charge storage layer provided;
The first charge storage layer and the second charge storage layer are provided via an interlayer insulating film,
A non-volatile semiconductor memory device in which control gates are provided on both sides in the longitudinal direction of the stacked body of the first charge storage layer, the interlayer insulating film, and the second charge storage layer through an inter-gate insulating film,
The surface of the first semiconductor layer opposite to the main surface on the second memory layer disposition side is disposed on the first diffusion source layer containing impurity atoms via the first insulating film,
The surface of the second semiconductor layer opposite to the main surface on the first memory layer arrangement side is arranged on the second diffusion source layer containing the impurity atoms via a second insulating film,
The thickness of the second insulating film is smaller than the thickness of the first insulating film,
The nonvolatile semiconductor memory device, wherein the impurity concentration of the second diffusion source layer is higher than the impurity concentration of the first diffusion source layer. Nonvolatile in which a first memory layer in which a memory cell is formed on a first semiconductor layer serving as an active region and a second memory layer in which a memory cell is formed on a second semiconductor layer serving as an active region are stacked In a semiconductor memory device,
The main surface of the first semiconductor layer on the second memory layer arrangement side is arranged on the first diffusion source layer containing impurity atoms via the first insulating film,
The main surface of the second semiconductor layer on the first memory layer arrangement side is arranged on the second diffusion source layer containing the impurity atoms with a second insulating film interposed therebetween. .   The nonvolatile semiconductor memory device according to claim 2, wherein a thickness of the second insulating film is smaller than a thickness of the first insulating film.   4. The nonvolatile semiconductor memory device according to claim 2, wherein the impurity concentration of the second diffusion source layer is higher than the impurity concentration of the first diffusion source layer. 5. The first memory layer is formed on the main surface of the sheet-like first semiconductor layer on the second memory layer arrangement side at a predetermined interval in the longitudinal direction of the first semiconductor layer via a first tunnel insulating film. A first charge storage layer provided;
The second memory layer corresponds to a formation position of the first charge storage layer on a main surface of the sheet-like second semiconductor layer on the first memory layer arrangement side via a second tunnel insulating film. A second charge storage layer provided;
The first charge storage layer and the second charge storage layer are provided via an interlayer insulating film,
5. A control gate is provided on both sides in the longitudinal direction of the laminate of the first charge storage layer, the interlayer insulating film, and the second charge storage layer via an inter-gate insulating film. The nonvolatile semiconductor memory device according to any one of the above. Forming a first diffusion source layer containing impurity atoms and a first insulating film on the substrate in order;
Forming a first semiconductor layer serving as an active region on the first insulating film;
Forming a first tunnel insulating film and a first charge storage layer in order on the first semiconductor layer;
Forming an interlayer insulating film on the first charge storage layer;
Forming a second charge storage layer on the interlayer insulating film;
Forming a groove from the second charge storage layer to the first tunnel insulating film in a predetermined direction at a predetermined interval;
Forming an inter-gate insulating film so as to conformally cover the inner surface of the groove;
Embedding a control gate in the trench covered with the inter-gate insulating film;
Forming a second tunnel insulating film on the top surfaces of the second charge storage layer and the control gate;
Forming a second semiconductor layer serving as an active region on the second tunnel insulating film;
Forming a second insulating film and a second diffusion source layer containing the impurity atoms in order on the second semiconductor layer;
A method for manufacturing a nonvolatile semiconductor memory device, comprising:

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