JP2013201193A - Method for manufacturing semiconductor light-emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor light-emitting device capable of simplifying element isolation.SOLUTION: According to an embodiment, a method for manufacturing a semiconductor light-emitting device comprises the steps of: forming a salient on a surface of a substrate by processing the surface of the substrate; forming a semiconductor layer including a light-emitting layer in a recess adjacent to the salient in the substrate in a state in which an upper surface of the salient is covered by a cap film; forming a non-light-emitting region not including the light-emitting layer on a surface side of the semiconductor layer by selectively removing a partial region on the surface side of the semiconductor layer; forming an n-side electrode on a surface of the non-light-emitting region in the semiconductor layer; forming a p-side electrode on a surface of the light-emitting region including the light-emitting layer in the semiconductor layer; and separating the semiconductor layer into a plurality of regions by removing at least the salient in the substrate.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor light emitting device.

  2. Description of the Related Art A method for manufacturing a semiconductor light emitting device is known in which a semiconductor layer including a light emitting layer, an electrode, and the like are formed on a substrate, and then the semiconductor layer is separated into a plurality of pieces (on a wafer level) on the substrate.

JP 2011-71272 A

  Embodiments of the present invention provide a method of manufacturing a semiconductor light emitting device that can simplify element isolation.

  According to the embodiment, the method for manufacturing a semiconductor light emitting device includes a step of processing the surface of the substrate and forming a convex portion on the surface of the substrate. The method for manufacturing a semiconductor light emitting device includes a step of forming a semiconductor layer including a light emitting layer in a concave portion adjacent to the convex portion in the substrate in a state where an upper surface of the convex portion is covered with a cap film. Further, the method for manufacturing the semiconductor light emitting device includes a step of selectively removing a partial region on the surface side of the semiconductor layer and forming a non-light emitting region not including the light emitting layer on the surface side of the semiconductor layer. Have. The method for manufacturing a semiconductor light emitting device includes a step of forming an n-side electrode on the surface of the non-light emitting region in the semiconductor layer. The method for manufacturing a semiconductor light emitting device includes a step of forming a p-side electrode on a surface of the light emitting region including the light emitting layer in the semiconductor layer. Further, the method for manufacturing the semiconductor light emitting device includes a step of removing at least the protrusions on the substrate and separating the semiconductor layer into a plurality of parts.

(A) is a schematic cross section of the semiconductor light emitting device of the embodiment, (b) is a schematic top view of the semiconductor light emitting device of the embodiment. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the semiconductor light emitting device of the embodiment. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the semiconductor light emitting device of the embodiment. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the semiconductor light emitting device of the embodiment. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the semiconductor light emitting device of the embodiment. FIG. 3 is a schematic plan view showing a method for manufacturing the semiconductor light emitting device of the embodiment. The schematic cross section of the semiconductor light-emitting device of other embodiment. Furthermore, the schematic cross section of the semiconductor light-emitting device of other embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element in each drawing.

  FIG. 1A is a schematic cross-sectional view of the semiconductor light-emitting device of the embodiment, and FIG. 1B is a schematic top view of the semiconductor light-emitting device shown in FIG.

  The semiconductor light emitting device of the embodiment includes a semiconductor layer 15. The semiconductor layer 15 has a first surface 15a and a second surface formed on the opposite side. Light is mainly emitted from the first surface (the upper surface in FIG. 1A) 15a of the semiconductor layer 15 to the outside. A p-side electrode 13 and an n-side electrode 14 are provided on the second surface of the semiconductor layer 15.

  The semiconductor layer 15 includes a first semiconductor layer 11 and a second semiconductor layer 12. The first semiconductor layer 11 and the second semiconductor layer 12 are made of a material containing, for example, gallium nitride. The first semiconductor layer 11 includes, for example, an n-type layer that functions as a current lateral path. The second semiconductor layer 12 includes a p-type layer and a light emitting layer (active layer) 12a.

  The second surface of the semiconductor layer 15 is processed into an uneven shape, and a part of the light emitting layer 12a is removed. Accordingly, the second surface of the semiconductor layer 15 includes the light emitting region 3 including the light emitting layer 12a (or facing the light emitting layer 12a) and the non-light emitting region 4 not including the light emitting layer 12a (or not facing the light emitting layer 12a). And have.

  The p-side electrode 13 is provided in the light emitting region 3 on the second surface, and the n-side electrode 14 is provided in the non-light emitting region 4 on the second surface. On the second surface, the area of the light emitting region 3 is larger than the area of the non-light emitting region 4. The area where the p-side electrode 13 extends on the second surface (light-emitting region 3) is larger than the area where the n-side electrode 14 extends on the second surface (non-light-emitting region 4).

  An insulating film 31 is provided in a portion where the p-side electrode 13 and the n-side electrode 14 are not provided on the second surface. The insulating film 31 is also provided at the step portion between the light emitting region 3 and the non-light emitting region 4. The insulating film 31 is an inorganic insulating film such as a silicon oxide film or a silicon nitride film.

  The p-side electrode 13 is covered with a p-side pad 16, and the n-side electrode 14 is covered with an n-side pad 17. The p-side pad 16 and the n-side pad 17 are made of a metal material, and serve as electrode protection and a reflective layer.

  A first insulating layer (hereinafter simply referred to as an insulating layer) 32 is further provided on the second surface side. The insulating layer 32 covers the insulating film 31, a part of the p-side pad 16, and a part of the n-side pad 17. The insulating film 31 and the insulating layer 32 are not provided on the first surface 15a.

  The insulating layer 32 is, for example, a resin such as polyimide having excellent patterning characteristics for fine openings. Alternatively, an inorganic material such as silicon oxide or silicon nitride can be used for the insulating layer 32.

  In the insulating layer 32, a plurality of first openings 32 a reaching the p-side pad 16 and a second opening 32 b reaching the n-side pad 17 are formed.

  On the insulating layer 32, the p-side wiring layer 18 and the n-side wiring layer 19 are provided so as to be separated from each other. The p-side wiring layer 18 is also provided in the first opening 32 a and is electrically connected to the p-side pad 16 and the p-side electrode 13. The n-side wiring layer 19 is also provided in the second opening 32 b and is electrically connected to the n-side pad 17 and the n-side electrode 14.

  A p-side metal pillar 21 is provided on the surface of the p-side wiring layer 18 opposite to the semiconductor layer 15. The p-side metal pillar 21 is thicker than the p-side wiring layer 18. The p-side wiring layer 18 and the p-side metal pillar 21 constitute the p-side wiring part in the embodiment.

  An n-side metal pillar 22 is provided on the surface opposite to the semiconductor layer 15 in the n-side wiring layer 19. The n-side metal pillar 22 is thicker than the n-side wiring layer 19. The n-side wiring layer 19 and the n-side metal pillar 22 constitute the n-side wiring portion in the embodiment.

  A resin layer 33 is provided on the insulating layer 32 as a second insulating layer. The resin layer 33 covers the periphery of the p-side wiring portion and the periphery of the n-side wiring portion.

  The surface of the p-side wiring layer 18 other than the connection surface with the p-side metal pillar 21 and the surface of the n-side wiring layer 19 other than the connection surface with the n-side metal pillar 22 are covered with the resin layer 33. The resin layer 33 is provided between the p-side metal pillar 21 and the n-side metal pillar 22 and covers the side surface of the p-side metal pillar 21 and the side surface of the n-side metal pillar 22. The resin layer 33 is filled between the p-side metal pillar 21 and the n-side metal pillar 22.

  A surface of the p-side metal pillar 21 opposite to the p-side wiring layer 18 is exposed without being covered with the resin layer 33, and functions as a p-side external terminal 21a bonded to the mounting substrate. The surface of the n-side metal pillar 22 opposite to the n-side wiring layer 19 is exposed without being covered with the resin layer 33, and functions as an n-side external terminal 22a that is bonded to the mounting substrate.

  Each of the p-side wiring part, the n-side wiring part, and the resin layer 33 is thicker than the semiconductor layer 15. The aspect ratio (ratio of the thickness to the planar size) of the p-side metal pillar 21 and the n-side metal pillar 22 is not limited to 1 or more, and the ratio may be smaller than 1.

  The p-side metal pillar 21, the n-side metal pillar 22, and the resin layer 33 that reinforces these function as a support for the semiconductor layer 15. Therefore, even if the substrate used for forming the semiconductor layer 15 is removed as described later, the semiconductor layer 15 is stabilized by the support including the p-side metal pillar 21, the n-side metal pillar 22, and the resin layer 33. The mechanical strength of the semiconductor light emitting device can be increased.

  Moreover, the stress applied to the semiconductor layer 15 in a state where the semiconductor light emitting device is mounted on the mounting substrate can be relaxed by the p-side metal pillar 21 and the n-side metal pillar 22 absorbing.

  The p-side wiring portion including the p-side wiring layer 18 and the p-side metal pillar 21 is connected to the p-side pad 16 through a plurality of vias provided in the plurality of first openings 32a and separated from each other. Yes. For this reason, the high stress relaxation effect by a p side wiring part is acquired.

  Alternatively, as shown in FIG. 8, the p-side wiring layer 18 may be connected to the p-side pad 16 through one large first opening 32a. In this case, the p-side electrode 13 that is a metal is used. The heat dissipation of the light emitting layer 12a can be improved through the p-side pad 16, the p-side wiring layer 18 and the p-side metal pillar 21.

  As a material for the p-side wiring layer 18, the n-side wiring layer 19, the p-side metal pillar 21, and the n-side metal pillar 22, copper, gold, nickel, silver, or the like can be used. Among these, when copper is used, good thermal conductivity, high migration resistance, and excellent adhesion with an insulating material can be obtained.

  It is desirable to use a resin layer 33 having the same or close thermal expansion coefficient as the mounting substrate. As such a resin layer, an epoxy resin, a silicone resin, a fluororesin, etc. can be mentioned as an example, for example.

  The first semiconductor layer 11 is electrically connected to the n-side metal pillar 22 including the n-side external terminal 22 a through the n-side electrode 14, the n-side pad 17, and the n-side wiring layer 19. The second semiconductor layer 12 including the light emitting layer 12a is electrically connected to the p-side metal pillar 21 including the p-side external terminal 21a via the p-side electrode 13, the p-side pad 16, and the p-side wiring layer 18. ing.

  A part of the n-side wiring layer 19 overlaps a portion on the insulating layer 32 facing the light emitting layer 12a. The area of the n-side wiring layer 19 extending on the insulating layer 32 is larger than the area where the n-side wiring layer 19 is connected to the n-side pad 17.

  According to the embodiment, a high light output can be obtained by the light emitting layer 12 a formed over a region wider than the n-side electrode 14. In addition, the n-side electrode 14 provided in the non-light-emitting region 4 that does not include the light-emitting layer 12a and is narrower than the light-emitting region 3 has been rearranged on the mounting surface side as the n-side wiring layer 19 having a larger area. The structure can be realized.

  The area where the p-side wiring layer 18 is connected to the p-side pad 16 through the plurality of first openings 32a is larger than the area where the n-side wiring layer 19 is connected to the n-side pad 17 through the second opening 32b. Therefore, the current distribution to the light emitting layer 12a can be improved, and the heat dissipation of the heat generated in the light emitting layer 12a can be improved.

  A phosphor layer 40 is provided on the first surface 15 a of the semiconductor layer 15. Further, the phosphor layer 40 is also provided on the side surface 15 c of the semiconductor layer 15. All of the side surface 15 c of the semiconductor layer 15 is covered with the phosphor layer 40. The phosphor layer 40 provided on the side surface 15c is supported on a laminate of the insulating film 31, the insulating layer 32, and the resin layer 33.

  The phosphor layer 40 includes phosphor particles that can absorb the emitted light (excitation light) from the light emitting layer 12a and emit wavelength-converted light. The phosphor particles are dispersed in a transparent resin that is transparent to the light from the light emitting layer 12a and the wavelength-converted light in the phosphor particles. The semiconductor light emitting device of the embodiment can emit mixed light of light from the light emitting layer 12a and wavelength converted light by phosphor particles.

  For example, when the phosphor particles are yellow phosphor particles that emit yellow light, as a mixed color of blue light from the light emitting layer 12a that is a GaN-based material and yellow light that is wavelength converted light in the phosphor layer 40, White or light bulb color can be obtained.

  As the phosphor layer, a red phosphor layer, a yellow phosphor layer, a green phosphor layer, and a blue phosphor layer exemplified below can be used.

The red phosphor layer can contain, for example, a nitride phosphor CaAlSiN ₃ : Eu or a sialon phosphor.

When using sialon phosphors,
(M _1-x , R _x ) _a1 AlSi _b1 O _c1 N _d1 ... Formula (1)
(M is at least one metal element excluding Si and Al, and is preferably at least one of Ca or Sr. R is a luminescent center element, and particularly Eu, x, a1, b1, c1, d1 satisfies the following relationship: 0 <x ≦ 1, 0.6 <a1 <0.95, 2 <b1 <3.9, 0.25 <c1 <0.45, 4 <d1 <5.7. ) Can be used.

  By using the sialon-based phosphor represented by the composition formula (1), the temperature characteristics of the wavelength conversion efficiency can be improved, and the efficiency in the large current density region can be further improved.

The yellow phosphor layer can contain, for example, a silicate phosphor (Sr, Ca, Ba) ₂ SiO ₄ : Eu.

The green phosphor layer can contain, for example, a halophosphate phosphor (Ba, Ca, Mg) ₁₀ (PO ₄ ) ₆ .Cl ₂ : Eu or a sialon phosphor.

When using sialon phosphors,
(M _1-x , R _x ) _a2 AlSi _b2 O _c2 N _d2 ... Formula (2)
(M is at least one metal element excluding Si and Al, and at least one of Ca and Sr is particularly desirable. R is an emission center element, and particularly Eu is preferred. X, a2, b2, c2, d2 satisfies the following relationship: 0 <x ≦ 1, 0.93 <a2 <1.3, 4.0 <b2 <5.8, 0.6 <c2 <1, 6 <d2 <11) Can be used.

  By using the sialon-based phosphor represented by the composition formula (2), the temperature characteristics of the wavelength conversion efficiency can be improved, and the efficiency in the large current density region can be further improved.

The blue phosphor layer can contain, for example, an oxide phosphor BaMgAl ₁₀ O ₁₇ : Eu.

  According to the semiconductor light emitting device of the embodiment, since not only the first surface 15a but also the side surface 15c of the semiconductor layer 15 is covered with the phosphor layer 40, light emitted from the side surface 15c also passes through the phosphor layer 40. can do. For this reason, it is possible to suppress, for example, strong bluish light leakage from the side surface 15c and to suppress variations in chromaticity.

  The insulating support part including the insulating film 31, the insulating layer 32, and the resin layer 33 provided on the second surface side of the semiconductor layer 15 has a larger planar size than the semiconductor layer 15, and the insulating support part is a semiconductor layer. It protrudes outward from the side surface 15 c of 15.

  And the fluorescent substance layer 40 which covers the side surface 15c is located on the said insulation support part above the external terminals 21a and 22a, and the side surface of an insulation support part is not covered. That is, the phosphor layer 40 is not wasted in a portion where light is not emitted, and the cost can be reduced.

  For example, as a comparative example, when a chip is flip-chip mounted on a mounting substrate and then the chip is covered with a phosphor layer, it is difficult to form the phosphor layer so as to cover only the semiconductor layer, and the wiring layer under the chip In addition, the phosphor layer is supplied to the package structure, the external terminals, etc., and is wasted.

  On the other hand, according to the embodiment, the phosphor layer 40 is formed only on the first surface 15a of the semiconductor layer 15 and the side surface 15c continuing from the first surface 15a by the manufacturing method described below. Is possible.

  Next, with reference to FIG. 2A to FIG. 6B, a method for manufacturing the semiconductor light emitting device of the embodiment will be described.

  FIG. 2A shows a cross section of the wafer in which the mask layer 51 is selectively formed on the main surface of the substrate 10. For example, the substrate 10 is a silicon substrate, and the mask layer 51 is a silicon oxide film.

  The surface of the substrate 10 is etched by, for example, RIE (Reactive Ion Etching) using the mask layer 51 as a mask. Thereby, as shown in FIG. 2 (b), a convex portion 10 a is formed on the surface of the substrate 10. Moreover, the recessed part 10b is formed adjacent to the convex part 10a. Since the substrate 10 is a silicon substrate, it is possible to easily perform uneven processing with high accuracy.

  Here, FIG. 6A corresponds to the top view of FIG.

  The mask layer 51 and the convex portion 10a below the mask layer 51 are formed, for example, in a lattice-like plane pattern on the wafer surface. The convex portion 10a is formed in a planar pattern that continuously surrounds the concave portion 10b. In FIG. 6A, for example, a rectangular planar recess 10b is shown, but the planar shape of the recess 10b is not limited to a rectangular shape.

  After removing the mask layer 51 used for the concave / convex mask of the substrate 10, a cap film 61 is formed on the upper surface of the convex portion 10a as shown in FIG. The cap film 61 is, for example, a silicon oxide film. Alternatively, a silicon nitride film can be used as the cap film 61.

  Then, with the upper surface of the convex portion 10a covered with the cap film 61, the semiconductor layer 15 is formed in the concave portion 10b as shown in FIG.

  Alternatively, the mask layer 51 used for processing the substrate 10 may be left as it is on the convex portion 10a and used as a cap film when the semiconductor layer 15 is formed. In this case, the cost can be reduced by reducing the process and material.

  For example, the semiconductor layer 15 made of a gallium nitride material is epitaxially grown on the substrate 10 by MOCVD (metal organic chemical vapor deposition). The semiconductor layer 15 is epitaxially grown only on the bottom surface of the recess 10 b where the surface of the substrate 10 is exposed without being covered with the cap film 61.

  A first semiconductor layer 11 is formed on the main surface of the substrate 10, and a second semiconductor layer 12 is formed on the first semiconductor layer 11. The first semiconductor layer 11 includes a base buffer layer, an n-type GaN layer, and the like. The second semiconductor layer 12 includes a light emitting layer 12a, a p-type GaN layer, and the like. As the light emitting layer 12a, a material that emits blue, purple, blue purple, near ultraviolet, ultraviolet light, or the like can be used.

  The film thickness of the semiconductor layer 15 is controlled to be the same as the height of the convex portion 10a or smaller than the height of the convex portion 10a. The semiconductor layer 15 does not overgrow on the cap film 61. After the formation of the semiconductor layer 15, the cap film 61 is removed as shown in FIG.

  Here, FIG. 6B corresponds to the top view of FIG.

  The convex part 10a is formed in a lattice-like plane pattern on the wafer surface, for example. The convex portion 10 a is formed in a planar pattern that continuously surrounds the semiconductor layer 15.

  The upper surface of the semiconductor layer 15 and the upper surface of the convex portion 10a of the substrate 10 are substantially flush with each other, and a mask layer 55 shown in FIG. 3B is formed on these upper surfaces. An opening 55 a is selectively formed in the mask layer 55. The mask layer 55 is a silicon oxide film, for example.

  Then, a partial region on the surface side of the semiconductor layer 15 exposed to the opening 55a is selectively removed by, for example, RIE using the mask layer 55. In the portion below the opening 55a, the light emitting layer 12a is removed, and the non-light emitting region 4 not including the light emitting layer 12a is formed on the surface side of the semiconductor layer 15.

  After removing the mask layer 55, the exposed portion on the substrate 10 is covered with an insulating film 31 as shown in FIG. The insulating film 31 is formed on the upper surface of the convex portion 10a and the upper surface (second surface) of the semiconductor layer 15 in FIG.

  Next, a part of the insulating film 31 on the non-light-emitting region 4 is removed to expose a part of the non-light-emitting region 4, and n is formed on the exposed non-light-emitting region 4 as shown in FIG. The side electrode 14 is formed. Further, a part of the insulating film 31 on the light emitting region 3 is removed to expose a part of the light emitting region 3, and a p-side electrode 13 is formed on the exposed light emitting region 3 as shown in FIG. Form.

  The n-side electrode 14 and the p-side electrode 13 are formed by, for example, a sputtering method or a vapor deposition method. Either the n-side electrode 14 or the p-side electrode 13 may be formed first, or may be formed of the same material at the same time.

  Next, as shown in FIG. 4B, the p-side pad 16 is formed on the p-side electrode 13, and the n-side pad 17 is formed on the n-side electrode 14. The area of the upper surface of the p-side pad 16 is larger than the contact area between the p-side electrode 13 and the semiconductor layer 15. The area of the upper surface of the n-side pad 17 is larger than the contact area between the n-side electrode 14 and the semiconductor layer 15.

  Next, all exposed portions of the structure on the substrate 10 obtained in the steps up to FIG. 4B are covered with the insulating layer 32 shown in FIG. Thereafter, a first opening 32a and a second opening 32b are formed in the insulating layer 32 by etching using a resist mask (not shown). The first opening 32 a reaches the p-side pad 16. The second opening 32 b reaches the n-side pad 17.

  Next, a metal film (not shown) that functions as a seed metal for plating is formed on the upper surface of the insulating layer 32, the inner walls (side walls and bottom) of the first opening 32a, and the inner walls (side walls and bottom) of the second opening 32b. . Then, a resist (not shown) is selectively formed on the metal film, and Cu electrolytic plating using the metal film as a current path is performed.

  By this plating, the p-side wiring layer 18 and the n-side wiring layer 19 are formed on the insulating layer 32 as shown in FIG. The p-side wiring layer 18 and the n-side wiring layer 19 are made of, for example, a copper material that is simultaneously formed by a plating method.

  The p-side wiring layer 18 is also formed in the first opening 32a, and is electrically connected to the p-side pad 16 through the metal film that is a seed metal. The n-side wiring layer 19 is also formed in the second opening 32b and is electrically connected to the n-side pad 17 through the metal film that is a seed metal.

  Next, using a resist (not shown) as a mask, Cu electrolytic plating using the remaining metal film as a current path is performed. By this plating, a p-side metal pillar 21 and an n-side metal pillar 22 are formed as shown in FIG. The p-side metal pillar 21 is formed on the p-side wiring layer 18, and the n-side metal pillar 22 is formed on the n-side wiring layer 19.

  After the p-side metal pillar 21 and the n-side metal pillar 22 are formed, the exposed portion of the metal film used as the seed metal is removed. Therefore, the metal film connected between the p-side wiring layer 18 and the n-side wiring layer 19 is divided.

  Next, as shown in FIG. 5A, a resin layer 33 is formed on the insulating layer 32 around the p-side metal pillar 21 and around the n-side metal pillar 22.

  Then, the substrate 10 is removed together with the protrusions 10a in a state where the semiconductor layer 15 is supported on the support including the p-side metal pillar 21, the n-side metal pillar 22, and the resin layer 33. The substrate 10 is a silicon substrate, for example, and can be easily removed by wet etching or dry etching.

  FIG. 5B shows a state after the substrate 10 is removed. By removing the convex portion 10a, a groove 56 reaching the insulating film 31 is formed. The semiconductor layer 15 is separated into a plurality by the grooves 56. That is, a structure in which the semiconductor layer 15 is separated into a plurality of elements simultaneously with the removal of the substrate 10 is obtained.

  Since the semiconductor layer 15 is supported by a thicker support (p-side metal pillar 21, n-side metal pillar 22, and resin layer 33), the wafer state can be maintained even when the substrate 10 is removed. is there.

  Further, the resin constituting the resin layer 33 and the metal constituting the p-side metal pillar 21 and the n-side metal pillar 22 are softer materials than the semiconductor layer 15 made of a GaN-based material. Therefore, even if a large internal stress generated by epitaxial growth for forming the semiconductor layer 15 on the substrate 10 is released at a time when the substrate 10 is removed, the semiconductor layer 15 can be prevented from being damaged.

  After removing the substrate 10, the first surface 15 a is cleaned, and a frost process is performed to form irregularities as necessary. The light extraction efficiency can be improved by forming minute irregularities on the first surface 15a.

  Thereafter, as shown in FIG. 5C, the phosphor layer 40 is formed on the first surface 15a. Further, the phosphor layer 40 is also filled in the groove 56, and the phosphor layer 40 is also provided on the side surface 15 c of the semiconductor layer 15 facing the groove 56.

  The step of forming the phosphor layer 40 includes a step of supplying a liquid transparent resin in which phosphor particles are dispersed on the first surface 15a by a method such as printing, potting, molding, compression molding, and the like. Heat curing.

  Further, the resin layer 33 is ground, and the p-side external terminal 21a and the n-side external terminal 22a are exposed from the resin layer 33 as shown in FIG.

  Then, the phosphor layer 40, the insulating film 31, the insulating layer 32, and the resin layer 33 are cut at the position of the groove 56 and separated into a plurality of semiconductor light emitting devices. At this time, the phosphor layer 40 is left on the side surface 15 c of the semiconductor layer 15 without removing all the phosphor layer 40 in the groove 56.

  Since the semiconductor layer 15 is not formed in the groove 56, the semiconductor layer 15 is not damaged during dicing.

  Each process described above before dicing is performed in a lump in a wafer state. Therefore, it is not necessary to form a support, protect a chip with an insulating material, and form a phosphor layer for each individual semiconductor light emitting device after dicing, and can greatly reduce the production cost. The phosphor layer 40 is already formed on the first surface 15a and the side surface 15c of the semiconductor layer 15 in the state of being separated into pieces as shown in FIGS.

  According to the embodiment described above, the semiconductor layer 15 is formed on the substrate 10 in a state in which the protrusions 10 a are processed in advance in the portion that becomes the element isolation region in the substrate 10. That is, the semiconductor layer 15 is formed on the substrate 10 in a state where the plurality of elements are already separated by the convex portion 10a. Therefore, it is not necessary to separate the semiconductor layer 15 after forming the electrodes 13 and 14 and the pads 16 and 17, and the element isolation process can be simplified.

  As the substrate 10, a sapphire substrate may be used. The sapphire substrate can be removed by, for example, a laser lift-off method.

  That is, laser light is irradiated from the back surface side of the sapphire substrate toward the first semiconductor layer 11. The laser light is transmissive to the sapphire substrate and has a wavelength that becomes an absorption region for the first semiconductor layer 11.

  When the laser light reaches the interface between the sapphire substrate and the first semiconductor layer 11, the first semiconductor layer 11 near the interface absorbs the energy of the laser light and decomposes. For example, the first semiconductor layer 11 made of a GaN-based material is decomposed into gallium (Ga) and nitrogen gas. By this decomposition reaction, a minute gap is formed between the sapphire substrate and the first semiconductor layer 11, and the sapphire substrate and the first semiconductor layer 11 are separated. Laser light irradiation is performed over the entire wafer in multiple times for each set region, and the sapphire substrate is removed.

  When the semiconductor layer 15 is, for example, a nitride semiconductor layer, the sapphire substrate is transmissive to light emitted from the semiconductor layer 15. Therefore, the sapphire substrate may be left on the first surface 15a without being removed.

  4D, the phosphor layer 40 is formed on the substrate 10, and in this state, the substrate 10 on the first surface 15a is not removed, and only the convex portion 10a is diced. It may be removed and separated into individual pieces. For example, it is possible to remove the convex portion 10a during dicing using a blade having a blade width equal to or larger than the width of the convex portion 10a. FIG. 7A shows a schematic cross-sectional view of the separated semiconductor light emitting device. In the case of this structure, the p-side wiring layer 18 and the n-side wiring layer 19 function as external terminals.

  Further, after the step of FIG. 5A, the phosphor layer 40 is formed on the substrate 10, and in this state, the substrate 10 on the first surface 15a is not removed, and only the convex portion 10a is diced. It may be removed and separated into individual pieces. FIG. 7B shows a schematic cross-sectional view of the separated semiconductor light emitting device.

  Further, the phosphor layer 40 is not necessarily provided. Alternatively, a lens layer may be provided on the first surface 15a.

  After the step of FIG. 5B with the substrate 10 removed, an insulating film may be formed on the entire exposed portion, and then the phosphor layer 40 may be formed. The insulating film is, for example, a silicon oxide film or a silicon nitride film formed by a sputtering method or a plasma chemical vapor deposition method and having a thickness that does not decrease the light extraction efficiency. Thereby, it is possible to prevent the refractive index of the medium from changing greatly in the light extraction direction through the first surface 15a, and to improve the light extraction efficiency. In addition, the adhesion between the phosphor layer 40 and the first surface 15a can be improved.

According to the embodiment, forming a first insulating layer having a first opening reaching the p-side electrode and a second opening reaching the n-side electrode on the p-side electrode and the n-side electrode; And a step of forming a p-side wiring layer on the first insulating layer and in the first opening, and a step of forming an n-side wiring layer on the first insulating layer and in the second opening. Yes.
According to the embodiment, after the p-side wiring layer and the n-side wiring layer are formed, the substrate is removed together with the convex portions.
In addition, according to the embodiment, there is provided a step of forming a phosphor layer in the groove formed by removing the convex portion and on the surface of the semiconductor layer.
According to the embodiment, the method includes a step of forming a p-side metal pillar on the p-side wiring layer and a step of forming an n-side metal pillar on the n-side wiring layer.
In addition, according to the embodiment, the method includes the step of forming the second insulating layer on the side surface of the p-side metal pillar and the side surface of the n-side metal pillar.
In addition, according to the embodiment, after forming the p-side metal pillar and the n-side metal pillar, the substrate is removed together with the convex portions.
In addition, according to the embodiment, there is provided a step of forming a phosphor layer in the groove formed by removing the convex portion and on the surface of the semiconductor layer.
In addition, according to the embodiment, the method includes the step of cutting the phosphor layer and the first insulating layer at the position of the groove, leaving the phosphor layer on the side surface facing the groove of the semiconductor layer.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 3 ... Light emission area | region, 4 ... Non light emission area | region, 10 ... Substrate, 10a ... Convex part, 10b recessed part, 11 ... 1st semiconductor layer, 12 ... 2nd semiconductor layer, 12a ... Light emission layer, 13 ... P side electrode, 14 ... n-side electrode, 15 ... semiconductor layer, 15c ... side surface, 16 ... p-side pad, 17 ... n-side pad, 18 ... p-side wiring layer, 19 ... n-side wiring layer, 21 ... p-side metal pillar, 22 ... n-side metal pillar, 40 ... phosphor layer, 56 ... groove, 51 ... mask layer, 61 ... cap film

Claims (5)

Processing the surface of the silicon substrate, forming a protrusion on the surface of the silicon substrate;
Forming a semiconductor layer including a light emitting layer in a concave portion adjacent to the convex portion in the silicon substrate in a state where the upper surface of the convex portion is covered with a cap film;
Selectively removing a partial region on the surface side of the semiconductor layer, and forming a non-light emitting region not including the light emitting layer on the surface side of the semiconductor layer;
Forming an n-side electrode on a surface of the non-light-emitting region in the semiconductor layer;
Forming a p-side electrode on the surface of the light emitting region including the light emitting layer in the semiconductor layer;
Removing the silicon substrate together with the protrusions and separating the semiconductor layer into a plurality of parts;
A method for manufacturing a semiconductor light emitting device comprising: Processing the surface of the substrate, forming a protrusion on the surface of the substrate;
Forming a semiconductor layer including a light emitting layer in a concave portion adjacent to the convex portion of the substrate in a state where the upper surface of the convex portion is covered with a cap film;
Selectively removing a partial region on the surface side of the semiconductor layer, and forming a non-light emitting region not including the light emitting layer on the surface side of the semiconductor layer;
Forming an n-side electrode on a surface of the non-light-emitting region in the semiconductor layer;
Forming a p-side electrode on the surface of the light emitting region including the light emitting layer in the semiconductor layer;
Removing at least the protrusions on the substrate and separating the semiconductor layer into a plurality of layers;
A method for manufacturing a semiconductor light emitting device comprising:   The method of manufacturing a semiconductor light emitting device according to claim 1, wherein the convex portion is formed in a planar pattern that continuously surrounds the concave portion.   The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the semiconductor layer is formed with a film thickness equal to or less than a height of the convex portion.   The mask layer used for processing the substrate for forming the convex portion is left as it is on the convex portion and used as the cap film when forming the semiconductor layer. Manufacturing method of the semiconductor light-emitting device.

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