JP2013200827A - Process scheduling device, process scheduling method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a process scheduling device, a process scheduling method, and a program, capable of suppressing performance deterioration in a multiple CPU system.SOLUTION: A process scheduling device 30 includes: a cost calculating part 31 for calculating, for each process, a maintenance cost for maintaining consistency in a content of each CPU on the basis of information indicative of an access state to a cache of each CPU or a memory 12 acquired for each process executed by a computer 100 so as to perform scheduling processes in the computer 100 having CPUs 10 and 11; a grouping part 32 for separating respective processes into groups on the basis of a calculated maintenance cost for each process; and a scheduling part 33 for allocating, for each group, respective processes to either of the CPUs.

Description

  The present invention relates to a process scheduling apparatus, a process scheduling method, and a program for realizing these processes, for performing process scheduling in a multi-CPU system.

  In recent years, the rise in the number of clocks of a CPU (Central Processing Unit) has come to a limit, and the use of a multi-core CPU having a plurality of processor cores has increased. FIG. 12 is a diagram showing a schematic configuration of a conventional general multi-core CPU. As shown in FIG. 12, in a general multi-core CPU, each core has an L1 cache and an L2 cache, respectively, and shares one L3 cache in the CPU.

  In addition, in order to further improve the processing capability of computers, the use of multi-CPU systems equipped with a plurality of such multi-core CPUs is also increasing. However, in a multi-CPU system having a plurality of multi-core CPUs, caches are disabled to maintain cache coherency when each process executed by different physical CPUs accesses the same memory area. Processing may be performed and memory access may be delayed. As a result, there arises a problem that the performance in the system is degraded.

  Here, the memory access delay will be described with reference to FIG. FIG. 13 is a diagram for explaining an operation in a conventional multi-CPU system. As shown in FIG. 13, when the CPU 2 accesses the memory to execute the process and requests to write the data X, another CPU 1 has already read the data X into its own L3 cache. Suppose that

  In this case, in order to maintain the consistency of the cache, the cache consistency maintenance mechanism (cache coherency mechanism) of the system invalidates the data X on the L3 cache of another CPU 1 and executes write back to the memory. For this reason, another CPU 1 needs to load data X from the memory into its own L3 cache again.

  When such a cache invalidation process is performed, the data access (read / write) of the CPU is delayed while data is loaded from the memory, and the performance is greatly reduced as compared with the case where the CPU operates alone. For example, when processes running on different CPUs share the same lock, when accessing a shared memory area between processes (between threads), such cache invalidation often occurs and the performance in the system decreases. To do.

  For this reason, conventionally, a method for suppressing a delay in memory access has been proposed (see Patent Documents 1 and 2). In such a method, a process (thread) is executed on the same CPU as much as possible, thereby suppressing a memory access delay due to cache invalidation.

  Specifically, in the method disclosed in Patent Document 1, first, the access of each process to the common data stored in the cache is detected. Then, the address of the common data where the access is detected, the identification information of the process accessing the common data, and the number of accesses to the same data by the same process are recorded. Next, based on the stored information, processes having a large number of accesses to the same address are assigned to the same CPU.

  In the method disclosed in Patent Document 2, first, the memory access amount of the process, the memory access waiting time, and the like are acquired by the performance measurement unit provided in the CPU or other performance measurement unit by HW (Hard Wear). The Next, the CPU having the larger cache is assigned in order from the process having the larger access amount or access time.

JP 2002-55966 A JP 2003-06175 A

  By the way, in the method disclosed in Patent Document 1, processes with a higher access count are assigned to the same CPU, but actually, a process with a higher access count does not cause a cache invalidation process. Also, acquiring and storing the address of the common data where access has been detected is a burden on the CPU because the amount of data becomes enormous. For this reason, with the method disclosed in Patent Document 1, memory access delay suppression is insufficient, and system performance may be degraded.

  Further, in the method disclosed in Patent Document 2, the CPU cache efficiency is not taken into consideration, and therefore, a process group that accesses the same memory area may be assigned to different CPUs. In this case, since the number of cache invalidation processes increases conversely, even with the method disclosed in Patent Document 2, the delay of memory access is insufficient and the system performance may be degraded.

  An object of the present invention is to provide a process scheduling apparatus, a process scheduling method, and a program that can solve the above-described problems and suppress performance degradation in a multi-CPU system.

To achieve the above object, a process scheduling apparatus according to one aspect of the present invention is an apparatus for scheduling processes in a computer having a plurality of CPUs.
The contents of the cache of each of the plurality of CPUs for each process based on the information indicating the access status to the cache of each of the plurality of CPUs or the memory of the computer acquired for each process executed by the computer A cost calculator that calculates the cost of maintaining consistency
A grouping unit that divides each of the processes into groups based on the calculated cost for each of the processes;
And a scheduling unit that assigns each of the processes to any of the plurality of CPUs for each of the groups.

In order to achieve the above object, a process scheduling method according to one aspect of the present invention is a method for scheduling a process in a computer having a plurality of CPUs.
(A) Each of the plurality of CPUs for each of the processes based on information indicating an access status to the cache of each of the plurality of CPUs or the memory of the computer acquired for each process executed by the computer Calculating the cost to maintain the consistency of the cache contents of the
(B) dividing each of the processes into groups based on the cost for each of the processes calculated in the step of (a);
(C) assigning each of the processes to any one of the plurality of CPUs for each of the groups.

Furthermore, in order to achieve the above object, a program according to one aspect of the present invention is a program for causing a computer having a plurality of CPUs to perform process scheduling,
In the computer,
(A) Based on information indicating an access status to each of the plurality of CPUs or the memory of the computer acquired for each process to be executed, each of the previous plurality of CPUs for each process Calculating the cost of maintaining the consistency of the content, steps,
(B) dividing each of the processes into groups based on the cost for each of the processes calculated in the step of (a);
(C) allocating each of the processes to any of the plurality of CPUs for each of the groups.

  As described above, according to the present invention, it is possible to suppress the performance degradation in the multi-CPU system.

FIG. 1 is a block diagram showing a configuration of a process scheduling apparatus according to Embodiment 1 of the present invention. FIG. 2 is a diagram for explaining processing in the performance information acquisition unit provided in the computer shown in FIG. FIG. 3 is a flowchart showing the operation of the process scheduling apparatus according to Embodiment 1 of the present invention. FIG. 4 is a diagram showing an example of a process for which the maintenance cost is calculated in the first embodiment of the present invention. FIG. 5 is a diagram conceptually illustrating the scheduling process shown in FIG. FIG. 6 is a flowchart showing the operation of the process scheduling apparatus according to Embodiment 2 of the present invention. FIG. 7 is a diagram conceptually illustrating the cost calculation process in the second embodiment of the present invention. FIG. 8 is a diagram conceptually illustrating the scheduling process in the second embodiment of the present invention. FIG. 9 is a flowchart showing the operation of the process scheduling apparatus according to the third embodiment of the present invention. FIG. 10 is a diagram conceptually showing the information acquisition process in the third embodiment of the present invention. FIG. 11 is a diagram conceptually illustrating the scheduling process according to the third embodiment of the present invention. FIG. 12 is a diagram showing a schematic configuration of a conventional general multi-core CPU. FIG. 13 is a diagram for explaining an operation in a conventional multi-CPU system.

(Embodiment 1)
Hereinafter, a process scheduling apparatus, a process scheduling method, and a program according to Embodiment 1 of the present invention will be described with reference to FIGS.

[Device configuration]
First, the configuration of the process scheduling apparatus according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a process scheduling apparatus according to Embodiment 1 of the present invention.

  As shown in FIG. 1, a process scheduling apparatus 30 according to the first embodiment is an apparatus that executes process scheduling in a computer 100 having CPUs 10 and 11. In the first embodiment, the process scheduling apparatus 30 is constructed by a program described later on the operating system 20 installed in the computer 100.

  As shown in FIG. 1, in the first embodiment, the computer 100 further includes a memory 12 as a main storage device and a performance information acquisition unit 13 provided for each CPU. The performance information acquisition unit 13 acquires, for each process executed by the computer 100, information indicating the access status of the corresponding CPU to the cache or memory 12 (hereinafter referred to as “performance information”), and the acquired information. Is input to the process scheduling apparatus.

  Further, in the first embodiment, the CPUs 10 and 11 are multi-core CPUs shown in FIG. Moreover, although only two CPUs are illustrated in FIG. 1, in the first embodiment, the number of CPUs provided in the computer is not particularly limited.

  As shown in FIG. 1, the process scheduling apparatus 30 includes a cost calculation unit 31, a grouping unit 32, and a scheduling unit 33. Among these, the cost calculation unit 31 maintains consistency (cache coherency) of the contents of the respective caches of the CPUs 10 and 11 for each process based on the performance information acquired for each process by the performance information acquisition unit 13. Cost (hereinafter referred to as “maintenance cost”).

  The grouping unit 32 divides each process into groups based on the calculated maintenance cost for each process. Furthermore, the scheduling unit 33 assigns each process to one of the CPUs 10 and 11 for each group.

  Thus, in the first embodiment, the process scheduling apparatus 30 calculates a maintenance cost necessary for maintaining cache coherency for each process based on the actual access status of each CPU. Then, the CPU allocation of each process is based on the calculated maintenance cost, for example, processes having a high maintenance cost are collectively allocated to the same CPU, so that memory access delay is suppressed, and as a result, in the multi-CPU system Performance degradation is also suppressed.

  Here, the configuration of the process scheduling apparatus 30 according to the first embodiment will be described more specifically with reference to FIG. 2 in addition to FIG. FIG. 2 is a diagram for explaining processing in the performance information acquisition unit provided in the computer shown in FIG.

  First, in the first embodiment, the performance information acquisition unit 13 provided in the computer 100 acquires, as performance information, the number of times the corresponding CPU cache is invalidated for each process. For this reason, the cost calculation unit 31 calculates the maintenance cost based on the number of times each CPU's cache is invalidated (hereinafter referred to as “cache invalidation count”).

  That is, in the first embodiment, “cache invalidation count” is regarded as a maintenance cost for maintaining cache coherency and is acquired. Then, scheduling is performed so that the number of cache invalidations is reduced, thereby improving the system performance. This is because the process in which the cache invalidation occurs accesses the same memory area as the process executed on the other CPU, so that it causes the cache invalidation of the other CPU and the performance degradation. Because it is.

  When a plurality of CPUs access the same memory area and each CPU executes only read processing on the memory, cache invalidation does not occur. When one of the CPUs performs a write process on the memory, the cache of the other CPU is invalidated, resulting in performance degradation.

  Specifically, in the first embodiment, the performance information acquisition unit 13 accesses the data in the memory corresponding to the cache line in the M state of another CPU as “cache invalidation count”. Get the number of times. In other words, as shown in FIG. 2, this number of times corresponds to the number of times the changed cache is invalidated in another CPU.

  As shown in FIG. 2, the “M state” is a state defined by “MESI protocol” which is one of the protocols for maintaining cache coherence, and the cache line exists only in the cache. The state where the value on the main memory is changed.

As a specific example of the performance information acquisition unit 13, for example, if the CPU is an Intel CPU, a CPU performance counter (see Reference Document 1 below) may be mentioned. In this case, using the L3_CACHE_HIT_OTHER_CORE_HITM of the CPU performance counter “MSR_OFFCORE_RSP_0”, the number of accesses to the L3 cache line existing in the M state in the other CPU is obtained for each logical core.
Reference 1: "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2"

  Further, in the first embodiment, the cost calculation unit 31 is provided for each performance information acquisition unit (for each CPU), and each cost calculation unit 31 stores “for each process acquired by the performance information acquisition unit 13. The “cache invalidation count” is the maintenance cost. Furthermore, each cost calculation part 31 records the value of the maintenance cost obtained in this way in the cost recording part 34 for each process (see FIG. 4 of dictation). Patent Document 2 described above discloses a method of recording the value of the performance counter of the CPU for each process.

  In the first embodiment, the grouping unit 32 sets each process to a group of processes whose cache invalidation count exceeds a preset threshold and the cache invalidation count is equal to or less than a preset threshold. Can be divided into groups of processes. This is because when the cache invalidation count is small, the performance degradation can be ignored.

  In this case, the scheduling unit 33 assigns a group of processes whose cache invalidation count exceeds the threshold to the same CPU. As a result, processes that have a high possibility of accessing the same memory area can be combined into one, so that the occurrence of cache invalidation is reduced and performance degradation is suppressed.

[Device operation]
Next, the operation of the process scheduling apparatus according to the first embodiment will be described with reference to FIGS. FIG. 3 is a flowchart showing the operation of the process scheduling apparatus according to Embodiment 1 of the present invention. FIG. 4 is a diagram showing an example of a process for which the maintenance cost is calculated in the first embodiment of the present invention. FIG. 5 is a diagram conceptually illustrating the scheduling process shown in FIG.

  Furthermore, in the first embodiment, the process scheduling method is implemented by operating the process scheduling apparatus 30. Therefore, the description of the process scheduling method in the first embodiment is replaced with the following description of the operation of the process scheduling apparatus 30. In the following description, FIGS. 1 and 2 are referred to as appropriate.

Further, in the first embodiment, the process scheduling apparatus 30 cooperates with a scheduler provided in advance in the operating system 20 to create a migration thread (see Reference Document 2 below) in the Linux (registered trademark) OS. To work.
Reference 2: "Detailed Linux Kernel Third Edition", written by Daniel P. Bovet, Marco Cesati, directed by Hirokazu Takahashi, Yumiko Sugita, Masaaki Shimizu, Masanori Takasugi, Masatsugu Hiramatsu, Takahiro Yasui

  As shown in FIG. 3, first, each cost calculation unit 31 initializes and sets the maintenance cost of each process recorded in the cost recording unit 34 to 0 (zero) (step A1). Subsequently, each cost calculation unit 31 selects one of the CPUs 10 and 11 (step A2). However, if the steps A1 to A7 shown in FIG. 3 have already been executed before executing the current step A2, each cost calculation unit 31 selects a CPU that has not been selected in the previous process. .

  Next, each cost calculation unit 31 receives performance information for each process from the corresponding performance information acquisition unit 13, obtains the cache invalidation count (maintenance cost) for each process, and uses the obtained cache invalidation count as the maintenance cost. It records in the cost recording part 34 (step A3). When step A3 is executed, the maintenance cost for each process is specified as shown in FIG.

  Next, when step A3 is executed, the grouping unit 32 sorts the processes in the order of the maintenance cost recorded for each process (step A4). Next, when the sorting is completed, the grouping unit 32 determines whether the maintenance cost of any process exceeds the set threshold value T (step A5).

  In the first embodiment, the “threshold value T” that is the determination criterion in step A5 can be specified by the user according to the system configuration of the computer 10. For example, the user can specify the threshold T based on the number of accesses to the L3 cache line of the process acquired from the CPU performance counter “UNCORE_HIT + OTHER_CORE_HIT_SNP + OTHER_CORE_HITM”. A specific example of the threshold T is a value of 80% of the number of accesses. When the threshold value T is set to such a value, in a process whose maintenance cost exceeds the threshold value T, accesses exceeding 80% of all accesses to the L3 cache line are cache invalidated.

  As a result of the determination in step A5, when the maintenance cost of any process does not exceed the threshold value T (when the maintenance cost of all processes is equal to or less than the threshold value T), the process in the process scheduling device 30 is temporarily ended. This is because it is considered that there is no performance degradation due to cache invalidation.

  On the other hand, if the maintenance cost of any process exceeds the threshold T as a result of the determination in step A5, the grouping unit 32, as shown in FIG. (Natural number) is set in one group (step A6). The number of processes N when grouping into one group is not particularly limited, but can be set to, for example, the “number of cores” of the CPU.

  Next, the scheduling unit 33 assigns the process belonging to the group set in step A6 to the CPU selected in step A2 (step A7). This is because if the top N processes having a large maintenance cost value are operated by different CPUs, performance degradation due to cache invalidation is likely to occur.

  When step A7 is executed, N processes A to H having a high maintenance cost are assigned to the same CPU. As shown in FIG. 5, for example, the maintenance costs of the process B and the process C having a high maintenance cost are reduced by scheduling. In FIG. 5, only a part of the process shown in FIG. 4 is illustrated.

  And step A1-A7 is performed again after progress of fixed time. In this case, in step A2, a CPU different from the previously selected CPU is selected as described above, and scheduling is executed. That is, the CPU to be selected is selected by the round robin method. In this way, by repeating steps A1 to A7, the maintenance cost is reduced in the computer 100 as a whole, and the decrease in performance is suppressed.

[Effect of Embodiment 1]
As described above, according to the first embodiment, scheduling is performed so that processes having a large number of cache invalidations are executed by the same CPU. Accordingly, a plurality of processes that acquire the same lock when operated on different CPUs, and a plurality of processes that access a shared memory area between processes / threads are executed by the same CPU. As a result, the number of cache invalidations decreases in each process, so that the memory access delay is reduced and the performance in the multi-CPU system is improved.

  In addition, a process with a large number of cache invalidations causes cache invalidation due to cache contention with other processes, which causes performance degradation. Since the user can specify the process causing the cache contention by using the calculation result of the maintenance cost, the CPU allocation can be manually set at the time of scheduling and the program structure can be improved.

[program]
Moreover, the program in this Embodiment 1 should just be a program which makes the computer 100 perform step A1-A7 shown in FIG. By installing and executing this program on a computer, the process scheduling apparatus and the process scheduling method according to the first embodiment can be realized. In this case, the CPUs 10 and 11 of the computer function as the cost calculation unit 31, the grouping unit 32, and the scheduling unit 33 to perform processing. Further, a storage device such as a hard disk or a memory provided in the computer functions as the cost recording unit 34.

  Further, the program according to the first embodiment may be provided in a state stored in a computer-readable recording medium, or may be distributed via a network such as the Internet. Specific examples of the recording medium include general-purpose semiconductor storage devices such as CF (Compact Flash (registered trademark)) and SD (Secure Digital), magnetic storage media such as a flexible disk, or CD-ROM (Compact Optical storage media such as Disk Read Only Memory).

(Embodiment 2)
Next, a process scheduling apparatus, a process scheduling method, and a program according to Embodiment 2 of the present invention will be described with reference to FIGS. In the following description, FIG. 1 will be referred to as appropriate.

  The process scheduling apparatus according to the second embodiment has the same configuration as that of the process scheduling apparatus 10 according to the first embodiment shown in FIG. However, in the second embodiment, the cost calculation unit 31 calculates the number of cache invalidations while each process is executing the shared area access processing for each process based on the number of cache invalidations of each CPU. The calculated cache invalidation count is used as the maintenance cost.

  That is, in the second embodiment, scheduling is executed so that a process having a high maintenance cost during shared area access processing is executed by the same CPU. The “shared area access process” generally includes a lock process, an access process to a shared memory, and the like. Furthermore, the shared area access process may be defined by the user. In this case, the user defines any process that may cause a memory contention between processes as a shared area access process during programming. To do. The shared area access process may be a lock process extracted from an existing program.

  Here, the operation of the process scheduling apparatus according to the second embodiment will be described with reference to FIGS. FIG. 6 is a flowchart showing the operation of the process scheduling apparatus according to Embodiment 2 of the present invention. FIG. 7 is a diagram conceptually illustrating the cost calculation process in the second embodiment of the present invention. FIG. 8 is a diagram conceptually illustrating the scheduling process in the second embodiment of the present invention.

  In the second embodiment, the process scheduling method is also implemented by operating the process scheduling apparatus. Therefore, the description of the process scheduling method in the second embodiment is also replaced with the following description of the operation of the process scheduling apparatus.

  First, in the second embodiment, as a premise, each cost calculation unit 31 always receives the cache invalidation count as performance information for each process from the corresponding performance information acquisition unit 13 and records this in the cost recording unit 34. Suppose you are. The recorded number of cache invalidations is used to calculate the maintenance cost.

  Subsequently, as illustrated in FIG. 6, each cost calculation unit 31 determines whether any process has executed the shared area access processing in the corresponding CPU (step B <b> 1). As a result of the determination in step B1, if no process is executing the shared area access processing, each cost calculation unit 31 enters a standby state, and executes step B1 again after the set time has elapsed.

  On the other hand, as a result of the determination in step B1, when any process executes the shared area access process, each cost calculation unit 31 identifies the process that executed the shared area access process (step B2).

  Next, each cost calculation unit 31 acquires the number of cache invalidations before and after the shared area access process from the cost recording unit 34 for the identified process. Then, as shown in FIG. 7, each cost calculation unit 31 calculates the difference between them, that is, the number of cache invalidations during execution of the shared area access process, and uses the calculated difference as the maintenance cost (step B3). . Each cost calculation unit 31 records the calculated maintenance cost in the cost recording unit 34.

  Next, the grouping unit 32 determines whether or not the maintenance cost calculated in Step B3 exceeds the set threshold value T (Step B4). The threshold value T is set in the same manner as in step A5 shown in FIG.

  As a result of the determination in step B4, when the maintenance cost does not exceed the threshold T, the process in the process scheduling device 30 is temporarily ended. On the other hand, as a result of the determination in step B4, if the maintenance cost exceeds the threshold T, the grouping unit 32 sets the processes whose maintenance cost exceeds the threshold T as one group (step B5).

  Next, the scheduling unit 33 selects an arbitrary CPU and assigns a process belonging to the group set in step B5 to the selected CPU (step B6). When step B6 is executed, steps B1 to B6 are executed again. As described above, in the second embodiment, scheduling is executed every time each process executes the shared area access processing. The CPU to be selected is selected by the round robin method.

  Specifically, as shown in FIG. 8, the process A that executes the shared area access processing 1 was scheduled to be executed by the CPU 10, but is assigned to the CPU 11 by the execution of step B6. If a process whose maintenance cost exceeds the threshold is operated by a separate CPU, performance degradation due to cache invalidation is likely to occur. However, since all processes that execute the shared area access processing 1 are executed by the CPU 11, multiple processes are executed. Performance degradation in the CPU system is suppressed.

  Moreover, the program in this Embodiment 2 should just be a program which makes the computer 100 perform step B1-B6 shown in FIG. By installing and executing this program on a computer, the process scheduling apparatus and the process scheduling method according to the second embodiment can be realized. In this case, the CPUs 10 and 11 of the computer function as the cost calculation unit 31, the grouping unit 32, and the scheduling unit 33 to perform processing. Further, a storage device such as a hard disk or a memory provided in the computer functions as the cost recording unit 34.

  Further, the program in the second embodiment may be provided in a state of being stored in a computer-readable recording medium as in the first embodiment, or distributed through a network such as the Internet. There may be.

(Embodiment 3)
Next, a process scheduling apparatus, a process scheduling method, and a program according to Embodiment 3 of the present invention will be described with reference to FIGS. In the following description, FIG. 1 will be referred to as appropriate.

  The process scheduling apparatus according to the third embodiment has the same configuration as that of the process scheduling apparatus 10 according to the first embodiment shown in FIG. However, in the third embodiment, in the computer 100, a plurality of non-uniform memory access (NUMA) nodes are set by each CPU and a memory provided in the computer. In the third embodiment, a plurality of memories 12 may be provided. In addition, the performance information acquisition unit 13 acquires, as performance information, whether each process has performed a write process on the memory 12.

  In the third embodiment, each cost calculation unit 31 counts the number of times each process has executed write processing to the memory 12 based on the performance information for each NUMA node, and for each NUMA node for each process. The total number of times the memory is accessed is taken as the maintenance cost. Then, the grouping unit 32 identifies the NUMA node having the highest number of accesses to the memory 12 for each process, and sets the processes having the same identified NUMA node as one group.

  Here, the operation of the process scheduling apparatus according to the third embodiment will be described with reference to FIGS. FIG. 9 is a flowchart showing the operation of the process scheduling apparatus according to the third embodiment of the present invention. FIG. 10 is a diagram conceptually showing the information acquisition process in the third embodiment of the present invention. FIG. 11 is a diagram conceptually illustrating the scheduling process according to the third embodiment of the present invention.

  In the third embodiment, the process scheduling method is also implemented by operating the process scheduling apparatus. Therefore, the description of the process scheduling method in the third embodiment is also replaced with the following description of the operation of the process scheduling apparatus.

  First, in the third embodiment, as a premise, as shown in FIG. 10, when the process executes the write process to the memory, the performance information acquisition unit 13 acquires the page where the write is performed, and sets the corresponding bit. It is set to 1, and this is notified to the corresponding cost calculation unit 31. Each cost calculation unit 31 holds a counter corresponding to the NUMA node. When the performance information acquisition unit 13 changes the bit from 0 to 1, the counter of the NUMA node to which the written page belongs is stored. Increment.

  Subsequently, as shown in FIG. 9, each cost calculation unit 31 counts the counters of the NUMA nodes for each set time, and the counter value for each NUMA node for each process (to the memory for each process NUMA node) The number of times of writing) is recorded in the cost recording unit 34 as a maintenance cost (step C1).

  Next, the grouping unit 32 specifies the NUMA node having the maximum maintenance cost (counter value) for each process based on the maintenance cost (step C2). Then, as illustrated in FIG. 11, the grouping unit 32 groups the processes so that the processes having the same NUMA node are included in one group (step C3).

  After that, as shown in FIG. 11, the grouping unit 32 assigns each process to each CPU for each group so that each group is assigned to a different CPU (step C4). As a result, processes having a high possibility of executing a write process on the same memory area are allocated to the same CPU, so that the cache efficiency is improved, and as a result, the performance of the multi-CPU system is also improved.

  Moreover, the program in this Embodiment 3 should just be a program which makes the computer 100 perform step C1-C4 shown in FIG. By installing and executing this program on a computer, the process scheduling apparatus and the process scheduling method according to the third embodiment can be realized. In this case, the CPUs 10 and 11 of the computer function as the cost calculation unit 31, the grouping unit 32, and the scheduling unit 33 to perform processing. Further, a storage device such as a hard disk or a memory provided in the computer functions as the cost recording unit 34.

  Also, the program in the third embodiment may be provided in a state of being stored in a computer-readable recording medium as in the first embodiment, or distributed through a network such as the Internet. May be.

  Part or all of the above-described embodiment can be expressed by (Appendix 1) to (Appendix 15) described below, but is not limited to the following description.

(Appendix 1)
An apparatus for scheduling processes in a computer having a plurality of CPUs,
The contents of the cache of each of the plurality of CPUs for each process based on the information indicating the access status to the cache of each of the plurality of CPUs or the memory of the computer acquired for each process executed by the computer A cost calculator that calculates the cost of maintaining consistency
A grouping unit that divides each of the processes into groups based on the calculated cost for each of the processes;
A scheduling unit that assigns each of the processes to any of the plurality of CPUs for each of the groups;
A process scheduling apparatus comprising:

(Appendix 2)
As the information, for each process, the number of times each cache of the plurality of CPUs is invalidated is acquired,
The cost calculation unit calculates the cost based on the number of times the acquired caches of the plurality of CPUs are invalidated;
The process scheduling apparatus according to appendix 1.

(Appendix 3)
The grouping unit divides each of the processes into a group of processes in which the number of times exceeds a preset threshold and a group of processes in which the number of times is equal to or less than a preset threshold.
The process scheduling apparatus according to attachment 2.

(Appendix 4)
The cost calculation unit calculates the number of times during which the process is executing shared area access processing for each process based on the number of times the acquired caches of the plurality of CPUs are invalidated. The calculated number of times is the cost.
The process scheduling apparatus according to attachment 2.

(Appendix 5)
In the computer, a plurality of nodes are set by each of the plurality of CPUs and a memory provided in the computer.
As the information, for each process, whether or not the process has executed write processing on the memory is acquired,
Based on the information, the cost calculation unit accessed the memory by counting the number of times each process executed a write process to the memory for each node and totaling for each node for each process. The number of times is the cost,
For each process, the grouping unit identifies a node having the highest number of accesses to the memory, and processes in which the identified nodes are the same are grouped together.
The process scheduling apparatus according to appendix 1.

(Appendix 6)
A method for scheduling a process in a computer having a plurality of CPUs, comprising:
(A) Each of the plurality of CPUs for each of the processes based on information indicating an access status to the cache of each of the plurality of CPUs or the memory of the computer acquired for each process executed by the computer Calculating the cost to maintain the consistency of the cache contents of the
(B) dividing each of the processes into groups based on the cost for each of the processes calculated in the step of (a);
(C) assigning each of the processes to any of the plurality of CPUs for each of the groups;
A process scheduling method comprising:

(Appendix 7)
As the information, for each process, the number of times each cache of the plurality of CPUs is invalidated is acquired,
In the step (a), the cost is calculated based on the number of times the acquired caches of the plurality of CPUs are invalidated.
The process scheduling method according to attachment 6.

(Appendix 8)
In the step (b), each of the processes is divided into a group of processes in which the number of times exceeds a preset threshold and a group of processes in which the number of times is less than or equal to a preset threshold.
The process scheduling method according to appendix 7.

(Appendix 9)
In the step (a), based on the number of times the acquired caches of the plurality of CPUs are invalidated, for each process, the number of times during which the process is executing shared area access processing is calculated. Calculate the number of times calculated as the cost,
The process scheduling method according to appendix 7.

(Appendix 10)
In the computer, a plurality of nodes are set by each of the plurality of CPUs and a memory provided in the computer.
As the information, for each process, whether or not the process has executed write processing on the memory is acquired,
In the step (a), based on the information, the number of times each of the processes has performed write processing on the memory is totaled for each node, and the memory is totaled for each node for each process. The number of accesses is the cost,
In the step (b), for each process, a node having the highest number of accesses to the memory is specified, and processes having the same specified node are grouped into one group.
The process scheduling method according to attachment 6.

(Appendix 11)
A program for causing a computer having a plurality of CPUs to perform process scheduling,
In the computer,
(A) Based on information indicating an access status to each of the plurality of CPUs or the memory of the computer acquired for each process to be executed, each of the previous plurality of CPUs for each process Calculating the cost of maintaining the consistency of the content, steps,
(B) dividing each of the processes into groups based on the cost for each of the processes calculated in the step of (a);
(C) assigning each of the processes to any of the plurality of CPUs for each of the groups;
A program that executes

(Appendix 12)
As the information, for each process, the number of times each cache of the plurality of CPUs is invalidated is acquired,
In the step (a), the cost is calculated based on the number of times the acquired caches of the plurality of CPUs are invalidated.
The program according to appendix 11.

(Appendix 13)
In the step (b), each of the processes is divided into a group of processes in which the number of times exceeds a preset threshold and a group of processes in which the number of times is less than or equal to a preset threshold.
The program according to attachment 12.

(Appendix 14)
In the step (a), based on the number of times the acquired caches of the plurality of CPUs are invalidated, for each process, the number of times during which the process is executing shared area access processing is calculated. Calculate the number of times calculated as the cost,
The program according to attachment 12.

(Appendix 15)
In the computer, a plurality of nodes are set by each of the plurality of CPUs and a memory provided in the computer.
As the information, for each process, whether or not the process has executed write processing on the memory is acquired,
In the step (a), based on the information, the number of times each of the processes has performed write processing on the memory is totaled for each node, and the memory is totaled for each node for each process. The number of accesses is the cost,
In the step (b), for each process, a node having the highest number of accesses to the memory is specified, and processes having the same specified node are grouped into one group.
The program according to appendix 11.

  According to the present invention, it is possible to suppress performance degradation in a multi-CPU system. The present invention is useful for a server computer or the like equipped with a multi-CPU system.

10, 11 CPU
DESCRIPTION OF SYMBOLS 12 Main memory 13 Performance information acquisition part 20 Operating system 30 Process scheduling apparatus 31 Cost calculation part 32 Grouping part 33 Scheduling part 34 Cost recording part 100 Computer

Claims (7)

An apparatus for scheduling processes in a computer having a plurality of CPUs,
The contents of the cache of each of the plurality of CPUs for each process based on the information indicating the access status to the cache of each of the plurality of CPUs or the memory of the computer acquired for each process executed by the computer A cost calculator that calculates the cost of maintaining consistency
A grouping unit that divides each of the processes into groups based on the calculated cost for each of the processes;
A scheduling unit that assigns each of the processes to any of the plurality of CPUs for each of the groups;
A process scheduling apparatus comprising: As the information, for each process, the number of times each cache of the plurality of CPUs is invalidated is acquired,
The cost calculation unit calculates the cost based on the number of times the acquired caches of the plurality of CPUs are invalidated;
The process scheduling apparatus according to claim 1. The grouping unit divides each of the processes into a group of processes in which the number of times exceeds a preset threshold and a group of processes in which the number of times is equal to or less than a preset threshold.
The process scheduling apparatus according to claim 2. The cost calculation unit calculates the number of times during which the process is executing shared area access processing for each process based on the number of times the acquired caches of the plurality of CPUs are invalidated. The calculated number of times is the cost.
The process scheduling apparatus according to claim 2. In the computer, a plurality of nodes are set by each of the plurality of CPUs and a memory provided in the computer.
As the information, for each process, whether or not the process has executed write processing on the memory is acquired,
Based on the information, the cost calculation unit accessed the memory by counting the number of times each process executed a write process to the memory for each node and totaling for each node for each process. The number of times is the cost,
For each process, the grouping unit identifies a node having the highest number of accesses to the memory, and processes in which the identified nodes are the same are grouped together.
The process scheduling apparatus according to claim 1. A method for scheduling a process in a computer having a plurality of CPUs, comprising:
(A) Each of the plurality of CPUs for each of the processes based on information indicating an access status to the cache of each of the plurality of CPUs or the memory of the computer acquired for each process executed by the computer Calculating the cost to maintain the consistency of the cache contents of the
(B) dividing each of the processes into groups based on the cost for each of the processes calculated in the step of (a);
(C) assigning each of the processes to any of the plurality of CPUs for each of the groups;
A process scheduling method comprising: A program for causing a computer having a plurality of CPUs to perform process scheduling,
In the computer,
(A) Based on information indicating an access status to each of the plurality of CPUs or the memory of the computer acquired for each process to be executed, each of the previous plurality of CPUs for each process Calculating the cost of maintaining the consistency of the content, steps,
(B) dividing each of the processes into groups based on the cost for each of the processes calculated in the step of (a);
(C) assigning each of the processes to any of the plurality of CPUs for each of the groups;
A program that executes

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