JP2013200692A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system which can, for example, appropriately process commands that are respectively stored in a plurality of command queues having different priorities in one embodiment.SOLUTION: In one embodiment, a memory system includes a nonvolatile semiconductor memory and a control unit. If a second command is stored in a second command queue when a first command that is stored in a first command queue is being executed, a processing unit of the control unit performs one of interruption processing and completion processing according to the progress status of access to the nonvolatile semiconductor memory by the first command at a timing when the second command is stored in the second command queue. In the interruption processing, the execution of the first command is interrupted and the second command is executed. In the completion processing, the execution of the first command is completed.

Description

  Embodiments described herein relate generally to a memory system.

  As a memory system used in a computer system, an SSD (Solid State Drive) equipped with a nonvolatile semiconductor memory such as a NAND flash memory has attracted attention. Some memory systems such as SSDs have a plurality of command queues having different priorities. At this time, it is desirable to appropriately process commands stored in a plurality of command queues having different priorities.

JP 2010-282422 A

  An object of one embodiment is to provide a memory system that can appropriately process, for example, commands stored in a plurality of command queues having different priorities.

  According to one embodiment, a memory system having a nonvolatile semiconductor memory and a control unit is provided. The control unit controls the nonvolatile semiconductor memory. The control unit includes a first command queue, a second command queue, and a processing unit. The second command queue has a higher priority than the first command queue. The processing unit selects one of the first command queue and the second command queue. The processing unit executes a command stored in the selected command queue and performs an access process to the nonvolatile semiconductor memory. When the second command is stored in the second command queue during execution of the first command stored in the first command queue, the processing unit stores the second command in the second command queue. Depending on the progress of access to the nonvolatile semiconductor memory by the first command at the specified timing, either the interruption process or the completion process is performed. In the interruption process, the execution of the first command is interrupted and the second command is executed. In the completion process, the execution of the first command is completed.

1 is a diagram showing a configuration of a memory system according to an embodiment. The figure which shows the structure of the NAND type flash memory in embodiment. The figure which shows the structure of the NAND controller in embodiment. 5 is a flowchart showing the operation of the memory system according to the embodiment. FIG. 3 is a diagram illustrating an operation of the memory system according to the embodiment. FIG. 3 is a diagram illustrating an operation of the memory system according to the embodiment. FIG. 3 is a diagram illustrating an operation of the memory system according to the embodiment. FIG. 3 is a diagram illustrating an operation of the memory system according to the embodiment. FIG. 3 is a diagram illustrating an operation of the memory system according to the embodiment. FIG. 3 is a diagram illustrating an operation of the memory system according to the embodiment.

  Hereinafter, a memory system according to an embodiment will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

(Embodiment)
A memory system 100 according to an embodiment will be described with reference to FIG. FIG. 1 is a diagram showing a configuration of the memory system 100.

  The memory system 100 functions as an external storage medium for the host device HA, and is, for example, an SSD (Solid State Drive) or a memory card. The host device HA includes, for example, a personal computer or a CPU core.

  The memory system 100 includes a drive control circuit 4 as a controller, a NAND flash memory 10 as a nonvolatile semiconductor memory, a RAM 20 as a randomly accessible semiconductor memory, and a memory such as an ATA interface (ATA I / F) 2. A connection interface is provided.

  For example, a volatile semiconductor memory is employed as the RAM 20. As the RAM 20, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), FeRAM (Ferroelectric Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Resistive Memory). . The RAM 20 is used as a storage unit for data transfer, management information recording, or work area.

  The drive control circuit 4 controls data transfer between the host HA and the NAND flash memory 10 via the RAM 20 and controls each component in the memory system 100.

  The drive control circuit 4 includes a data access bus 101 and a circuit control bus 102. A processor 104 that controls the entire drive control circuit 4 is connected to the circuit control bus 102. A boot ROM 105 storing a boot program for booting each management program (FW: firmware) stored in the NAND flash memory 10 is connected to the circuit control bus 102 via a ROM controller 106.

  The ATA interface controller (ATA controller) 117, the NAND controller 110, and the RAM controller 114 are connected to both the data access bus 101 and the circuit control bus 102. The ATA controller 117 transmits and receives data to and from the host HA via the ATA interface 2. An SRAM 115 used as a data work area and a firmware development area is connected to the data access bus 101 via an SRAM controller 116. The firmware stored in the NAND flash memory 10 is transferred to the SRAM 115 by a boot program stored in the boot ROM 105 at startup. The processor 104 operates as the uppermost controller in the memory system 100 by executing the firmware transferred to the SRAM 115 and controls the components in the drive control circuit 4.

  The RAM controller 114 executes interface processing between the processor 104 and the RAM 20, data transfer control between the ATA I / F 2 and RAM 20, data transfer control between the NAND flash memory 10 and RAM 20, and the like. The NAND controller 110 executes interface processing between the processor 104 and the NAND flash memory 10, data transfer control between the NAND flash memory 10 and the RAM 20, error correction code encoding / decoding processing, and the like.

The NAND flash memory 10 stores write data from the host device 100, and stores backup data and difference data of an address conversion table loaded in a work area (not shown). The NAND flash memory 10 is composed of one or more memory chips. When the NAND flash memory 10 is composed of a plurality of memory chips, high speed operation can be realized by driving the plurality of memory chips in parallel. The NAND flash memory 10 may be a binary memory (SLC: Single Level Cell) that stores 1 bit in one memory cell, or a multi-level memory (MLC) that stores 2 bits or more in one memory cell. : Multi Level Cell). Hereinafter, the NAND memory 2 will be described as a multi-value memory.
Next, the NAND flash memory 10 will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of the NAND flash memory 10.

The NAND flash memory 10 includes a control circuit 15, a memory cell array 11, a page buffer 12, a data cache 13, and a status register 14.
The control circuit 15 controls each part of the NAND flash memory 10 as a whole.

  When the memory cell array 11 is a multi-value memory, for example, a plurality of memory cells are arranged in a matrix, and each memory cell can be stored in multi-value using an upper page and a lower page. is there. The memory cell array 11 includes a plurality of physical blocks that are units of erasure, and each physical block includes a plurality of physical pages (hereinafter simply referred to as pages) that are units of reading and writing. In addition, since each memory cell holds the data in a nonvolatile manner until the data is erased once it is written, it is difficult to further overwrite the data.

  The data cache 13 and the page buffer 12 have a storage capacity for one page, for example. The data cache 13 is used as a buffer for the NAND flash memory 10 to transmit / receive data to / from the NAND controller 110, and the page buffer 12 is used for the NAND flash memory 10 to input / output data to / from the memory cell array 11. Used as a buffer.

  Specifically, when a write command is executed, the control circuit 15 clears the data stored in the data cache 13 and stores the write data in the data cache 13 when write data is sent from the NAND controller 110. The control circuit 15 further copies the write data stored in the data cache 13 to the page buffer 12. Then, the control circuit 15 programs the write data stored in the page buffer 12 in the memory cell array 11. At the time of programming, the control circuit 15 compares the programmed write data with the write data stored in the page buffer 12 to verify whether or not the program is correctly programmed.

  At the time of a read command, the control circuit 15 reads target data from the memory cell array 11 to the page buffer 12. The control circuit 15 clears the data stored in the data cache 13 and then copies the read data stored in the page buffer 12 to the data cache 13. The control circuit 15 sends the read data stored in the data cache 13 to the NAND controller 110 by a data output signal (for example, RE signal).

  The status register 14 stores status information generated by the control circuit 15. The status information stored in the status register 14 is sent to the NAND controller 110 under the control of the control circuit 15.

  Specifically, the control circuit 15 receives a status read command (Cmd70-StatusOut) from the NAND controller 110 when a write command is executed or an erase command is executed. When receiving the status read command, the control circuit 15 outputs the status information stored in the status register 14 to the NAND controller 110.

  For example, when the write command is executed, the control circuit 15 receives the status read command (Cmd70-StatusOut) after the write command (Cmd80h-Adr-DataIn-Cmd10h) related to the write data, and the write data is stored in the data cache 13. If it is, status information is output as to whether or not the programming related to the write data is successful.

  Note that when the write data stored in the data cache 13 is cleared, the control circuit 15 also clears the status information related to the write data from the status register 14 accordingly. Therefore, it is difficult for the control circuit 15 to output status information related to the write data when the write data is not stored in the data cache 13.

For example, when executing the erase command, the control circuit 15 succeeds in erasing the erase command as status information when receiving a status read command (Cmd70-StatusOut) after the erase command (Cmd60h-Adr-CmdD0h) related to the erase command. Output whether or not.
Next, the NAND controller 110 will be described with reference to FIG. FIG. 3 is a diagram illustrating a configuration of the NAND controller 110.

  In the memory system 100, commands having different priorities may be requested at different timings. This priority is, for example, a priority related to the execution order in relation to other commands during command execution. Considering this point, the NAND controller 110 has two command queues having different priorities, and an event in which a command is set in a command queue having a higher priority, a command queue having a higher priority from a command queue having a lower priority. It has a mechanism to determine whether or not to switch to.

  Specifically, the NAND controller 110 includes a low-priority command queue (first command queue) 111, a high-priority command queue (second command queue) 112, and a processing unit 113.

  The low priority command queue 111 has a lower priority than the high priority command queue 112. That is, in the command queue 111 with low priority, commands with lower priority than the commands stored in the command queue 112 with high priority are stored in the command execution order. The low priority command queue 111 can store a plurality of commands, for example. The low-priority command queue 111 has, for example, a FIFO (First In First Out) structure, and moves a plurality of commands from the input position 111a to the execution position 111b (see FIG. 5A) in the stored order. .

  The high priority command queue 112 has a higher priority than the low priority command queue 111. That is, in the command queue 112 with high priority, commands having higher priority than commands stored in the command queue 111 with low priority are stored in the command execution order. The high priority command queue 112 can store one or more commands, for example. In the following, for simplification of description, a case where the command queue 112 with high priority stores one command will be described as an example. However, the following idea is based on the fact that the command queue 112 with high priority has a plurality of commands. It can be similarly applied to the case where it is possible to store.

  The processing unit 113 selects one of the command queues 111 having a low priority and the command queue 112 having a high priority, and executes a command stored in the selected command queue so that the NAND flash memory 10 can receive the command queue. Perform access processing.

  For example, if no command is stored in the command queue 112 with a high priority, the processing unit 113 selects the command queue 111 with a low priority, and the command stored in the execution position 111b in the command queue 111 with a low priority. Is executed. For example, if the write command WR0 is stored in the execution position 111b in the low priority command queue 111 (see FIG. 5A), the processing unit 113 causes the write command WR0 to be executed.

  For example, when a command is stored in the command queue 112 with a high priority when no command is stored in the command queue 111 with a low priority, the processing unit 113 selects the command queue 112 with a high priority, The command stored in the command queue 112 having a high priority is executed. For example, if the write command WR2 is stored in the high priority command queue 112 (see FIG. 5A), the processing unit 113 executes the write command WR2.

  On the other hand, when one or more commands are stored in the low priority command queue 111 and the command stored in the execution position 111b is being executed, the command is stored in the high priority command queue 112. It becomes.

  Here, it is assumed that the processing unit 113 always completes the command processing of the command queue 111 with the low priority and then processes the command of the command queue 112 with the high priority. In this case, there is a tendency that the latency (time to command response) to a command with a higher priority becomes longer by the time waiting for the completion of processing of a command with a lower priority.

Therefore, in the embodiment, when the processing unit 113 stores the second command in the high priority command queue 112 while the first command stored in the low priority command queue 111 is being executed, Depending on the progress of access to the NAND flash memory 10 by the first command at the timing when the command is stored in the command queue 112 having a high priority, either the interruption process or the completion process is performed. The interruption process is a process for interrupting the execution of the first command and executing the second command. The completion process is a process for completing the execution of the first command. That is, the processing of the first command in the low priority command queue 111 is not necessarily completed, but the first command is completed in consideration of the progress of access to the NAND flash memory 10 by the first command. Control to switch between being interrupted and interrupted.
Specifically, the processing unit 113 includes a queue switching unit 113a and a command sequence issuing unit 113b.

  The queue switching unit 113a monitors the commands stored in the low-priority command queue 111 and the high-priority command queue 112, and before the command sequence issuance by the command sequence issuance unit 113b, Depending on the storage status, one of the command queues 111 having a low priority and the command queue 112 having a high priority is selected, and the contents of the command stored in the selected command queue are sent to the command sequence issuing unit 113b. Notice.

  When the command sequence issuing unit 113b receives notification of the contents of the command to be executed from the queue switching unit 113a, the command sequence issuing unit 113b issues a command sequence according to the content of the command to be executed. The command sequence issuing unit 113b performs an access process for generating instructions and data to be supplied to the NAND flash memory 10 and supplying them to the NAND flash memory 10 according to the issued command sequence. Further, the command sequence issuing unit 113b notifies the queue switching unit 113a that the command sequence has been issued.

  On the other hand, after issuing the command sequence by the command sequence issuing unit 113b, the queue switching unit 113a stores the second priority in the high priority command queue 112 during execution of the first command stored in the low priority command queue 111, for example. When the command is stored, the command sequence issuing unit 113b is inquired about the progress of the access to the NAND flash memory 10 by the first command at the timing when the second command is stored in the command queue 112 having a high priority.

  The command sequence issuing unit 113b determines the access progress status in response to the inquiry. That is, the command sequence issuing unit 113b receives Busy signals from the NAND flash memory 10 one by one after the command sequence is issued. The command sequence issuing unit 113b determines the access progress status according to whether the value of the Busy signal is “Ready” or “Busy”.

  For example, if the value of the Busy signal is “Ready” before issuing “Busy” after the command sequence issuance, the command sequence issuing unit 113b determines that the access progress status is before the start of the busy state (for example, “NANDBusy” shown in FIG. It is determined that “before”).

  For example, if the value of the Busy signal is “Busy”, the command sequence issuing unit 113b determines that the access progress status is busy (for example, “NAND Busy” shown in FIG. 10).

For example, if the value of the Busy signal is “Ready” after becoming “Busy” after issuance of the command sequence, the command sequence issuing unit 113b determines that the access progress status is after the busy state expires (for example, “ After NAND Busy ”).
The command sequence issuing unit 113b notifies the queue switching unit 113a of the determined access progress status.

  When receiving the notification of the access progress status, the queue switching unit 113a performs either an interruption process or a completion process for the first command being executed according to the access progress status.

  That is, when performing the interruption process, the queue switching unit 113a interrupts the first command by switching from the state in which the low priority command queue 111 is selected to the state in which the high priority command queue 112 is selected. The second command is executed. At this time, the queue switching unit 113a may hold a suspension state flag indicating that the first command is suspended.

  Alternatively, when performing the completion process, the queue switching unit 113a maintains the state in which the low-priority command queue 111 is selected, thereby completing the execution of the first command. Then, the queue switching unit 113a starts executing the second command after the execution of the first command is completed by the completion process. For example, when the queue switching unit 113a receives a notification from the command sequence issuing unit 113b that the execution of the first command has been completed, the queue switching unit 113a changes the command queue 112 with the high priority from the state where the command queue 111 with the low priority is selected. By switching to the selected state, execution of the second command is started.

  Furthermore, for example, the queue switching unit 113a performs either the interruption process or the completion process depending on the progress of access to the NAND flash memory 10 associated with the execution of the first command and the type of the first command. I do. For example, the queue switching unit 113a performs an interruption process in response to the first command being an erase command or a read command, and performs a completion process in response to the first command being a write command.

  More specifically, the queue switching unit 113a determines that the first command is a write command and that the progress of access to the NAND flash memory 10 is before the start of the busy state of the NAND flash memory 10. , Interrupt processing. In addition, the queue switching unit 113a performs the completion process in response to the first command being a write command and the progress of access to the NAND flash memory 10 being after the busy state of the NAND flash memory 10 is started. Do.

  Alternatively, suppose that the processing unit 113 forcibly discards the command processing in the low priority command queue 111 and then processes the command in the high priority command queue 112 when performing the interruption processing. Think about when to do. In this case, since the processing of commands in the command queue 111 with low priority is forcibly discarded, the throughput of commands in the command queue 111 with low priority tends to decrease.

  In this regard, in the embodiment, after the execution of the first command is interrupted by the interruption process and the execution of the second command is completed, the processing unit 113 performs the NAND flash memory according to the first command at the interruption timing. Depending on the progress status of access to 10, either continuation processing or retry processing is performed. The continuation process is a process that continues the execution of the first command from the process at the time of interruption. The retry process is a process that causes the first command to be executed again from the first process.

  For example, after the execution of the first command is interrupted by the interruption process and the execution of the second command is completed, the queue switching unit 113a selects the command queue having the low priority from the state where the command queue 112 having the high priority is selected. By switching 111 to the selected state, the command sequence issuing unit 113b is notified that the execution of the interrupted first command should be executed.

  In response to this, the command sequence issuing unit 113b determines the progress of access to the NAND flash memory 10 at the timing when the execution of the first command is interrupted by the interruption process. At this time, the command sequence issuing unit 113b may use, for example, the access progress status used when the interruption process is performed as the determined access progress status. For example, the command sequence issuing unit 113b issues a command sequence of the first command from the beginning in response to the progress of access to the NAND flash memory 10 before the busy state of the NAND flash memory 10 expires. As a result, a retry process is performed to restart the execution of the first command from the first process. Alternatively, for example, the command sequence issuance unit 113b interrupts the command sequence of the first command when the access progress status to the NAND flash memory 10 is after the busy state of the NAND flash memory 10 has expired. By issuing the command, the continuation process for continuing the execution of the first command from the process at the time of interruption is performed.

  Further, for example, the command sequence issuance unit 113b determines the progress of access to the NAND flash memory 10 by the first command at the interrupted timing, and the combination of the first command type and the second command type. In response, either continuation processing or retry processing is performed. For example, the command sequence issuance unit 113b performs continuation processing in response to the combination of the first command type and the second command type including an erase command and a read command, and performs the first command type and the first command type. Retry processing is performed in response to the combination of the two command types not including the erase command and the read command.

  More specifically, the command sequence issuing unit 113b indicates that the combination of the first command type and the second command type includes an erase command and a read command, and the access progress status to the NAND flash memory 10 is NAND. In response to the fact that the busy state of the type flash memory 10 has not expired, a retry process is performed. The command sequence issuing unit 113b includes a combination of the first command type and the second command type that includes an erase command and a read command, and the access progress status to the NAND flash memory 10 is busy of the NAND flash memory 10. Continue processing is performed according to the fact that the state has expired.

For example, if the command being executed is a write command or an erase command, the command sequence issuance unit 113b executes in response to receiving a response to the status read command (for example, status information) from the NAND flash memory 10. It is determined that the command inside is complete. Alternatively, for example, if the command being executed is a read command, the command sequence issuing unit 113b completes the command being executed in response to reception of data at the final address of the data to be read from the NAND flash memory 10 Judge that When determining that the command being executed is completed, the command sequence issuing unit 113b notifies the queue switching unit 113a to that effect.
Next, the operation of the memory system 100 will be described with reference to FIG. FIG. 4 is a flowchart showing the operation of the memory system 100.

  In step S1, the NAND controller 110 is executing a command (first command) in the command queue 111 with a low priority in response to the second command being stored in the command queue 112 with a high priority. It is determined whether or not. If the NAND controller 110 is executing the command processing of the command queue 111 with the low priority (Yes in step S1), the NAND controller 110 advances the processing to step S10 and is executing the command processing of the command queue 111 with the low priority. If not (No in step S1), the process proceeds to step S7.

In step S10, the NAND controller 110 performs a completion process according to the progress of access to the NAND flash memory 10 by the first command at the timing when the second command is stored in the command queue 112 having a high priority. A stop determination is made to select one of the interruption processes. In the completion processing, after the access processing by the first command being executed in the command queue with low priority is completed, the second command in the command queue with high priority is executed. In the interruption process, the access process by the first command being executed in the command queue having a low priority is interrupted, and the second command in the command queue having a high priority is executed.
Specifically, in step S10, the NAND controller 110 performs the following steps S11 to S13.

  In step S11, the NAND controller 110 determines whether or not the progress of access to the NAND flash memory 10 is after the busy state is started. If the access progress status is before the start of the busy state, the NAND controller 110 advances the process to step S7. If the access progress status is not before the start of the busy state (that is, after the start of the busy state), the NAND controller 110 Proceed to S13.

  In step S13, the NAND controller 110 determines whether or not the type of the first command being executed is a write command (WR access). If the first command type is a write command (Yes in step S13), the NAND controller 110 advances the process to step S2. If the first command type is not a write command (No in step S13), the NAND controller 110 performs processing. To step S7.

  In step S2, the NAND controller 110 performs a completion process. That is, the NAND controller 110 completes the execution of the first command in the command queue 111 with a low priority.

In step S7, the NAND controller 110 performs an interruption process. That is, the NAND controller 110 interrupts the execution of the first command in the command queue 111 having a low priority. At this time, the NAND controller 110 may generate and hold an interruption state flag indicating that execution of the first command is being interrupted.
In step S3, the NAND controller 110 executes the second command in the command queue 112 having a high priority, and completes the execution of the second command.

In step S20, the NAND controller 110 returns to perform any one of normal processing, continuation processing, and retry processing according to the progress of access to the NAND flash memory 10 by the first command at the interrupted timing. Make a decision. The normal process corresponds to the case where the completion process (step S2) is performed in response to the determination that the first command should be completed in the stop determination (step S10). Process. In the continuation process, the interruption process (step S7) is interrupted in response to the interruption process (step S7) performed in response to the determination that the first command should be interrupted in the stop determination (step S10). Continue the access processing after that. The retry process corresponds to the case where the interruption process (step S7) is performed in response to the determination that the first command should be interrupted in the stop determination (step S10), and to the command queue 112 having a high priority. Retry processing is performed on the first command in the low-priority command queue 111 before switching.
Specifically, in step S20, the NAND controller 110 performs the following steps S21 to S23.

  In step S21, the NAND controller 110 determines whether or not the low priority command queue 111 is suspended, for example, by referring to the suspension status flag. If the low priority command queue 111 is not suspended, that is, if the processing of the first command has been completed (No in step S21), the NAND controller 110 advances the processing to step S4, and executes the low priority command. If the queue 111 is suspended (Yes in step S22), the process proceeds to step S22.

  In step S22, the NAND controller 110 determines whether the progress of access to the NAND flash memory 10 by the first command at the interrupted timing is after the busy state has expired (the busy state has expired). If the access progress status is after the busy state has expired (Yes in step S22), the NAND controller 110 advances the processing to step S23, and if the access progress status is not after the busy state has expired, that is, before the busy state has expired (step) The process proceeds to step S6.

  In step S23, the processing executed by the NAND controller 110 in the NAND flash memory 10 is the processing of the first command in the command queue 111 having a low priority executed by the second command in the command queue 112 having a high priority. It is determined whether or not the process is affected by an access for updating information (cache, status information, etc.).

  For example, when the combination of the first command type of the low priority command queue 111 and the second command type of the high priority command queue 112 includes an erase command and a read command, the NAND controller 110 It is determined that the process of the first command is a process that is not affected by the update access of the internal information in the NAND flash memory 10 (No in step S23), and the process proceeds to step S5.

  Alternatively, for example, when the combination of the first command type and the second command type does not include an erase command and a read command, the NAND controller 110 performs processing of the first command in the NAND flash memory 10. It is determined that the process is affected by the internal information update access (Yes in step S23), and the process proceeds to step S6.

  In step S4, the NAND controller 110 performs normal processing. That is, the NAND controller 110 executes the command stored next to the first command in the command queue 111 having a low priority.

  In step S5, the NAND controller 110 performs a continuation process. That is, the NAND controller 110 completes the execution of the first command from the process at the time of interruption.

In step S6, the NAND controller 110 performs a retry process. That is, the NAND controller 110 starts and completes the execution of the first command from the first process.
Next, operations associated with the stop determination (step S10) and the return determination (step S20) will be described with reference to specific cases.

  In the first case, as shown in FIG. 5A, the write command WR2 is stored in the command queue 112 with high priority while the write command WR0 of the command queue 111 with low priority is being executed. The first case is, for example, a case corresponding to the normal process (step S4) shown in FIG.

  As shown in FIG. 5B, in the command sequence of the write command WR0 of the low priority command queue 111, the write command (Cmd80h-Adr-DataIn-Cmd10h), the write from the NAND controller 110 to the NAND flash memory 10 is performed. It is scheduled that an access process (tProg) such as data transfer and a status read command (Cmd70-StatusOut) are sequentially processed. The value of the Busy signal is “Ready” before and after the access process (tProg), and is scheduled to become “Busy” during the access process (tProg).

  At this time, when the write command WR2 is stored in the command queue 112 having a high priority at the timing t1 or the timing t2 after the start of the “Busy” state, as shown in FIG. 5C, the entire command sequence of the command WR0 After completing the write command, the access process, and the status read command, the execution of the write command WR2 of the command queue 112 having a high priority is started.

  Here, if the write command WR2 is stored in the command queue 112 with a high priority at the timing t1 or the timing t2, if the write command WR0 of the command queue 111 with a low priority is interrupted, the priority is high. Even if the write command WR0 of the low priority command queue 111 is started from the point of interruption after the completion of the write command WR2 of the command queue 112, writing to the NAND flash memory 10 is overwritten. Since the NAND flash memory 10 is difficult to overwrite the memory cell once written as described above, an alternative memory cell is searched for and written. It will be discarded as an invalid memory cell. As a result, resources in the NAND flash memory 10 are wasted.

  On the other hand, in the embodiment, when the write command WR2 is stored in the command queue 112 having a high priority at the timing t1 or the timing t2 after the timing when the access process (tProg) is started, the characteristics of the NAND flash memory 10 Therefore, all command sequences of the command WR0 being executed are completed without interruption. Thereby, useless consumption of resources in the NAND flash memory 10 can be reduced.

  As shown in FIG. 6A, the second case is a case where the read command RD0 is stored in the high priority command queue 112 while the erase command ER0 of the low priority command queue 111 is being executed. The second case is, for example, a case corresponding to the continuation process (step S5) shown in FIG.

  As shown in FIG. 6B, in the command sequence of the erase command ER0 of the low priority command queue 111, the erase command (Cmd60h-Adr-CmdD0h) is used for the erase operation from the NAND controller 110 to the NAND flash memory 10. The accompanying access process (tBERASE) and the status read instruction (Cmd70-StatusOut) are scheduled to be processed in order. The value of the Busy signal is “Ready” before and after the access process (tBERASE), and is scheduled to become “Busy” during the access process (tBERASE).

  At this time, when the read command RD0 is stored in the command queue 112 with high priority at the timing t3 after the expiration of the “Busy” state, as shown in FIG. 6C, the erase command ER0 in the command sequence of the erase command ER0. And the access process are completed, the erase command ER0 is interrupted, and the execution of the read command RD0 of the command queue 112 having a high priority is started. Then, when the execution of the read command RD0 of the command queue 112 with a high priority is completed, the processing is resumed and completed from the status read command in the command sequence of the erasure command ER0 being interrupted.

  In this case, because the internal information (cache, status information, etc.) of the NAND flash memory 10 when interrupted by the command queue 111 with low priority by processing of the read command RD0 of the command queue 112 with high priority is not lost. After the interruption, after the execution of the read command RD0 of the command queue 112 with the high priority is completed, the erasure command ER0 being interrupted can be continued.

  As shown in FIG. 7A, the third case is a case where the erase command ER0 is stored in the high priority command queue 112 while the read command RD0 of the low priority command queue 111 is being executed. The third case is, for example, a case corresponding to the continuation process (step S5) shown in FIG.

  As shown in FIG. 7B, in the command sequence of the read command RD0 of the low priority command queue 111, the read command (Cmd00h-Adr-Cmd30h), the data read operation from the NAND controller 110 to the NAND flash memory 10 is performed. It is scheduled that the access process (tR) accompanying the above and the data transfer process (DataOut) from the NAND flash memory 10 to the NAND controller 110 are sequentially processed. The value of the Busy signal is “Ready” before and after the access process (tR), and is scheduled to become “Busy” during the access process (tR).

  At this time, if the erase command ER0 is stored in the command queue 112 having a high priority at the timing t4 after the “Busy” state expires, as shown in FIG. 7C, the read command RD0 in the command sequence of the read command RD0. And the access process are completed, the read command RD0 is interrupted, and the execution of the erase command ER0 of the command queue 112 having a high priority is started. Then, when the execution of the erase command ER0 of the command queue 112 having a high priority is completed, the processing is resumed and completed from the data transfer process in the command sequence of the interrupted read command RD0.

  In this case, because the internal information (cache, status information, etc.) of the NAND flash memory 10 when interrupted by the low priority command queue 111 by the processing of the erase command ER0 of the high priority command queue 112 is not lost. After the interruption, after the execution of the erase command ER0 of the high priority command queue 112 is completed, the continuation processing of the suspended read command RD0 is possible.

  In the fourth case, as shown in FIG. 8A, the erase command ER1 is stored in the command queue 112 having a high priority while the erase command ER0 of the command queue 111 having a low priority is being executed. The fourth case is, for example, a case corresponding to the retry process (step S6) shown in FIG.

  As shown in FIG. 8B, in the command sequence of the erase command ER0 of the low priority command queue 111, the erase command (Cmd60h-Adr-CmdD0h) is used for the erase operation from the NAND controller 110 to the NAND flash memory 10. The accompanying access process (tBERASE) and the status read instruction (Cmd70-StatusOut) are scheduled to be processed in order. The value of the Busy signal is “Ready” before and after the access process (tBERASE), and is scheduled to become “Busy” during the access process (tBERASE).

  At this time, when the erase command ER1 is stored in the high priority command queue 112 at the timing t5 after the expiration of the “Busy” state, the erase command ER0 is interrupted as shown in FIG. The execution of the erase command ER1 of the high command queue 112 is started. When the execution of the erase command ER1 of the command queue 112 having a high priority is completed, the process is started and completed so that the process is restarted from the first erase instruction in the command sequence of the interrupted erase command ER0.

  In this case, the internal information (cache, status information, etc.) of the NAND flash memory 10 when it is interrupted by the low priority command queue 111 by the processing of the erase command ER1 of the high priority command queue 112 is discarded. For this reason, after execution of the erase command ER1 of the command queue 112 with high priority is completed after the interruption, retry processing of the erase command ER0 being interrupted is necessary.

  In the fifth case, as shown in FIG. 9A, the erase command ER1 is stored in the command queue 112 having a high priority while executing the erase command ER0 of the command queue 111 having a low priority. The fifth case is, for example, a case corresponding to the retry process (step S6) shown in FIG.

  As shown in FIG. 9B, in the command sequence of the erase command ER0 of the low priority command queue 111, the erase command (Cmd60h-Adr-CmdD0h) is used for the erase operation from the NAND controller 110 to the NAND flash memory 10. The accompanying access process (tBERASE) and the status read instruction (Cmd70-StatusOut) are scheduled to be processed in order. The value of the Busy signal is “Ready” before and after the access process (tBERASE), and is scheduled to become “Busy” during the access process (tBERASE).

  At this time, if the erase command ER1 is stored in the high priority command queue 112 at the timing t6 before the start of the “Busy” state, the erase command ER0 is interrupted as shown in FIG. The execution of the erase command ER1 of the high command queue 112 is started. When the execution of the erase command ER1 of the command queue 112 having a high priority is completed, the process is started and completed so that the process is restarted from the first erase instruction in the command sequence of the interrupted erase command ER0.

  Alternatively, when the erase command ER1 is stored in the high priority command queue 112 at the timing t7 in the “Busy” state, the erase command ER0 is interrupted as shown in FIG. The execution of the erase command ER1 in the command queue 112 is started. When the execution of the erase command ER1 of the command queue 112 having a high priority is completed, the process is started and completed so that the process is restarted from the first erase instruction in the command sequence of the interrupted erase command ER0.

  In this case, the internal information (cache, status information, etc.) of the NAND flash memory 10 when it is interrupted by the low priority command queue 111 by the processing of the erase command ER1 of the high priority command queue 112 is discarded. For this reason, after execution of the erase command ER1 of the command queue 112 with high priority is completed after the interruption, retry processing of the erase command ER0 being interrupted is necessary.

  As described above, the operations associated with the stop determination (step S10) and the return determination (step S20) have been described by exemplifying the first case to the fifth case, but various other cases are conceivable. A summary of the various cases is shown in FIG.

  Here, it is assumed that the processing unit 113 always completes the command processing of the command queue 111 with the low priority and then processes the command of the command queue 112 with the high priority. In this case, there is a tendency that the latency (time to command response) to a command with a higher priority becomes longer by the time waiting for the completion of processing of a command with a lower priority.

  On the other hand, in the embodiment, when the processing unit 113 stores the second command in the high priority command queue 112 while executing the first command stored in the low priority command queue 111, Depending on the progress of access to the NAND flash memory 10 by the first command at the timing when the second command is stored in the high priority command queue 112, either the interruption process or the completion process is performed. The interruption process is a process for interrupting the execution of the first command and executing the second command. The completion process is a process for completing the execution of the first command. As a result, the latency (time to command response) for a command having a higher priority can be shortened as compared with the case where the execution of the first command is necessarily completed.

  In the embodiment, the processing unit 113 selects either the interruption process or the completion process depending on the progress of access to the NAND flash memory 10 associated with the execution of the first command and the type of the first command. Do something. As a result, with regard to stopping the first command, it is possible to perform appropriate processing in consideration of both the access progress status and the type of the first command.

  For example, in the embodiment, the processing unit 113 performs an interruption process in response to the first command being an erase command or a read command, and performs a completion process in response to the first command being a write command. As a result, the interruption process and the completion process can be switched in consideration of the characteristics of the NAND flash memory 10 associated with the execution of the command.

  Alternatively, suppose that the interruption process is performed when the first command is a write command and the progress of access to the NAND flash memory 10 is after the NAND flash memory 10 is in a busy state. In this case, even if the first command (write command) of the low priority command queue 111 is started from the point of interruption after the execution of the second command of the high priority command queue 112 is completed, it is transferred to the NAND flash memory 10. Will be overwritten. Since the NAND flash memory 10 is difficult to overwrite the memory cell once written as described above, an alternative memory cell is searched for and written. It will be discarded as an invalid memory cell. As a result, resources in the NAND flash memory 10 are wasted.

  Alternatively, suppose that the completion processing is performed when the first command is a write command and the progress of access to the NAND flash memory 10 is before the busy state of the NAND flash memory 10 starts. In this case, the first command (write command) in the low priority command queue 111 can be started from the point of interruption after the execution of the second command in the high priority command queue 112 is completed. That is, if the busy state is not yet started, the writing to the memory cell in the NAND flash memory 10 has not been performed yet, so the writing to the memory cell can be performed without being overwritten. That is, in this case, performing the completion process unnecessarily completes the execution of the first command, and tends to increase the latency (time to command response) to a command with a high priority.

  On the other hand, in the embodiment, the processing unit 113 responds that the first command is a write command and the progress of access to the NAND flash memory 10 is before the start of the busy state of the NAND flash memory 10. To perform interruption processing. Accordingly, the command sequence of the first command (write command) being executed is interrupted in consideration of the characteristics of the NAND flash memory 10, so that the latency to a command with a high priority can be reduced. Further, the processing unit 113 performs a completion process in response to the first command being a write command and the progress of access to the NAND flash memory 10 being after the busy state of the NAND flash memory 10 is started. . That is, the processing unit 113 starts executing the second command after the execution of the first command is completed by the completion process. As a result, the command sequence of the first command (write command) being executed is completed without interruption in consideration of the characteristics of the NAND flash memory 10, and wasteful consumption of resources in the NAND flash memory 10 is achieved. Can be reduced. That is, according to the embodiment, it is possible to reduce the latency to a command having a high priority, and to reduce wasteful consumption of resources in the NAND flash memory 10.

  Alternatively, if the processing unit 113 performs the interruption process, the processing of the first command in the low priority command queue 111 is forcibly discarded, and then the second priority in the high priority command queue 112 is set. Consider the case of command processing. In this case, since the processing of the first command in the command queue 111 with a low priority is forcibly discarded, the throughput of the first command in the command queue 111 with a low priority tends to decrease. .

  On the other hand, in the embodiment, after the execution of the first command is interrupted by the interruption process and the execution of the second command is completed, the processing unit 113 performs the NAND type based on the first command at the interruption timing. Depending on the progress of access to the flash memory 10, either the continuation process or the retry process is performed. The continuation process is a process for continuing the execution of the first command from the process at the time of interruption. The retry process is a process for redoing the execution of the first command from the first process. Thus, in consideration of the characteristics of the NAND flash memory 10, that is, whether or not the internal state of the NAND flash memory 10 is destroyed, the first command can be continued from the processing at the time of interruption when possible. it can. As a result, the throughput can be improved with respect to the processing of the first command in the command queue 111 having a low priority.

  In the embodiment, the processing unit 113 performs a retry process in response to the progress of access to the NAND flash memory 10 before the busy state of the NAND flash memory 10 expires, and transfers the NAND flash memory 10 to the NAND flash memory 10. Is continued after the busy state of the NAND flash memory 10 has expired. As a result, the first command can be continued from the processing at the time of interruption when possible, considering the access progress.

  Further, in the embodiment, the processing unit 113 performs the progress of access to the NAND flash memory 10 by the first command at the interrupted timing, and the combination of the first command type and the second command type. In response, either continuation processing or retry processing is performed. As a result, regarding the return to the execution of the first command, it is possible to perform appropriate processing in consideration of both the access progress status and the combination of the first command type and the second command type.

  In the embodiment, the processing unit 113 performs a continuation process in response to the combination of the first command type and the second command type including an erase command and a read command, and the first command type. In response to the combination of the second command type not including the erase command and the read command, the retry process is performed. Thus, in consideration of the characteristics of the NAND flash memory 10, that is, whether or not the internal state of the NAND flash memory 10 is destroyed, the first command can be continued from the processing at the time of interruption when possible. it can.

  In the embodiment, the processing unit 113 includes a combination of the first command type and the second command type that includes an erase command and a read command, and the access progress status to the NAND flash memory 10 is NAND flash. In response to the fact that the busy state of the memory 10 has not expired, a retry process is performed. The processing unit 113 includes a combination of the first command type and the second command type including an erase command and a read command, and the access progress status to the NAND flash memory 10 indicates that the NAND flash memory 10 is busy. Continue processing is performed according to what is later. Thus, in consideration of both the access progress and the combination of the first command type and the second command type, the first command is interrupted when the internal state of the NAND flash memory 10 is not destroyed. It can be continued from time processing.

  In the above embodiment, the case where the status read command (Cmd70-StatusOut) is performed after the completion of the access process (tProg) in the command sequence of the write command is illustrated (see FIG. 5B). The read command may be repeated as a status polling command, starting from the access process.

  Similarly, in the command sequence of the erase command, a case where a status read command (Cmd70-StatusOut) is performed after the completion of the access process (tBERASE) is illustrated (see FIG. 6B). As a polling instruction, it may be started repeatedly during access processing.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  2 ATA I / F, 4 drive control circuit, 10 NAND flash memory, 11 memory cell array, 12 page buffer, 13 data cache, 14 status register, 15 control circuit, 20 RAM, 100 memory system, 101 data access bus, 102 circuit control bus, 104 processor, 105 boot ROM, 106 ROM controller, 110 NAND controller, 111 low priority command queue, 112 high priority command queue, 113 processing unit, 113a queue switching unit, 113b command sequence issue Part, 114 RAM controller, 115 SRAM, 116 SRAM controller, 117 ATA controller.

Claims (10)

Non-volatile semiconductor memory;
A control unit for controlling the nonvolatile semiconductor memory;
With
The controller is
A first command queue;
A second command queue having a higher priority than the first command queue;
A processing unit that selects any one of the first command queue and the second command queue, executes a command stored in the selected command queue, and performs access processing to the nonvolatile semiconductor memory. If the second command is stored in the second command queue during execution of the first command stored in the first command queue, the second command is stored in the second command queue. And an interrupt process for interrupting execution of the first command and executing the second command in accordance with the progress of access to the nonvolatile semiconductor memory by the first command at the timing stored in A processing unit that performs any one of a completion process for completing the execution of one command;
A memory system comprising: The processing unit performs either the interruption process or the completion process depending on the progress of access to the nonvolatile semiconductor memory accompanying the execution of the first command and the type of the first command. The memory system according to claim 1, wherein the memory system is performed. The processing unit performs the interruption process in response to the first command being an erase command or a read command, and performs the completion process in response to the first command being a write command. The memory system according to claim 2. The processing unit performs the interruption process when the first command is a write command and the progress of access to the nonvolatile semiconductor memory is before the busy state of the nonvolatile semiconductor memory is started. The completion processing is performed in response to the first command being a write command and the progress of access to the nonvolatile semiconductor memory being after the busy state of the nonvolatile semiconductor memory is started. The memory system according to claim 3. 5. The method according to claim 1, wherein the processing unit starts executing the second command after the execution of the first command is completed by the completion processing. 6. Memory system. After the execution of the first command is interrupted by the interruption process and the execution of the second command is completed, the processing unit applies the first command to the nonvolatile semiconductor memory at the interruption timing. According to an access progress situation, either the continuation process for continuing the execution of the first command from the process at the time of interruption or the retry process for re-executing the execution of the first command from the first process is performed. The memory system according to any one of claims 1 to 4. The processing unit performs the retry process in response to the progress of access to the non-volatile semiconductor memory being before the busy state of the non-volatile semiconductor memory expires, and the progress of access to the non-volatile semiconductor memory is The memory system according to claim 6, wherein the continuation process is performed in response to the expiration of the busy state of the nonvolatile semiconductor memory. The processing unit, according to the progress of access to the nonvolatile semiconductor memory by the first command at the interrupted timing, and a combination of the type of the first command and the type of the second command, The memory system according to claim 6, wherein either the continuation process or the retry process is performed. The processing unit performs the continuation process in response to the combination including an erase command and a read command, and performs the retry process in response to the combination not including an erase command and a read command. The memory system according to claim 8. The processing unit performs the retry process when the combination includes an erase command and a read command and the progress of access to the nonvolatile semiconductor memory is before the busy state of the nonvolatile semiconductor memory expires. The continuation processing is performed when the combination includes an erase command and a read command, and the progress of access to the nonvolatile semiconductor memory is after the busy state of the nonvolatile semiconductor memory has expired. The memory system according to claim 9.

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