JP2013197413A - Method of manufacturing magnetoresistive effect element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid processing damage.SOLUTION: In the method of manufacturing a magnetoresistive effect element, a first insulation layer 32 and a second insulation layer 33 are formed on a substrate. A second hole 34 penetrating the second insulation layer, and a first hole 35 penetrating the first insulation layer are formed. Diameter of the first hole is set larger than that of the second hole. A first magnetic layer 37 is formed on the substrate in the first hole, and the second insulation layer on the outside of the first and second holes, so as to be separated from each other. Diameters of the first hole and second hole are enlarged. The first magnetic layer on the outside of the first and second holes is removed. On the first magnetic layer in the first hole, a tunnel barrier layer 38 is formed to cover the first magnetic layer in the first hole. A second magnetic layer 39 is formed on the tunnel barrier layer in the first hole.

Description

  Embodiments described herein relate generally to a method of manufacturing a magnetoresistive element.

  In the process of manufacturing a resistance change memory, after depositing a lower electrode layer, a variable resistance layer, and an upper electrode layer, a resist pattern is formed by lithography, and the upper electrode layer, variable resistance layer, and lower electrode layer are formed using the resist pattern as a mask. Is etched to form a variable resistance element.

  In MRAM (Magnetic Random Access Memory), a magnetoresistive element is used as a variable resistance element. The magnetoresistive element is composed of a magnetic tunnel junction (MTJ) element including a first magnetic layer, an intermediate layer (tunnel barrier layer), and a second magnetic layer.

  The magnetic layer in this MTJ element does not have corrosion resistance. For this reason, when RIE (Reactive Ion Etching) using a general chlorine gas is performed as the etching of the magnetic layer, the magnetic layer absorbs moisture due to residual chlorine adsorbed after the etching and corrodes.

  As a countermeasure, a method of etching the magnetic layer by physical etching such as IBE (Ion Beam Etching) has been proposed. However, when physical etching is performed, processing damage occurs at the etching end of the magnetic layer. For this reason, with the miniaturization of the element, the influence of the damage on the end portion of the magnetic layer is increased, and the magnetic characteristics are deteriorated.

JP 2002-26421 A

  A method of manufacturing a magnetoresistive element that avoids processing damage is provided.

  According to the present embodiment, a method for manufacturing a magnetoresistive effect element is provided. In the method for manufacturing a magnetoresistive element, a first insulating layer is formed on a substrate. A second insulating layer is formed on the first insulating layer. After forming the second hole penetrating the second insulating layer, the first hole connecting to the second hole and penetrating the first insulating layer is formed. The first insulating layer and the second insulating layer are processed so that the diameter of the first hole is larger than the diameter of the second hole. A first magnetic layer is formed on the substrate in the first hole and on the second insulating layer outside the first hole and the second hole so as to be separated from each other. The first insulating layer and the second insulating layer are processed so that the diameter of the first hole and the diameter of the second hole are increased. The first magnetic layer outside the first hole and the second hole is removed. The first magnetic layer in the first hole so as to be separated from each other on the first magnetic layer in the first hole and on the second insulating layer outside the first hole and the second hole. A tunnel barrier layer is formed so as to cover the layer. A second magnetic layer is formed on the tunnel barrier layer in the first hole and on the tunnel barrier layer outside the first hole and the second hole so as to be separated from each other. The second magnetic layer and the tunnel barrier layer outside the first hole and the second hole are removed.

The circuit diagram which shows the memory cell of MARM. Sectional drawing which shows the structure of the memory cell of MARM. Sectional drawing which shows the structure of the magnetoresistive effect element which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 1st Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 1st Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 1st Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 1st Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 1st Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 1st Embodiment following FIG. Sectional drawing which shows the structure of the magnetoresistive effect element which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 2nd Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 2nd Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 2nd Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 2nd Embodiment following FIG. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 2nd Embodiment following FIG. FIG. 18 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the second embodiment, following FIG. 17. Sectional drawing which shows the structure of the magnetoresistive effect element which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 3rd Embodiment. FIG. 22 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the third embodiment, following FIG. 21. FIG. 22 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the third embodiment, following FIG. 21. FIG. 23 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the third embodiment, following FIG. 22. FIG. 24 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the third embodiment, following FIG. 23. FIG. 25 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the third embodiment, following FIG. 24. Sectional drawing which shows the structure of the magnetoresistive effect element which concerns on 4th Embodiment. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 4th Embodiment. FIG. 28 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the fourth embodiment, following FIG. 27. FIG. 29 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the fourth embodiment, following FIG. 28. FIG. 30 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the fourth embodiment, following FIG. 29. FIG. 31 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the fourth embodiment, following FIG. 30. Sectional drawing which shows the manufacturing process of the magnetoresistive effect element which concerns on 4th Embodiment following FIG. FIG. 33 is a cross-sectional view showing the manufacturing process of the magnetoresistive effect element according to the fourth embodiment, following FIG. 32.

  The present embodiment will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals. In addition, overlapping explanation will be given as necessary.

<MRAM configuration example>
A configuration example of MARM will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a circuit diagram showing a MARM memory cell.

  As shown in FIG. 1, the memory cell in the memory cell array MA includes a serial connection body of a magnetoresistive effect element MTJ and a switch element (for example, FET) T. One end of the series connection body (one end of the magnetoresistive effect element MTJ) is connected to the bit line BLA, and the other end of the series connection body (one end of the switch element T) is connected to the bit line BLB. The control terminal of the switch element T, for example, the gate electrode of the FET is connected to the word line WL.

  The potential of the word line WL is controlled by the first control circuit 11. Further, the potentials of the bit lines BLA and BLB are controlled by the second control circuit 12.

  FIG. 2 is a cross-sectional view showing the structure of a MARM memory cell.

  As shown in FIG. 2, the memory cell includes a switch element T and a magnetoresistive effect element MTJ disposed on the semiconductor substrate 21.

  The semiconductor substrate 21 is, for example, a Si (silicon) substrate, and its conductivity type may be either P type or N type. In the semiconductor substrate 21, for example, a silicon oxide film having an STI structure is disposed as the element isolation insulating layer 22.

  The switch element T is disposed in the surface region of the semiconductor substrate 21, specifically, in an element region (active area) surrounded by the element isolation insulating layer 22. In this example, the switch element T is an FET, and includes two source / drain diffusion layers 23 in the semiconductor substrate 21 and a gate electrode 24 disposed on a channel region therebetween. The gate electrode 24 functions as the word line WL.

  The switch element T is covered with an interlayer insulating layer. The contact hole is provided in the interlayer insulating layer, and the contact via (CB) 26 is disposed in the contact hole. The contact via 26 is formed of a metal material such as W (tungsten) or Cu (copper).

  The lower surface of the contact via 26 is connected to the switch element. In this example, the contact via 26 is in direct contact with the source / drain diffusion layer 23.

  A lower electrode (LE) 27 is disposed on the contact via 26. The lower electrode 27 is made of, for example, TiN (titanium nitride).

  A magnetoresistive element MTJ is disposed on the lower electrode 27, that is, immediately above the contact via 26. Details of the magnetoresistive element MTJ according to the present embodiment will be described later.

  An upper electrode (UE) 28 is disposed on the magnetoresistive element MTJ. The upper electrode 28 is made of, for example, TiN. The upper electrode 28 is connected to a bit line (for example, Cu) BLA through a via (for example, Cu) 29.

<First Embodiment>
The magnetoresistive effect element MTJ according to the first embodiment will be described with reference to FIGS. In the first embodiment, the second hole 34 is formed in the second insulating layer 33, and the first hole 35 having a larger diameter (diameter in the plane) than the second hole 34 is formed in the first insulating layer 32. Then, the magnetoresistive effect element MTJ is formed at the bottom in the first hole 35 by the sputtering method through the second hole 34. Thereby, the magnetoresistive effect element MTJ can be formed without etching, and processing damage to the magnetoresistive effect element MTJ can be avoided. The magnetoresistive effect element MTJ according to the first embodiment will be described in detail below.

[Structure of First Embodiment]
First, the structure of the magnetoresistive element MTJ according to the first embodiment will be described with reference to FIG.

  FIG. 3 is a cross-sectional view showing the structure of the magnetoresistive element MTJ according to the first embodiment. In FIG. 3, the via 29 in FIG. 2 is omitted.

  As shown in FIG. 3, the magnetoresistive element MTJ includes a storage layer 37, a tunnel barrier layer 38, a reference layer 39, and the like.

  The memory layer 37 is formed on the lower electrode 27 (on the upper surface) via a base layer (not shown). The lower electrode 27 is formed in contact with the contact via 26 formed in the inter-wiring insulating layer 31 and is electrically connected to the semiconductor substrate 21. The storage layer 37 is a ferromagnetic layer having a variable magnetization direction, and has perpendicular magnetization that is perpendicular or nearly perpendicular to the film surface (upper surface / lower surface). Here, the variable magnetization direction means that the magnetization direction changes with respect to a predetermined write current. Further, that the magnetization direction is perpendicular or nearly perpendicular means that it is in a range of 45 ° <θ ≦ 90 ° with respect to the film surface.

  The storage layer 37 is made of a ferromagnetic material including one or more elements of, for example, Co (cobalt) or Fe (iron). For the purpose of adjusting saturation magnetization or magnetocrystalline anisotropy, an element such as B (boron), C (carbon), or Si may be added to the ferromagnetic material.

  The tunnel barrier layer 38 is formed on the storage layer 37 (on the upper surface). The tunnel barrier layer 38 is a nonmagnetic layer and is made of, for example, MgO (magnesium oxide).

  The reference layer 39 is formed on the tunnel barrier layer 38 (on the upper surface). The reference layer 39 is a ferromagnetic layer whose magnetization direction is invariant and has perpendicular magnetization that is perpendicular or nearly perpendicular to the film surface. Here, that the magnetization direction is unchanged means that the magnetization direction does not change with respect to a predetermined write current. That is, the reference layer 39 has a larger magnetization direction reversal threshold than the storage layer 37.

  The reference layer 39 is made of, for example, a ferromagnetic material including one or more elements of Co, Fe, B, Ni (nickel), Ir (iridium), Pt (platinum), Mn (manganese), or Ru. Is done.

  An upper electrode 28 is formed on the reference layer 39 (on the upper surface). On the upper electrode 28, a bit line BLA is formed through a via (not shown). Thereby, the upper electrode 28 is electrically connected to the bit line BLA.

  The planar shape of the magnetoresistive effect element MTJ including the memory layer 37, the tunnel barrier layer 38, and the reference layer 39 is, for example, a circle. The diameters of the storage layer 37, the tunnel barrier layer 38, and the reference layer 39 are, for example, about the same. That is, the magnetoresistive effect element MTJ is formed in a cylindrical shape. The lower electrode 27 and the upper electrode 28 have the same planar shape and diameter as these. Note that the planar shape of the magnetoresistive element MTJ is not limited to a circle. When an in-plane magnetization film is used as the magnetic layer, the planar shape of the magnetoresistive element MTJ may be an elliptical shape.

  Although not shown, an interface layer may be formed at the interface between the reference layer 39 and the tunnel barrier layer 38. The interface layer achieves lattice matching with the tunnel barrier layer 38 in contact with the lower layer. The interface layer is made of the same material as that of the reference layer 39, for example, but the composition ratio may be different.

  Further, a shift adjustment layer may be formed on the reference layer 39 via a spacer layer (not shown) (for example, Ru). The shift adjustment layer is a magnetic layer whose magnetization direction is not changed, and has perpendicular magnetization that is perpendicular or nearly perpendicular to the film surface. The magnetization direction is opposite to the magnetization direction of the reference layer 39. Thereby, the shift adjustment layer can cancel the leakage magnetic field from the reference layer 39 applied to the storage layer 37. In other words, the shift adjustment layer has an effect of adjusting the offset of the inversion characteristic with respect to the storage layer 37 due to the leakage magnetic field from the reference layer 39 in the reverse direction. This shift adjustment layer is composed of, for example, an artificial lattice having a laminated structure of a magnetic material such as Ni, Fe, or Co and a nonmagnetic material such as Cu, Pd, or Pt.

  Further, the arrangement of the storage layer 37 and the reference layer 39 may be reversed. That is, the reference layer 39, the tunnel barrier layer 38, and the memory layer 37 may be formed on the lower electrode 27 in order.

  A third insulating layer 40 is formed on the side surfaces of the magnetoresistive element MTJ, the lower electrode 27, and the upper electrode 28. In other words, the third insulating layer 40 is formed so as to surround the magnetoresistive element MTJ, the lower electrode 27, and the upper electrode 28. The third insulating layer 40 is made of, for example, a silicon oxide film or a silicon nitride film.

  A first insulating layer 32 is formed on the side surface of the third insulating layer 40. In other words, the first insulating layer 32 is formed so as to surround the third insulating layer 40. The lower surface of the first insulating layer 32 is formed at the same height as the lower surface of the lower electrode 27, and the upper surface of the first insulating layer 32 is formed at the same height as or higher than the upper surface of the upper electrode 28. The first insulating layer 32 is made of, for example, a silicon oxide film.

  Thus, the third insulating layer 40 is formed as a side wall of the first hole 35 described later formed in the first insulating layer 32, and the magnetoresistive effect element is formed on the side surface of the third insulating layer 40 in the first hole 35. MTJ, lower electrode 27, and upper electrode 28 are formed.

  A second insulating layer 33 is formed on the upper surface of the first insulating layer 32. The second insulating layer 33 has a higher nitrogen concentration than the first insulating layer 32 and is made of, for example, a silicon oxynitride film.

  The material which comprises the 1st insulating layer 32 and the 2nd insulating layer 33 is not restricted to the said material. In the wet etching process described later, the first insulating layer 32 may be made of an insulating material that has an etching rate larger than that of the second insulating layer 33. For example, the first insulating layer 32 may be composed of a silicon oxynitride film having a low nitrogen concentration, and the second insulating layer 33 may be composed of a silicon oxynitride film having a high nitrogen concentration. The first insulating layer 32 may be formed of a silicon oxynitride film, and the second insulating layer 33 may be formed of a silicon nitride film.

  Next, an operation example of the magnetoresistive element MTJ will be described.

  The magnetoresistive element MTJ is, for example, a spin injection type magnetoresistive element. Therefore, when writing data to the magnetoresistive effect element MTJ or reading data from the magnetoresistive effect element MTJ, the magnetoresistive effect element MTJ is energized in both directions in a direction perpendicular to the film surface (lamination surface). Is done.

  More specifically, data writing to the magnetoresistive effect element MTJ is performed as follows.

  When electrons are supplied from the upper electrode 28 side (electrons traveling from the reference layer 39 to the storage layer 37), electrons that are spin-polarized in the same direction as the magnetization direction of the reference layer 39 are injected into the storage layer 37. In this case, the magnetization direction of the storage layer 37 is aligned with the same direction as the magnetization direction of the reference layer 39. As a result, the magnetization direction of the reference layer 39 and the magnetization direction of the storage layer 37 are arranged in parallel. In the parallel arrangement, the resistance value of the magnetoresistive element MTJ is the smallest. This case is defined as, for example, data “0”.

  On the other hand, when electrons (electrons traveling from the storage layer 37 to the reference layer 39) are supplied from the lower electrode 27 side, the electrons are reflected by the reference layer 39 and thus spin-polarized in a direction opposite to the magnetization direction of the reference layer 39. Electrons are injected into the storage layer 37. In this case, the magnetization direction of the storage layer 37 is aligned with the direction opposite to the magnetization direction of the reference layer 39. Thereby, the magnetization direction of the reference layer 39 and the magnetization direction of the storage layer 37 are antiparallel. In this antiparallel arrangement, the resistance value of the magnetoresistive element MTJ is the largest. This case is defined as, for example, data “1”.

  Data is read as follows.

  A read current is supplied to the magnetoresistive element MTJ. This read current is set to a value that does not reverse the magnetization direction of the storage layer 32 (a value smaller than the write current). By detecting a change in the resistance value of the magnetoresistive effect element MTJ at this time, a semiconductor device capable of memory operation is obtained.

[Production Method of First Embodiment]
Next, a method for manufacturing the magnetoresistive element MTJ according to the first embodiment will be described with reference to FIGS.

  4 to 10 are cross-sectional views showing manufacturing steps of the magnetoresistive element MTJ according to the first embodiment.

  First, as shown in FIG. 4, an inter-wiring insulating layer 31 is formed on a semiconductor substrate 21 on which a cell transistor (switch element T) is formed. A contact hole is formed in the inter-wiring insulating layer 31, and a contact via 26 made of, for example, W is formed in the contact hole. Thereby, the magnetoresistive effect element MTJ formed later and the semiconductor substrate 21 can be electrically connected. In the following description, the inter-wiring insulating layer 31 in which the contact via 26 is formed may be referred to as a substrate.

  Next, as shown in FIG. 5, the first insulating layer 32 is formed on the inter-wiring insulating layer 31 in which the contact vias 26 are formed by, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition). The first insulating layer 32 is made of, for example, a silicon oxide film. Further, the film thickness of the first insulating layer 32 is thicker than the integrated film thickness of the lower electrode 27, the magnetoresistive effect element MTJ, and the upper electrode 28 that are formed later.

  Next, the second insulating layer 33 is formed on the first insulating layer 32 by, for example, PECVD. The second insulating layer 33 has a higher nitrogen concentration than the first insulating layer 32 and is made of, for example, a silicon oxynitride film.

  Next, a resist pattern (not shown) is formed on the second insulating layer 33 by lithography. Using this resist pattern as a mask, through holes 36 penetrating from the upper surface to the lower surface are formed in the second insulating layer 33 and the first insulating layer 32 by, for example, RIE. The through hole 36 includes a second hole 34 that penetrates the second insulating layer 33, and a first hole 35 that is connected to the second hole 34 and penetrates the first insulating layer 32. As a result, the substrate, particularly the upper surface of the contact via 26 is exposed at the bottom surface of the through hole 36 (first hole 35). The planar shape of the through hole 36 is, for example, a circle.

  Next, as shown in FIG. 6, the first insulating layer 32 and the second insulating layer 33 are isotropically etched by, for example, wet etching using a diluted hydrofluoric acid aqueous solution. At this time, since the upper surface of the second insulating layer 33 is covered with a resist pattern (not shown), the side surfaces of the first insulating layer 32 and the second insulating layer 33 are etched.

  At this time, the first insulating layer 32 made of a silicon oxide film has a higher etching rate than the second insulating layer 33 made of a silicon oxynitride film containing more nitrogen. Therefore, the side surface of the first insulating layer 32 in the first hole 35 is etched more than the side surface of the second insulating layer 33 in the second hole 34. Accordingly, the diameter of the first hole 35 (the diameter on the upper side of the through hole 36) is larger than the diameter of the second hole 34 (the diameter on the lower side of the through hole 36). In other words, the second insulating layer 33 protrudes toward the central axis of the through hole 36 from the first insulating layer 32. A gap 60 is formed in the first hole 35 below the protruding portion of the second insulating layer 33. That is, when viewed in plan, the circular shape of the second hole 34 is included in the circular shape of the first hole 35. Thereafter, the resist pattern (not shown) is removed.

  Next, as shown in FIG. 7, the lower electrode 27 made of, eg, TiN is deposited by, eg, sputtering. At this time, for example, a sputtering method having a high vertical component (from the vertical direction or substantially vertical direction) is performed on the film surface using a collimator or the like. Thereby, the lower electrode 27 is hardly formed on the side surface of the second insulating layer 33 in the second hole 34. Further, since the gap 60 is provided in the first hole 35, the lower electrode 27 is not formed on the side surface of the first insulating layer 32 in the first hole 35.

  Note that the sputtering method from the vertical direction or the substantially vertical direction is a sputtering method in which deposited molecules fly from a direction in which the deposited film is not substantially formed on the side surface of the second insulating layer 33 in the second hole 34. is there.

  As a result, the lower electrode 27 is formed on the contact via 26 in the first hole 35, that is, on the bottom surface in the first hole 35 with a gap 60. At the same time, the lower electrode 27 is also formed on the second insulating layer 33 outside the through hole 36. At this time, the lower electrode 27 on the contact via 26 in the first hole 35 and the lower electrode 27 on the second insulating layer 33 outside the through hole 36 are formed so as to be separated from each other.

  Further, since the lower electrode 27 is formed by the sputtering method through the second hole 34, the planar shape of the lower electrode 27 is approximately the same as the planar shape of the second hole 34. Further, the diameter of the lower electrode 27 is approximately the same as the diameter of the second hole 34.

  Next, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are sequentially deposited by, for example, the sputtering method similar to that for the lower electrode 27. At this time, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are hardly formed on the side surface of the second insulating layer 33 in the second hole 34. Further, since the gap 60 is provided in the first hole 35, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are on the side surface of the first insulating layer 32 in the first hole 35. Also not formed.

  As a result, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are sequentially formed on the lower electrode 27 (on the upper surface) in the first hole 35 with a gap 60. At the same time, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are also formed on the lower electrode 27 outside the through hole 36. At this time, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 on the lower electrode 27 in the first hole 35, and the memory layer 37 and the tunnel barrier layer on the lower electrode 27 outside the through hole 36. 38, the reference layer 39, and the upper electrode 28 are formed so as to be separated from each other.

  Further, since the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are formed by the sputtering method through the second hole 34, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are formed. The planar shape of the electrode 28 is approximately the same as the planar shape of the second hole 34 (lower electrode 27). The diameters of the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are approximately the same as the diameter of the second hole 34 (lower electrode 27).

  The memory layer 37 is made of a ferromagnetic material including one or more elements of Co or Fe, for example. The tunnel barrier layer 38 is a nonmagnetic layer and is made of, for example, MgO. The reference layer 39 is made of, for example, a ferromagnetic material including one or more elements of Co, Fe, B, Ni, Ir, Pt, Mn, or Ru. The upper electrode 28 is made of, for example, TiN.

  Thus, the lower electrode 27, the magnetoresistive effect element MTJ, and the upper electrode 28 are formed in the through hole 35 without etching.

  Next, as shown in FIG. 8, the third insulating layer 40 is formed so as to fill the first hole 35 and the second hole 34 by, for example, a spin coating method. The third insulating layer 40 is made of, for example, a silicon oxide film or a silicon nitride film. The method for forming the third insulating layer 40 is not limited to the spin coating method, and any film forming method that does not have an oxidizing action on the magnetoresistive effect element MTJ may be used. In order to suppress oxygen from entering the magnetoresistive element MTJ in a later process, the third insulating layer 40 is preferably formed of, for example, a silicon nitride film.

  Next, as shown in FIG. 9, the upper electrode 28, the reference layer 39, the tunnel barrier layer 38, and the memory layer 37 formed on the second insulating layer 33 outside the through hole 36 by, for example, CMP (Chemical Mechanical Polishing). And the lower electrode 27 are removed. Further, a part on the upper side of the third insulating layer 40 is also removed.

  Next, as shown in FIG. 10, a resist pattern (not shown) is formed on the second insulating layer 33 (and the third insulating layer 40) by lithography. Using this resist pattern as a mask, wiring grooves 41 are formed in the first insulating layer 32, the second insulating layer 33, and the third insulating layer 40 by, for example, RIE. As a result, the upper surface of the upper electrode 28 is exposed at the bottom surface of the wiring groove 41.

  Next, as shown in FIG. 3, after forming a Cu seed layer (not shown) on the entire surface by, for example, sputtering, a Cu layer is formed on the Cu seed layer by, for example, an electrolytic plating technique. Thereafter, the Cu layer formed on the second insulating layer 33 outside the wiring groove 41 is removed, and the bit line BLA made of Cu is formed in the wiring groove 41.

  Thus, the magnetoresistive effect element MTJ according to the first embodiment, the wiring electrode connected thereto, and the like are formed.

[Effect of the first embodiment]
According to the first embodiment, after the first insulating layer 32 and the second insulating layer 33 are stacked, the second hole 34 is formed in the second insulating layer 33, and the second hole 34 is formed in the first insulating layer 32. A first hole 35 having a larger diameter is formed. Then, the lower electrode 27, the magnetoresistive effect element MTJ (the memory layer 37, the tunnel barrier layer 38, and the reference layer 39), and the upper electrode 28 are formed on the bottom of the first hole 35 by a sputtering method through the second hole 34. Form. Thereby, the magnetoresistive effect element MTJ can be formed without etching. Therefore, it is possible to avoid processing damage to the magnetoresistive effect element MTJ that has been caused by etching.

<Second Embodiment>
A magnetoresistive element MTJ according to the second embodiment will be described with reference to FIGS. 11 to 18. The second embodiment is a modification of the first embodiment. After the storage layer 37 is formed, the diameter of the second hole 34 is increased, so that the tunnel barrier layer 38 formed thereafter forms the storage layer. It is an example which covers the upper surface and side surface of 37. The magnetoresistive effect element MTJ according to the second embodiment will be described in detail below.

  Note that in the second embodiment, description of the same points as in the first embodiment will be omitted, and different points will be mainly described.

[Structure of Second Embodiment]
First, the structure of the magnetoresistive element MTJ according to the second embodiment will be described with reference to FIG.

  FIG. 11 is a cross-sectional view showing the structure of the magnetoresistive element MTJ according to the second embodiment. In FIG. 11, the via 29 in FIG. 2 is omitted.

  As shown in FIG. 11, the second embodiment is different from the first embodiment in that the tunnel barrier layer 38 is formed so as to cover the upper surface and the side surface of the storage layer 37 and the side surface of the lower electrode 27. It is a point.

  More specifically, the lower electrode 27 is formed on the contact via 26 formed in the inter-wiring insulating layer 31. On the lower electrode 27 (on the upper surface), a memory layer 37 having a planar shape and diameter comparable to those of the lower electrode 27 is formed. A tunnel barrier layer 38 is formed so as to cover the upper and side surfaces of the storage layer 37 and the side surface of the lower electrode 27. In other words, the tunnel barrier layer 38 is formed so as to be connected to the upper surface and the side surface of the memory layer 37 and the side surface of the lower electrode 27. As a result, the end of the storage layer 37 is covered with the tunnel barrier layer 38, and leakage between the storage layer 37 and the reference layer 39 can be prevented and insulated. The tunnel barrier layer 38 may be formed so as to be connected to the substrate (on the contact via 26 and the inter-wiring insulating layer 31).

  A reference layer 39 is formed on the tunnel barrier layer 38 (on the upper surface). At this time, since the tunnel barrier layer 38 is also formed on the side surface of the storage layer 37, the reference layer 39 is formed with a diameter larger than that of the storage layer 37. Thereby, the influence of the leakage magnetic field from the reference layer 39 on the storage layer 37 can be suppressed, and the inversion efficiency of the storage layer 37 can be improved. The reference layer 39 may be formed so as to be connected to the side surface of the tunnel barrier layer 38.

  An upper electrode 28 is formed on the reference layer 39 (on the upper surface). At this time, the upper electrode 28 has the same planar shape and diameter as the reference layer 39. The upper electrode 28 may be formed so as to be connected to the side surface of the reference layer 39 and / or the side surface of the tunnel barrier layer 38.

[Manufacturing Method of Second Embodiment]
Next, a method for manufacturing the magnetoresistive element MTJ according to the second embodiment will be described with reference to FIGS.

  12 to 18 are cross-sectional views showing manufacturing steps of the magnetoresistive element MTJ according to the second embodiment.

  First, the steps of FIGS. 4 to 6 according to the first embodiment are performed. That is, the diameter of the first hole 35 is made larger than the diameter of the second hole 34 by performing wet etching on the first insulating layer 33 and the second insulating layer 32.

  Next, as shown in FIG. 12, the lower electrode 27 made of, for example, TiN is deposited by, eg, sputtering. At this time, for example, a sputtering method having a high vertical component (from the vertical direction or substantially vertical direction) is performed on the film surface using a collimator or the like. Thus, the lower electrode 27 is formed on the contact via 26 in the first hole 35, that is, on the bottom surface in the first hole 35 with a gap 60. At the same time, the lower electrode 27 is also formed on the second insulating layer 33 outside the through hole 36 so as to be separated from the contact via 26 in the first hole 35.

  Next, the memory layer 37 is deposited by the same sputtering method as that for the lower electrode 27, for example. Thereby, the memory layer 37 is formed on the lower electrode 27 in the first hole 35. At the same time, the memory layer 37 is also formed on the lower electrode 27 outside the through hole 36 so as to be separated from the lower electrode 27 in the first hole 35.

  Next, as shown in FIG. 13, the first insulating layer 32 and the second insulating layer 33 are isotropically etched, for example, by wet etching using a diluted hydrofluoric acid aqueous solution. At this time, since the upper surface of the second insulating layer 33 is covered with the lower electrode 27 and the memory layer 37, the side surfaces of the first insulating layer 32 and the second insulating layer 33 are etched. Thereby, the diameter of the 1st hole 35 and the diameter of the 2nd hole 34 become large, respectively.

  Next, as shown in FIG. 14, the storage layer 37 and the lower electrode 27 formed on the second insulating layer 33 outside the through hole 36 are removed. The removal of the memory layer 37 and the lower electrode 27 outside the through hole 36 is performed by, for example, an RF sputtering method (reverse sputtering method) using these as targets.

  Next, the tunnel barrier layer 38 is deposited by, for example, the same sputtering method as that for the lower electrode 27. At this time, the tunnel barrier layer 38 is formed by a sputtering method through the second hole 34 having a larger diameter than that at the time of forming the memory layer 37. For this reason, the tunnel barrier layer 38 is formed in a region larger than the formation region of the memory layer 37 in the first hole 35. In other words, the diameter of the tunnel barrier layer 38 is larger than the diameter of the storage layer 37.

  As a result, the tunnel barrier layer 38 is formed so as to cover the side surface and upper surface of the memory layer 37 and the side surface of the lower electrode 27 in the first hole 35. In other words, the tunnel barrier layer 38 is formed so as to be connected to the upper surface and the side surface of the memory layer 37 and the side surface of the lower electrode 27. Thereby, the edge part of the memory | storage layer 37 can be covered.

  At the same time, the tunnel barrier layer 38 is also formed on the second insulating layer 33 outside the through hole 36. At this time, the tunnel barrier layer 38 on the storage layer 37 in the first hole 35 and the tunnel barrier layer 38 on the second insulating layer 33 outside the through hole 36 are formed so as to be separated from each other.

  Next, as shown in FIG. 15, the reference layer 39 and the upper electrode 28 are sequentially deposited by, for example, the same sputtering method as that for the lower electrode 27. Thereby, the reference layer 39 and the upper electrode 28 are sequentially formed on the tunnel barrier layer 38 (on the upper surface) in the first hole 35. At this time, since the tunnel barrier layer 38 is also formed on the side surface of the memory layer 37, the reference layer 39 and the upper electrode 28 are formed with a diameter larger than that of the memory layer 37. The reference layer 39 and the upper electrode 28 may be formed so as to be connected to the side surface of the tunnel barrier layer 38.

  At the same time, the reference layer 39 and the upper electrode 28 are also formed on the tunnel barrier layer 38 outside the through hole 36. At this time, the reference layer 39 and the upper electrode 28 on the tunnel barrier layer 38 in the first hole 35 and the reference layer 39 and the upper electrode 28 on the tunnel barrier layer 38 outside the through hole 36 are separated from each other. Formed.

  Next, as shown in FIG. 16, the third insulating layer 40 is formed so as to fill the first hole 35 and the second hole 34 by, for example, a spin coating method. The third insulating layer 40 is made of, for example, a silicon oxide film or a silicon nitride film.

  Next, as shown in FIG. 17, the upper electrode 28, the reference layer 39, and the tunnel barrier layer 38 formed on the second insulating layer 33 outside the through hole 36 are removed by, for example, CMP. Further, a part on the upper side of the third insulating layer 40 is also removed.

  Next, as shown in FIG. 18, a resist pattern (not shown) is formed on the second insulating layer 33 (and the third insulating layer 40) by lithography. Using this resist pattern as a mask, wiring grooves 41 are formed in the first insulating layer 32, the second insulating layer 33, and the third insulating layer 40 by, for example, RIE. As a result, the upper surface of the upper electrode 28 is exposed at the bottom surface of the wiring groove 41.

  Next, as shown in FIG. 11, after forming a Cu seed layer (not shown) on the entire surface by, for example, sputtering, a Cu layer is formed on the Cu seed layer by, for example, an electrolytic plating technique. Thereafter, the Cu layer formed on the second insulating layer 33 outside the wiring groove 41 is removed, and the bit line BLA made of Cu is formed in the wiring groove 41.

  Thus, the magnetoresistive effect element MTJ according to the second embodiment, the wiring electrode connected to the magnetoresistive effect element MTJ, and the like are formed.

[Effects of Second Embodiment]
According to the second embodiment, the same effect as in the first embodiment can be obtained.

  Furthermore, in the second embodiment, after the storage layer 37 is formed, the diameter of the second hole 34 is increased. Then, the tunnel barrier layer 38 is formed so as to cover the upper surface and the side surface of the memory layer 37 in the first hole 35 by the sputtering method through the second hole 34 having a larger diameter than that at the time of forming the memory layer 37. As a result, the tunnel barrier layer 38 can be formed with a sufficient film thickness near the end of the memory layer 37 that is difficult to form. Accordingly, it is possible to suppress leakage between the storage layer 37 and the reference layer 39 formed thereafter, particularly in the vicinity of the end portion, and to insulate and separate them.

  By the way, as a method of forming the tunnel barrier layer so as to cover the memory layer formed in the hole, there is a method of forming a film by a sputtering method with an inclination instead of a vertical direction. However, when the tunnel barrier layer is formed by an inclined sputtering method, a sufficient film thickness cannot be ensured at the end of the memory layer, particularly at the side surface. For this reason, a leak may occur between the storage layer and the reference layer. This problem becomes more conspicuous as device miniaturization proceeds.

  On the other hand, in the second embodiment, it is possible to form the tunnel barrier layer 38 having a sufficient film thickness at the end, that is, the side surface of the memory layer 37. For this reason, it is possible to suppress leakage between the memory layer 37 and the reference layer 39 even if the element is further miniaturized.

<Third Embodiment>
A magnetoresistive element MTJ according to the third embodiment will be described with reference to FIGS. In the third embodiment, after forming the first hole 35 in the first insulating layer 32, the fourth insulating layer 51 with poor coverage is formed on the inner surface of the first hole 35. Thereby, the diameter of the first hole 35 is increased from the upper side toward the lower side. A magnetoresistive element MTJ is formed at the bottom of the first hole 35 by sputtering through the first hole 35. Thereby, an effect can be acquired similarly to 1st Embodiment. The magnetoresistive effect element MTJ according to the first embodiment will be described in detail below.

  Note that in the third embodiment, a description of the same points as in the above-described embodiments will be omitted, and different points will mainly be described.

[Structure of Third Embodiment]
First, the structure of the magnetoresistive element MTJ according to the third embodiment will be described with reference to FIG.

  FIG. 19 is a cross-sectional view showing the structure of the magnetoresistive element MTJ according to the third embodiment. In FIG. 19, the via 29 in FIG. 2 is omitted.

  As shown in FIG. 19, the third embodiment is different from the above embodiments in that the third insulating layer 40, the fourth insulating layer 40, and the fourth electrode 40 are formed on the side surfaces of the magnetoresistive element MTJ, the lower electrode 27, and the upper electrode 28. The insulating layer 51 and the first insulating layer 32 are formed.

  More specifically, the third insulating layer 40 is formed on the side surfaces of the magnetoresistive element MTJ, the lower electrode 27, and the upper electrode 28. In other words, the third insulating layer 40 is formed so as to surround the magnetoresistive element MTJ, the lower electrode 27, and the upper electrode 28. The third insulating layer 40 is made of, for example, a silicon oxide film or a silicon nitride film. The third insulating layer 40 is formed so that its film thickness increases from the upper side toward the lower side.

  A fourth insulating layer 51 is formed on the side surface of the third insulating layer 40. In other words, the fourth insulating layer 51 is formed so as to surround the third insulating layer 40. The fourth insulating layer 51 is made of, for example, a silicon oxide film, but is not limited thereto. The fourth insulating layer 51 may be composed of various insulating films such as a silicon nitride film, a silicon oxynitride film, or a high-k film. The fourth insulating layer 51 is formed so that its film thickness decreases from the upper side toward the lower side. Thereby, the integrated film thickness of the fourth insulating layer 51 and the third insulating layer 40 formed on the side surfaces of the magnetoresistive element MTJ, the lower electrode 27, and the upper electrode 28 is constant.

  A first insulating layer 32 is formed on the side surface of the fourth insulating layer 51. In other words, the first insulating layer 32 is formed so as to surround the fourth insulating layer 51.

  As described above, the fourth insulating layer 51 and the third insulating layer 40 are sequentially formed as side walls of the first hole 35 formed in the first insulating layer 32, and on the side surface of the third insulating layer 40 in the first hole 35. The magnetoresistive effect element MTJ, the lower electrode 27, and the upper electrode 28 are formed.

  A fourth insulating layer 51 is formed on the upper surface of the first insulating layer 32. The fourth insulating layer 51 on the side surface of the first insulating layer 32 and the fourth insulating layer 51 on the upper surface of the first insulating layer 32 may be connected to each other, or may be formed by bit lines BLA (wiring grooves 41). ) May be separated.

[Manufacturing Method of Third Embodiment]
Next, a manufacturing method of the magnetoresistive effect element MTJ according to the third embodiment will be described with reference to FIGS.

  20 to 25 are cross-sectional views illustrating manufacturing steps of the magnetoresistive element MTJ according to the third embodiment.

  First, the process of FIG. 4 in the first embodiment is performed. That is, a contact hole (not shown) is formed in the inter-wiring insulating layer 31, and a contact via 26 is formed in the contact hole.

  Next, as shown in FIG. 20, the first insulating layer 32 is formed on the inter-wiring insulating layer 31 in which the contact vias 26 are formed by, for example, PECVD. The first insulating layer 32 is made of, for example, a silicon oxide film.

  Next, a resist pattern (not shown) is formed on the first insulating layer 32 by lithography. Using this resist pattern as a mask, a first hole 35 penetrating from the upper surface to the lower surface is formed in the first insulating layer 32 by, for example, RIE.

  Next, the 4th insulating layer 51 is deposited by PECVD method, for example. At this time, the PECVD method is performed under the condition that the deposited film is diffusion-controlled. Thereby, the fourth insulating layer 51 with poor coverage is formed on the first insulating layer 32 and the substrate.

  More specifically, the fourth insulating layer 51 is formed on the side surface of the first insulating layer 32 in the first hole 35, on the upper surface of the substrate in the first hole 35, and outside the first hole 35. 32 is formed on the upper surface. The fourth insulating layer 51 is formed on the side surface of the first insulating layer 32 in the first hole 35 so that the film thickness decreases from the upper side toward the lower side. Thereby, the diameter of the first hole 35 is formed so as to increase from the upper side toward the lower side.

  The fourth insulating layer 51 is made of, for example, a silicon oxide film, but is not limited thereto. The fourth insulating layer 51 may be composed of various insulating films such as a silicon nitride film, a silicon oxynitride film, or a high-k film.

  Next, as shown in FIG. 21, the fourth insulating layer 51 formed on the upper surface of the substrate in the first hole 35 is removed by, for example, RIE, and the substrate is exposed. At this time, the fourth insulating layer 51 formed on the upper surface of the first insulating layer 32 outside the first hole 35 is also removed, but remains because the film is thick.

  Next, as shown in FIG. 22, the lower electrode 27 made of, eg, TiN is deposited by, eg, sputtering. At this time, for example, a sputtering method having a high vertical component (from the vertical direction or substantially vertical direction) is performed on the film surface using a collimator or the like. At this time, since the first hole 35 has a diameter that increases toward the lower side, the lower electrode 27 is not formed on the side surface of the fourth insulating layer 51 in the first hole 35. Accordingly, the lower electrode 27 is formed on the contact via 26 in the first hole 35, that is, on the bottom surface in the first hole 35. At the same time, the lower electrode 27 is also formed on the fourth insulating layer 51 outside the first hole 35 so as to be separated from the contact via 26 in the first hole 35.

  The lower electrode 27 is formed by a sputtering method through the uppermost portion of the first hole 35 having the smallest diameter. For this reason, the planar shape of the lower electrode 27 is approximately the same as the planar shape of the uppermost portion of the first hole 35. Further, the diameter of the lower electrode 27 is approximately the same as the diameter of the uppermost portion of the first hole 35.

  Next, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are sequentially deposited by, for example, the sputtering method similar to that for the lower electrode 27. At this time, since the first hole 35 has a diameter that increases toward the lower side, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are formed on the fourth insulating layer 51 in the first hole 35. It is not formed on the side. As a result, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are sequentially formed on the lower electrode 27 (on the upper surface) in the first hole 35. At the same time, the memory layer 37, the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 are separated from the lower electrode 27 outside the first hole 35 and from the lower electrode 27 inside the first hole 35, respectively. To be formed.

  Next, as shown in FIG. 23, the third insulating layer 40 is formed so as to fill the first hole 35 by, for example, a spin coating method. The third insulating layer 40 is made of, for example, a silicon oxide film or a silicon nitride film.

  Next, as shown in FIG. 24, the upper electrode 28, the reference layer 39, the tunnel barrier layer 38, the memory layer 37, and the lower electrode formed on the fourth insulating layer 51 outside the first hole 35 by, for example, CMP. 27 is removed. Further, a part on the upper side of the third insulating layer 40 is also removed.

  Next, as shown in FIG. 25, a resist pattern (not shown) is formed on the fourth insulating layer 51 (and the third insulating layer 40) by lithography. Using this resist pattern as a mask, wiring grooves 41 are formed in the fourth insulating layer 51, the first insulating layer 32, and the third insulating layer 40 by, for example, RIE. As a result, the upper surface of the upper electrode 28 is exposed at the bottom surface of the wiring groove 41.

  Next, as shown in FIG. 19, after forming a Cu seed layer (not shown) on the entire surface by, for example, sputtering, a Cu layer is formed on the Cu seed layer by, for example, an electrolytic plating technique. Thereafter, the Cu layer formed on the fourth insulating layer 51 outside the wiring trench 41 is removed, and the bit line BLA made of Cu is formed in the wiring trench 41.

  Thus, the magnetoresistive effect element MTJ according to the third embodiment, the wiring electrode connected to the magnetoresistive effect element MTJ, and the like are formed.

[Effect of the third embodiment]
According to the third embodiment, after forming the first hole 35 in the first insulating layer 32, the fourth insulating layer 51 with poor coverage is formed on the inner surface of the first hole 35. Thereby, the diameter of the first hole 35 is increased from the upper side toward the lower side. Then, the magnetoresistive effect element MTJ is formed at the bottom in the first hole 35 by the sputtering method through the top of the first hole 35 having the smallest diameter. Thereby, the effect similar to 1st Embodiment can be acquired.

  In the third embodiment, the first hole 35 is formed in the first insulating layer 32 with a critical dimension of lithography technology, and then the fourth insulating layer 51 is formed on the surface, thereby reducing the diameter of the first hole 35. Smaller than the critical dimension of lithography technology. That is, it is possible to form a magnetoresistive effect element MTJ having a critical dimension or less of the lithography technique.

<Fourth Embodiment>
A magnetoresistive element MTJ according to the fourth embodiment will be described with reference to FIGS. 26 to 33. The fourth embodiment is a modification of the third embodiment. After the storage layer 37 is formed, the diameter of the first hole 35 is increased, so that the tunnel barrier layer 38 formed thereafter forms the storage layer. It is an example which covers the upper surface and side surface of 37. That is, the fourth embodiment is a combination of the second embodiment and the third embodiment. The magnetoresistive effect element MTJ according to the fourth embodiment will be described in detail below.

  Note that in the fourth embodiment, a description of the same points as in the above-described embodiments will be omitted, and different points will mainly be described.

[Structure of Fourth Embodiment]
First, the structure of the magnetoresistive element MTJ according to the fourth embodiment will be described with reference to FIG.

  FIG. 26 is a cross-sectional view showing the structure of the magnetoresistive element MTJ according to the fourth embodiment. In FIG. 26, the via 29 in FIG. 2 is omitted.

  As shown in FIG. 26, the fourth embodiment is different from the above embodiments in that the tunnel barrier layer 38 is formed so as to cover the upper surface and the side surface of the storage layer 37 and the side surface of the lower electrode 27, and magnetically. The third insulating layer 40, the fourth insulating layer 51, and the first insulating layer 32 are formed so as to surround the resistance effect element MTJ, the lower electrode 27, and the upper electrode 28.

  More specifically, the lower electrode 27 is formed on the contact via 26 formed in the inter-wiring insulating layer 31. A memory layer 37 is formed on the lower electrode 27 (on the upper surface). A tunnel barrier layer 38 is formed so as to cover the upper and side surfaces of the storage layer 37 and the side surface of the lower electrode 27. In other words, the tunnel barrier layer 38 is formed so as to be connected to the upper surface and the side surface of the memory layer 37 and the side surface of the lower electrode 27.

  A reference layer 39 is formed on the tunnel barrier layer 38 (on the upper surface). At this time, since the tunnel barrier layer 38 is also formed on the side surface of the storage layer 37, the reference layer 39 is formed with a diameter larger than that of the storage layer 37. Further, the upper electrode 28 is formed on the reference layer 39 (on the upper surface).

  A third insulating layer 40 is formed so as to surround the magnetoresistive element MTJ, the lower electrode 27, and the upper electrode 28. That is, the third insulating layer 40 is formed on the side surfaces of the tunnel barrier layer 38, the reference layer 39, and the upper electrode 28 that cover the side surface of the memory layer 37. The third insulating layer 40 is formed so that its film thickness increases from the upper side toward the lower side.

  A fourth insulating layer 51 is formed on the side surface of the third insulating layer 40. In other words, the fourth insulating layer 51 is formed so as to surround the third insulating layer 40. The fourth insulating layer 51 is formed so that its film thickness decreases from the upper side toward the lower side. Thereby, the integrated film thickness of the fourth insulating layer 51 and the third insulating layer 40 formed on the side surfaces of the magnetoresistive element MTJ, the lower electrode 27, and the upper electrode 28 is constant.

  A first insulating layer 32 is formed on the side surface of the fourth insulating layer 51. In other words, the first insulating layer 32 is formed so as to surround the fourth insulating layer 51.

[Manufacturing Method of Fourth Embodiment]
Next, a manufacturing method of the magnetoresistive element MTJ according to the fourth embodiment will be described with reference to FIGS.

  27 to 33 are cross-sectional views showing manufacturing steps of the magnetoresistive element MTJ according to the fourth embodiment.

  First, the steps of FIGS. 20 and 21 in the third embodiment are performed. That is, after forming the first hole 35 in the first insulating layer 32, the fourth insulating layer 51 with poor coverage is formed on the side surface of the first insulating layer 32 and on the upper surface of the first insulating layer 32 outside the first hole 35. It is formed.

  Next, as shown in FIG. 27, the lower electrode 27 made of, eg, TiN is deposited by, eg, sputtering. At this time, for example, a sputtering method having a high vertical component (from the vertical direction or substantially vertical direction) is performed on the film surface using a collimator or the like. Accordingly, the lower electrode 27 is formed on the contact via 26 in the first hole 35, that is, on the bottom surface in the first hole 35. At the same time, the lower electrode 27 is also formed on the fourth insulating layer 51 outside the first hole 35 so as to be separated from the contact via 26 in the first hole 35.

  Next, the memory layer 37 is deposited by the same sputtering method as that for the lower electrode 27, for example. At this time, since the first hole 35 has a diameter that increases toward the lower side, the memory layer 37 is not formed on the side surface of the fourth insulating layer 51 in the first hole 35. As a result, the memory layer 37 is formed on the lower electrode 27 (on the upper surface) in the first hole 35. At the same time, the memory layer 37 is formed on the lower electrode 27 outside the first hole 35 so as to be separated from the lower electrode 27 inside the first hole 35.

  Next, as shown in FIG. 28, the fourth insulating layer 51 is isotropically etched by, for example, wet etching using a diluted hydrofluoric acid aqueous solution. At this time, since the upper surface of the fourth insulating layer 51 is covered with the lower electrode 27 and the memory layer 37, the side surface of the fourth insulating layer 51 is etched. Thereby, the diameter of the 1st hole 35 becomes large.

  Next, as shown in FIG. 29, the memory layer 37 and the lower electrode 27 formed on the fourth insulating layer 51 outside the first hole 35 are removed.

  Next, the tunnel barrier layer 38 is deposited by, for example, the same sputtering method as that for the lower electrode 27. At this time, the tunnel barrier layer 38 is formed by a sputtering method through the first hole 35 having a larger diameter than that at the time of forming the memory layer 37. For this reason, the tunnel barrier layer 38 is formed in a region larger than the formation region of the memory layer 37 in the first hole 35.

  As a result, the tunnel barrier layer 38 is formed so as to cover the side surface and upper surface of the memory layer 37 and the side surface of the lower electrode 27 in the first hole 35. In other words, the tunnel barrier layer 38 is formed so as to be connected to the upper surface and the side surface of the memory layer 37 and the side surface of the lower electrode 27. Thereby, the edge part of the memory | storage layer 37 can be covered.

  At the same time, the tunnel barrier layer 38 is also formed on the fourth insulating layer 51 in the first hole 35. At this time, the tunnel barrier layer 38 on the storage layer 37 in the first hole 35 and the tunnel barrier layer 38 on the fourth insulating layer 51 outside the first hole 35 are formed so as to be separated from each other.

  Next, as shown in FIG. 30, the reference layer 39 and the upper electrode 28 are sequentially deposited by, for example, the same sputtering method as that of the lower electrode 27. Thereby, the reference layer 39 and the upper electrode 28 are sequentially formed on the tunnel barrier layer 38 (on the upper surface) in the first hole 35. At this time, since the tunnel barrier layer 38 is also formed on the side surface of the memory layer 37, the reference layer 39 and the upper electrode 28 are formed with a diameter larger than that of the memory layer 37.

  At the same time, the reference layer 39 and the upper electrode 28 are also formed on the tunnel barrier layer 38 outside the first hole 35. At this time, the reference layer 39 and the upper electrode 28 on the tunnel barrier layer 38 in the first hole 35 and the reference layer 39 and the upper electrode 28 on the tunnel barrier layer 38 outside the first hole 35 are separated from each other. Formed as follows.

  Next, as shown in FIG. 31, the third insulating layer 40 is formed so as to fill the first hole 35 by, for example, a spin coating method. The third insulating layer 40 is made of, for example, a silicon oxide film or a silicon nitride film.

  Next, as shown in FIG. 32, the upper electrode 28, the reference layer 39, and the tunnel barrier layer 38 formed on the fourth insulating layer 51 outside the first hole 35 are removed by CMP, for example. Further, a part on the upper side of the third insulating layer 40 is also removed.

  Next, as shown in FIG. 33, a resist pattern (not shown) is formed on the fourth insulating layer 51 (and the third insulating layer 40) by lithography. Using this resist pattern as a mask, wiring grooves 41 are formed in the fourth insulating layer 51, the first insulating layer 32, and the third insulating layer 40 by, for example, RIE. As a result, the upper surface of the upper electrode 28 is exposed at the bottom surface of the wiring groove 41.

  Next, as shown in FIG. 26, after forming a Cu seed layer (not shown) on the entire surface by, for example, sputtering, a Cu layer is formed on the Cu seed layer by, for example, an electrolytic plating technique. Thereafter, the Cu layer formed on the second insulating layer 33 outside the wiring groove 41 is removed, and the bit line BLA made of Cu is formed in the wiring groove 41.

  Thus, the magnetoresistive effect element MTJ according to the fourth embodiment, the wiring electrode connected to the magnetoresistive effect element MTJ, and the like are formed.

[effect]
According to the fourth embodiment, it is possible to obtain the same effects as those of the second embodiment and the third embodiment.

  In each of the above-described embodiments, an example in which the present invention is applied to the magnetoresistive element MTJ of the MRAM has been shown, but the present invention is not limited to this. Each of the above embodiments can be applied to a variable resistance element such as a ReRAM (Resistance Random Access Memory) or a PRAM (Phase-change Random Access Memory) as long as it is an element formed in a cylindrical shape.

  In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention when it is practiced. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

  26 ... Contact via, 31 ... Inter-wiring insulating layer, 32 ... First insulating layer, 33 ... Second insulating layer, 34 ... Second hole, 35 ... First hole, 37 ... Memory layer, 38 ... Tunnel barrier layer, 39 ... Reference layer, 40 ... Third insulating layer

Claims (7)

Forming a first insulating layer on the substrate;
Forming a second insulating layer on the first insulating layer;
Forming a second hole penetrating the second insulating layer and then forming a first hole connected to the second hole and penetrating the first insulating layer;
Processing the first insulating layer and the second insulating layer such that the diameter of the first hole is larger than the diameter of the second hole;
Forming a first magnetic layer on the substrate in the first hole and on the second insulating layer outside the first hole and the second hole so as to be separated from each other;
Processing the first insulating layer and the second insulating layer such that the diameter of the first hole and the diameter of the second hole are increased;
Removing the first magnetic layer outside the first hole and the second hole;
The first magnetic layer in the first hole so as to be separated from each other on the first magnetic layer in the first hole and on the second insulating layer outside the first hole and the second hole. Forming a tunnel barrier layer to cover the layer;
Forming a second magnetic layer on the tunnel barrier layer in the first hole and on the tunnel barrier layer outside the first hole and the second hole so as to be separated from each other;
Removing the second magnetic layer and the tunnel barrier layer outside the first hole and the second hole;
A method of manufacturing a magnetoresistive effect element comprising:   2. The method of manufacturing a magnetoresistive element according to claim 1, wherein the first insulating layer is made of a silicon oxynitride film, and the second insulating layer is made of a silicon oxide film.   3. The method of manufacturing a magnetoresistive element according to claim 1, wherein the processing of the first insulating layer and the second insulating layer is performed by wet etching. 4.   4. The method of manufacturing a magnetoresistive element according to claim 1, wherein the tunnel barrier layer is formed by a sputtering method from a direction perpendicular to a film surface. 5.   The diameter of the second magnetic layer formed on the tunnel barrier layer in the first hole is larger than the diameter of the first magnetic layer formed on the substrate in the first hole. The manufacturing method of the magnetoresistive effect element of any one of Claim 1 thru | or 4.   6. The method according to claim 1, further comprising a step of forming a third insulating layer so as to fill the first hole and the second hole after forming the second magnetic layer. A method for producing a magnetoresistive element according to claim 1.   The method of manufacturing a magnetoresistive effect element according to claim 6, wherein the third insulating layer is formed by a coating method.

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