JP2013196711A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve efficiency of repairing failed memory cells included in a memory cell array.SOLUTION: A semiconductor device includes: a memory cell array 101; an optical fuse circuit 141 and electric fuse circuit 142 that store addresses of failed memory cells; and a replacement address analysis circuit 146 that writes row addresses or column addresses of the failed memory cells to the electric fuse circuit 142. When a first operation mode is selected, the replacement address analysis circuit 146 is enabled to write both the row address and column address to the electric fuse circuit 142. When a second operation mode is selected, the circuit is enabled to write one of the row address and column address to the electric fuse circuit 142 and disabled to write the other address. Thus, even when either all redundant word lines or all redundant bit lines are used up, a correct repair can be made.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device capable of replacing a defective memory cell with a redundant cell and a manufacturing method thereof.

  A semiconductor memory device typified by a DRAM (Dynamic Random Access Memory) includes a large number of memory cells, but it is inevitable that some memory cells become defective due to the influence of manufacturing conditions and the like. In order to ship such a semiconductor memory device as a non-defective product, a redundant repair technique for replacing a defective memory cell with a redundant cell is essential.

  In the redundancy repair technique, first, an operation test is performed on a semiconductor memory device in a wafer state, and an address (defective address) of a defective memory cell is detected. Then, the detected address is programmed into an optical fuse provided in the semiconductor memory device. An optical fuse is a fuse that can be cut by irradiation with a laser beam, for example, and once cut, it cannot be returned to a conductive state, so that information can be stored in a nonvolatile manner and irreversibly. When an access is requested to the address programmed in the optical fuse, an alternative access is made to a redundant cell (alternative cell) instead of a defective memory cell, thereby relieving the address. It will be.

  Since defects in memory cells mainly occur at the wafer stage (a manufacturing process for forming a plurality of circuits on a wafer, so-called pre-process), most defects are remedied by replacement using an optical fuse. However, after replacement using an optical fuse, a new defect may occur in a later process due to a thermal load during packaging. Such defects can no longer be remedied using optical fuses.

  As methods for solving this problem, methods described in Patent Documents 1 to 3 have been proposed. In particular, Patent Documents 2 and 3 propose semiconductor devices capable of using both replacement using an optical fuse and replacement using an electric fuse.

  However, since a high-speed operation is required for a tester used in a subsequent process, it is not realistic to mount a large-capacity analysis memory like a low-speed tester used in the wafer stage. For this reason, in order to analyze a defect occurring in a subsequent process on the tester side, it is necessary to reduce the number of semiconductor devices that can be tested at the same time, and there is a problem that the production efficiency is greatly reduced.

  On the other hand, in Patent Document 4, when a plurality of detected defective memory cells are located on the same line, a method of compressing the amount of information related to a defective memory cell by determining line defects rather than individual bit defects. Is described. However, in the method described in Patent Document 4, since only a plurality of bit defects are handled as line defects, the amount of information finally obtained can be reduced, but the work area required for address analysis, that is, The storage capacity of the analysis memory can hardly be reduced. This is because, depending on the order of defective memory cells to be detected, it is necessary to hold a lot of information regarding bit defects until it is determined as a line defect.

Japanese Patent Laid-Open No. 11-16385 JP 2002-25289 A JP 2007-328914 A JP 2001-52497 A

  In order to solve the problems of the techniques described in Patent Documents 1 to 4, a semiconductor memory device having an analysis circuit and an analysis memory for analyzing a defect generated in a subsequent process has been devised. In such a semiconductor memory device, it is possible to analyze a defect generated in a subsequent process internally, so that it is not necessary to mount a large capacity analysis memory in the tester. A defective memory cell generated in a later process can be remedied by replacing a corresponding word line with a redundant word line or replacing a corresponding bit line with a redundant bit line. The former relief method is called “row relief”, and the latter relief method is called “column relief”.

  The selection of row relief or column relief is determined by the algorithm of the analysis circuit. For example, when a plurality of defective memory cells exist on the same word line, row relief is selected, and a plurality of rows are selected on the same bit line. If there is a defective memory cell, column relief is selected. In such an algorithm, there are cases where row relief is selected even when all the redundant word lines are used up, or column relief is selected even when all the redundant bit lines are used up. Therefore, there is a possibility that the remedy is impossible although the remedy is actually possible.

  In particular, in the configuration in which the same redundant word line can be used in both row relief in the pre-process and the post-process, and the same redundant bit line can be used in column relief in the pre-process and the post-process. Since there are cases where the redundant word lines or redundant bit lines are used up by the primary repair in the previous process or there are almost no remaining numbers, there is a high possibility that the secondary repair cannot be performed in the subsequent process by the above algorithm. For this reason, in the semiconductor memory device capable of relieving a defect generated in a subsequent process, there is a room for further improving the relieving efficiency. This applies not only to semiconductor memory devices such as DRAMs, but also to all semiconductor devices incorporating a memory cell array.

  A semiconductor device according to the present invention includes a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells selected by these, and a word line corresponding to a predetermined defective memory cell among the plurality of memory cells. A fuse circuit for storing a row address and a column address of a bit line corresponding to another defective memory cell among the plurality of memory cells, and a word line specified by the row address stored in the fuse circuit are replaced. A plurality of redundant word lines, a plurality of redundant bit lines for replacing a bit line specified by the column address stored in the fuse circuit, and the row address and the column address in the fuse circuit. A replacement address analysis circuit for writing, and the fuse circuit is an optical fuse circuit When the first operation mode is selected, the replacement address analysis circuit is permitted to write both the row address and the column address to the electrical fuse circuit. When the second operation mode is selected, one of writing of the row address and writing of the column address to the electric fuse circuit is permitted and the other is prohibited.

  A method of manufacturing a semiconductor device according to the present invention includes a step of performing a first operation test on a memory device in a wafer state, and analyzing an address of a first defective memory cell detected by the first operation test. Identifying the first defective word line and the first defective bit line, and the first defective word line and the first defective bit line in the wafer state respectively in the first redundant word line and the first defective bit line. A redundant bit line, a step of taking out a memory chip in which the memory device is separated by cutting the wafer, and packaging one or more semiconductor chips including at least the memory chip. A step of performing a second operation test on the packaged semiconductor device, and the second operation test is detected. Generating a failure analysis data by analyzing the address of the second failure memory cell, and setting a second redundancy word line corresponding to the second failure memory cell to a second redundancy based on the failure analysis data. Selecting whether to replace with a word line or to replace a second defective bit line corresponding to the second defective memory cell with a second redundant bit line; and Replacing each of the two defective bit lines with a second redundant word line or a second redundant bit line, and in the selecting step, when the first operation mode is selected, When both the replacement by the second redundant word line and the replacement by the second redundant bit line are enabled and the second operation mode is selected, the replacement by the second redundant word line and the replacement First While the enable replacement of by redundant bit lines, characterized by disabling the other.

  According to the present invention, one of the row relief and the column relief can be invalidated by selecting the operation mode, so that one of the redundant word line and the redundant bit line is used up or there is almost no remaining number. Even in such a case, the replacement using the other of the redundant word line and the redundant bit line enables correct repair. As a result, it is possible to increase the efficiency of repairing defects generated in the subsequent process.

1 is a block diagram showing a configuration of a semiconductor device 100 according to a preferred first embodiment of the present invention. It is a figure for demonstrating low relief. It is a figure for demonstrating column relief. 3 is a flowchart schematically showing a manufacturing process of the semiconductor device 100. 5 is a block diagram showing a configuration of a replacement address analysis circuit 146. FIG. 5 is a flowchart for explaining the operation of a replacement address analysis circuit 146. It is a figure for demonstrating the selection method of the relief address RADD. It is a block diagram which shows the structure of the replacement address analysis circuit 146a by a modification. FIG. 5 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to a preferred second embodiment of the present invention. 2 is a block diagram showing a circuit configuration of a main part of the semiconductor device 10. FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 100 according to a preferred first embodiment of the present invention.

  Of the constituent elements shown in FIG. 1, the constituent elements other than the DFT circuit 145 and the replacement address analyzing circuit 146 are substantially the same as the constituent elements shown in FIG. 1 of US Patent Application 13 / 200,649 incorporated herein by reference. Have the same configuration.

  FIG. 2 is a diagram for explaining row relief.

  As shown in FIG. 2, the optical fuse circuit 141 includes optical relief sets LFR (0) to LFR (N) for row relief. These N + 1 optical fuse sets LFR (0) to LFR (N) correspond to the redundant word lines RWL (0) to RWL (N) in the row redundant circuit 102, respectively. This means that N + 1 defective word lines can be replaced with redundant word lines by row relief using the optical fuse circuit 141. On the other hand, the electric fuse circuit 142 is provided with electric relief sets AFR (Nx) to AFR (N) for row relief. These x + 1 electric fuse sets AFR (N−x) to AFR (N) correspond to redundant word lines RWL (N−x) to RWL (N) in the row redundant circuit 102, respectively. This means that x + 1 defective word lines can be replaced with redundant word lines by row relief using the electrical fuse circuit 142.

  The defective addresses stored in the optical fuse sets LFR (0) to LFR (N) are transferred to the latch circuit 151 included in the repair control circuit 140. The defective addresses stored in the electrical fuse sets AFR (N−x) to AFR (N) are transferred to the latch circuit 152 included in the repair control circuit 140. Among these, the output of the latch circuit 151 corresponding to the optical fuse sets LFR (0) to LFR (N-1-x) is supplied as it is to the corresponding determination circuit 104a in the row decoder 104. On the other hand, regarding the output of the latch circuit 151 corresponding to the optical fuse sets LFR (Nx) to LFR (N), the latch circuit 152 corresponding to the electrical fuse sets AFR (Nx) to AFR (N) Along with the output, it is supplied to the corresponding selection circuit 153. The selection circuit 153 selects either the output of the latch circuit 151 or the output of the latch circuit 152, and supplies the output of the selected latch circuit to the corresponding determination circuit 104a in the row decoder 104. The function of the determination circuit 104a will be described later.

  Thus, the redundant word lines RWL (0) to RWL (N-1-x) correspond only to the optical fuse set LFR, whereas the redundant word lines RWL (N−x) to RWL (N) The optical fuse set LFR and the electric fuse set AFR are both supported. Therefore, among the redundant word lines RWL (N−x) to RWL (N), those already used by replacement using the optical fuse set LFR cannot be used for replacement using the electrical fuse set AFR. .

  In the present embodiment, the optical fuse sets LFR (Nx) to LFR (N) and the electrical fuse sets AFR (Nx) to AFR (N) are prevented from competing as much as possible with the optical fuse sets LFR (0) to LFR ( N) and the use order of the electric fuse sets AFR (Nx) to AFR (N) are reversed. Specifically, the optical fuse sets LFR (0) to LFR (N) are preferentially used from the one corresponding to the redundant word line RWL having a smaller assigned number. That is, the optical fuse set LFR (0) is used in order. The order of use of the optical fuse sets LFR (0) to LFR (N) is indicated by an arrow LF in FIG. On the other hand, the electrical fuse sets AFR (N−x) to AFR (N) are preferentially used from the one corresponding to the redundant word line RWL having a large assigned number. That is, the electric fuse set AFR (N) is used in order. The order of use of the electrical fuse sets AFR (N−x) to AFR (N) is indicated by an arrow AF in FIG. Thereby, the competition between the optical fuse sets LFR (Nx) to LFR (N) and the electrical fuse sets AFR (Nx) to AFR (N) is minimized.

  However, when more than Nx redundant word lines are used by replacement using the optical fuse set LFR, redundant word lines that can be used by replacement using the electrical fuse set AFR are increased by the amount exceeding Nx. The number decreases. In an extreme case, when all N + 1 redundant word lines are used by replacement using the optical fuse set LFR, row repair using the electrical fuse set AFR can no longer be performed.

  FIG. 3 is a diagram for explaining column relief.

  As shown in FIG. 3, the optical fuse circuit 141 is provided with column fuse optical fuse sets LFC (0) to LFC (M). These M + 1 optical fuse sets LFC (0) to LFC (M) correspond to redundant column selection lines RYS (0) to RYS (M) in the column control circuit 107, respectively. Redundant column selection lines RYS (0) to RYS (M) are signal lines for selecting redundant bit lines RBL (0) to RBL (M) in the column redundancy circuit 103, respectively.

  This means that M + 1 defective bit lines can be replaced with redundant bit lines by column relief using the optical fuse circuit 141. On the other hand, the electric fuse circuit 142 is provided with column fuse electric fuse sets AFC (My) to AFC (M). These y + 1 electrical fuse sets AFC (My) to AFC (M) correspond to the redundant bit lines RBL (My) to RBL (M) in the column redundant circuit 103, respectively. This means that y + 1 defective bit lines can be replaced with redundant bit lines by column relief using the electrical fuse circuit 142.

  The defective addresses stored in the optical fuse sets LFC (0) to LFC (M) are transferred to the latch circuit 154 included in the repair control circuit 140. Further, the defective address stored in the electrical fuse sets AFC (My) to AFC (M) is transferred to the latch circuit 155 included in the repair control circuit 140. Among these, the output of the latch circuit 154 corresponding to the optical fuse sets LFC (0) to LFC (M-1-y) is supplied as it is to the corresponding determination circuit 105a in the column decoder 105. On the other hand, regarding the output of the latch circuit 154 corresponding to the optical fuse sets LFC (My) to LFC (M), the latch circuit 155 corresponding to the electrical fuse sets AFC (My) to AFC (M) Along with the output, it is supplied to a corresponding selection circuit 156. The selection circuit 156 selects either the output of the latch circuit 154 or the output of the latch circuit 155 and supplies the output of the selected latch circuit to the corresponding determination circuit 105 a in the column decoder 105. The function of the determination circuit 105a will be described later.

  Thus, the redundant bit lines RBL (0) to RBL (M-1-y) correspond only to the optical fuse set LFC, whereas the redundant bit lines RBL (My) to RBL (M) Both optical fuse set LFC and electric fuse set AFC are supported. Accordingly, among the redundant bit lines RBL (My) to RBL (M), those already used by replacement using the optical fuse set LFC cannot be used for replacement using the electrical fuse set AFC. .

  Also in the column relief, the optical fuse sets LFC (0) to LFC (0) are used so that the optical fuse sets LFC (My) to LFC (M) and the electric fuse sets AFC (My) to AFC (M) do not compete as much as possible. The order of use of M) and the order of use of the electrical fuse sets AFC (My) to AFC (M) are reversed. Specifically, the optical fuse sets LFC (0) to LFC (M) are preferentially used from the one corresponding to the redundant bit line RBL having a smaller assigned number. That is, the optical fuse set LFC (0) is used in order. The order of use of the optical fuse sets LFC (0) to LFC (M) is indicated by an arrow LF in FIG. On the other hand, the electrical fuse sets AFC (My) to AFC (M) are preferentially used from the one corresponding to the redundant bit line RBL having a large assigned number. That is, the electric fuse set AFC (M) is used in order. The order of use of the electrical fuse sets AFC (My) to AFC (M) is indicated by an arrow AF in FIG. Thereby, the competition between the optical fuse sets LFC (My) to LFC (M) and the electrical fuse sets AFC (My) to AFC (M) is minimized.

  However, when more than My redundancy bits are used by replacement using the optical fuse set LFC, the redundancy bit lines that can be used by replacement using the electrical fuse set AFC are increased by the amount exceeding My. The number decreases. In an extreme case, when all M + 1 redundant bit lines are used by replacement using the optical fuse set LFC, column repair using the electric fuse set AFC can no longer be performed.

  As shown in FIG. 1, the replacement address analysis circuit 146 is supplied with mode signals RMODE and CMODE from the DFT circuit 145. The mode signal RMODE is activated when the row relief mode is selected. When the row relief mode is selected, only the row relief is permitted for the replacement address analysis circuit 146, and the column relief is prohibited. . The row relief mode is selected when all the redundant bit lines RBL are used up by the optical fuse set LFC shown in FIG. 2 or when there are almost no remaining redundant bit lines RBL.

  The mode signal CMODE is a signal activated when the column relief mode is selected. When the column relief mode is selected, only column relief is permitted for the replacement address analysis circuit 146, and row relief is prohibited. Is done. The column relief mode is selected when all the redundant word lines RWL are used up by the optical fuse set LFR shown in FIG. 3 or when there are almost no remaining redundant word lines RWL.

  On the other hand, when neither of the mode signals RMODE and CMODE is activated, the normal mode is selected, and both the row relief and the column relief are permitted for the replacement address analysis circuit 146.

  The method for actually selecting the mode is not particularly limited, and the mode may be automatically selected from the usage status of the optical fuse circuit 141, or the usage status of the optical fuse circuit 141 is estimated from the process maturity of the lot. May be selected by the operator.

  FIG. 4 is a flowchart schematically showing the manufacturing process of the semiconductor device 100 according to the present embodiment.

  First, a wafer-state memory device is manufactured by the previous process (diffusion process) (step S1), and an operation test is performed on the wafer-state memory device (step S2). The operation test in step S2 is a test for detecting the address of a defective memory cell in a wafer state, and is executed in parallel on a plurality of memory devices using a low-speed tester equipped with a large-capacity analysis memory. The address of the defective memory cell thus detected is analyzed in the tester, and thereby the defective word line and the defective bit line are specified (step S3). Then, the address of the defective word line and the address of the defective bit line are written in the optical fuse circuit 141 using a laser trimmer. As a result, the defective word line and the defective bit line are replaced with the redundant word line and the redundant bit line (step S4). As described above, the memory device in the wafer state subjected to the primary relief is completed.

  Next, by dicing the wafer, a memory chip in which the memory device is separated is taken out (step S5), and packaged to obtain the semiconductor device 100 (step S6). Steps S5 and S6 are processes belonging to a so-called post-process, and a new defective memory cell may be generated due to a thermal load during packaging. Since it is after packaging, such a defect can no longer be remedied using the optical fuse circuit 141. Defects after packaging are remedied using the electrical fuse circuit 142 as follows.

  First, an operation test is performed on the packaged semiconductor device 100 to detect an address of a defective memory cell (step S7). Such a test is performed by writing and reading test data in a state where the test mode is set in the mode register 125, and outputting the obtained determination signal P / F to the analysis circuit 143. Specifically, when the determination signal P / F indicates a failure, the defective word line and the defective bit line are specified by referring to the accessed address (step S8). At this time, the analysis circuit 143 updates the error pattern information and the error address information every time a defective memory cell is detected. Error pattern information and error address information are stored in the analysis memory 144.

  Then, the finally obtained error pattern information and error address information are analyzed by the replacement address analysis circuit 146, thereby specifying the address of the defective word line and the address of the defective bit line to be replaced (step S9). Then, by writing the specified address into the electric fuse circuit 142, the defective word line and the defective bit line are replaced with the redundant word line and the redundant bit line (step S10). Thus, the semiconductor device 100 in which the secondary relief is completed is completed.

  Thus, in the present embodiment, primary relief is performed in the wafer state, and secondary relief is performed after packaging. Since the redundant word lines and redundant bit lines provided in the semiconductor device 100 can be used for primary repair or secondary repair, it is not necessary to provide a redundant circuit dedicated to secondary repair. Moreover, in the secondary remedy, since the address analysis of the defective memory cell is performed using the analysis circuit 143 and the analysis memory 144 provided in the semiconductor device 100, the external tester has these functions. There is no need to let

  Further, in secondary relief, error pattern information and error address information are updated each time a defective memory cell is detected, so that the analysis is performed in comparison with the method of recording the address of the defective memory cell as it is each time. The storage capacity required for the memory 144 is greatly reduced. In addition, if all the redundant word lines are used up by primary repair, or if there are almost no remaining redundant word lines, correct repair can be performed by selecting the column repair mode in the secondary repair. . On the other hand, if all the redundant bit lines are used up by the primary repair, or if there are almost no remaining redundant bit lines, the repair can be performed correctly by selecting the row repair mode at the time of the secondary repair. .

  Next, the replacement address analysis circuit 146 will be described.

  FIG. 5 is a block diagram showing a configuration of the replacement address analysis circuit 146.

  As shown in FIG. 5, the replacement address analysis circuit 146 reads the failure analysis data FMI <0> to FMI <P> stored in the analysis memory 144, and specifies a repair address arithmetic circuit based on the read failure analysis data FMI <0> to FMI <P>. 161. The defect analysis data FNI <0> to FMI <P> are substantially the same as the FMI <0> to FMI <N> described in FIG. 4 of US patent application 13 / 200,649 incorporated herein by reference. And The failure analysis data FMI <0> to FMI <P> are read by activating the read signal FMread, and the relief address calculation circuit 161 receives the error pattern information D of the read failure analysis data FMI <j>. By referencing, it is determined whether to perform row relief or column relief. Whether to perform row relief or column relief is performed by supplying a selection signal X / Y from the relief address calculation circuit 161 to the selection circuit 162.

  The selection circuit 162 activates the row relief strobe signal XSTB when the selection signal X / Y indicates row relief, and selects the column relief strobe signal YSTB when the selection signal X / Y indicates column relief. To activate. The row relief strobe signal XSTB and the column relief strobe signal YSTB are supplied to the electric fuse circuit 142 and to the row relief remaining number counter 163 and the column relief remaining number counter 164, respectively. The row relief remaining number counter 163 is a counter that indicates the remaining number of electrical fuse sets AFR included in the electrical fuse circuit 142. The column repair remaining number counter 164 is a counter indicating the remaining number of the electrical fuse set AFC included in the electrical fuse circuit 142.

  The count value of the row relief remaining number counter 163 is decremented every time the row relief strobe signal XSTB is activated, and when the count value becomes zero, the row overflow signal ROVFa is activated to a high level. Similarly, the count value of the column repair remaining number counter 164 is decremented every time the column repair strobe signal YSTB is activated, and the column overflow signal COVFa is activated to a high level when the count value becomes zero.

  The row overflow signal ROVFa and the column overflow signal COVFa are respectively supplied to one input node of the OR gate circuits G1 and G2. Mode signals CMODE and RMODE are supplied to the other input nodes of the OR gate circuits G1 and G2, respectively.

  When the row overflow signal ROVF is output from the OR gate circuit G1 and activated to a high level, the relief address calculation circuit 161 fixes the selection signal X / Y to column relief. This prohibits row relief, and all defective memory cells are rescued using redundant bit lines. Therefore, when the mode signal CMODE is activated to a high level, that is, when the column relief mode is selected, row relief is prohibited regardless of the count value of the row relief remaining number counter 163, and only column relief is effective. It becomes.

  On the other hand, when the column overflow signal COVF is output from the OR gate circuit G2 and activated to the high level, the relief address calculation circuit 161 fixes the selection signal X / Y to the row relief. As a result, column repair is prohibited, and all defective memory cells are repaired using redundant word lines. Therefore, when the mode signal RMODE is activated to a high level, that is, when the row relief mode is selected, column relief is prohibited regardless of the count value of the column relief remaining counter 164, and only row relief is effective. It becomes.

  When both the row overflow signal ROVF and the column overflow signal COVF are inactivated to the low level, both row relief and column relief are permitted, so that the relief address arithmetic circuit 161 has the failure analysis data FMI <j > Of the row relief and the column relief is selected based on the error pattern information D included in>.

  When row relief is selected by the relief address calculation circuit 161, the relief address selector 165 selects the necessary relief address RADD from the error address information supplied from the defect analysis data FMI <j>, and this is the electric fuse circuit. 142. The selection of the relief address RADD is performed based on the selection signal SEL supplied from the relief address calculation circuit 161.

  The relief address RADD supplied to the electric fuse circuit 142 is written to the row relief electric fuse set AFR (see FIG. 2) when the row relief strobe signal XSTB is activated, and the column relief strobe signal YSTB is activated. If it is, the data is written in the column fuse electric fuse set AFC (see FIG. 3).

  FIG. 6 is a flowchart for explaining the operation of the replacement address analysis circuit 146.

  First, an operation mode is selected using the DFT circuit 145 (step S11). When “normal mode” is selected, both the mode signals RMODE and CMODE are deactivated to a low level. Thereby, both row relief and column relief are permitted in the subsequent operations (step S12). Further, when the “row relief mode” is selected, the mode signal RMODE is activated to a high level. As a result, the column overflow signal COVF is forcibly activated, so that only row relief is permitted and column relief is prohibited in the subsequent operations (step S13). Further, when the “column relief mode” is selected, the mode signal CMODE is activated to a high level. As a result, the row overflow signal ROVF is forcibly activated, so that only column relief is permitted and row relief is prohibited in the subsequent operations (step S14).

  Next, the remaining numbers of unused electrical fuse sets AFR and AFC are acquired from the electrical fuse circuit 142 and loaded into the row repair remaining number counter 163 and the column repair remaining number counter 164, respectively (step S15). When secondary repair is performed for the first time, since the total number of electric fuse sets AFR and AFC is unused, the remaining numbers loaded in the row repair remaining number counter 163 and the column repair remaining number counter 164 are x + 1 and y + 1, respectively. It becomes. However, this does not mean that x + 1 defective word lines can be relieved and y + 1 defective bit lines can be relieved. As described above, the redundant word line RWL assigned to the electrical fuse set AFR is also assigned to the optical fuse set LFR, and similarly, the redundant bit line RBL assigned to the electrical fuse set AFC is the optical fuse set. This is because it is also assigned to the LFC. That is, the redundant word line RWL and the redundant bit line RBL used for replacement using the optical fuse sets LFR and LFC in the primary repair are used for replacement using the electrical fuse sets AFR and AFC in the secondary repair. Therefore, the remaining number is reduced by the amount used for the primary relief.

  However, information on the number of redundant word lines RWL and redundant bit lines RBL used in the primary repair is not included in the electrical fuse circuit 142. Therefore, when performing the secondary repair for the first time, the row repair remaining number counter 163 and The values loaded into the column repair remaining number counter 164 are all full as described above. For this reason, when the remaining number that can actually be used is small, even if the replacement address analysis circuit 146 performs a correct analysis, a case where a repair error actually occurs may occur. Such a problem can be avoided by setting the “row relief mode” or the “column relief mode” in advance using the mode signals RMODE and CMODE. For example, when the process maturity level is low as in the early stage of mass production, a large number of redundant bit lines RBL may be used for primary relief. In such a case, the “row relief mode” is activated by activating the mode signal RMODE ".

  Next, the first failure analysis data FMI <0> is read from the analysis memory 144 (step S16), and the relief address calculation circuit 161 selects whether to perform row relief or column relief. Of course, when the row relief mode is selected, the row relief is always selected, and when the column relief mode is selected, the column relief is always selected. The selection result is notified to the selection circuit 162 by the selection signal X / Y, and one of the row relief strobe signal XSTB and the column relief strobe signal YSTB is activated. In synchronization with this, the relief address selector 165 selects the necessary relief address RADD and supplies it to the electrical fuse circuit 142 (step S17). A specific method for selecting the relief address RADD will be described later.

  As a result, the relief address RADD is programmed in the electric fuse circuit 142 (step S18). That is, when the row relief strobe signal XSTB is activated, the relief address RADD is programmed in the electrical fuse set AFR (see FIG. 2), and when the column relief strobe signal YSTB is activated, the electrical fuse set is set. The relief address RADD is programmed in the AFC (see FIG. 3). The order of the electric fuse sets AFR and AFC to be used is as described above, and the electric fuse sets AFR and AFC are used in descending order of assigned numbers.

  When such processing is sequentially performed on all the failure analysis data FMI <0> to FMI <P> and processing is performed on all the failure analysis data FMI <0> to FMI <P>, replacement address analysis is performed. A series of processes using the circuit 146 is completed (step S19: YES).

  FIG. 7 is a diagram for explaining a method of selecting the relief address RADD.

  As shown in FIG. 7A, when the error pattern information D is a “Null” pattern, the corresponding error address information does not exist, and therefore, no relief address RADD is generated. On the other hand, as shown in FIGS. 7B to 7F, the error pattern information D is any one of the “Sn” pattern, the “By” pattern, the “Ey” pattern, the “Cx” pattern, and the “Cy” pattern. In this case, the generated relief address RADD differs depending on whether the row overflow signal ROVF or the column overflow signal COVF is activated. The row overflow signal ROVF is activated not only when the column relief mode is selected, but also when the normal mode is selected, but the row relief signal ROVF remains in the middle of the analysis using the replacement address analysis circuit 146. The case where the count value of the number counter 163 becomes zero is also applicable. Similarly, the column overflow signal COVF is activated not only when the row relief mode is selected, but also when the normal mode is selected, but during the analysis using the replacement address analysis circuit 146, the column relief signal COVF is activated. The case where the count value of the remaining number counter 164 becomes zero is also applicable.

  First, as shown in FIG. 7B, when the error pattern information D is the “Sn” pattern, in principle, the error address information y0 included in the failure analysis data FMI <j> is selected as the repair address RADD. The Thereby, the memory cell is replaced by column relief. However, when the column overflow signal COVF is activated, the error address information x0 included in the failure analysis data FMI is selected as the relief address RADD. As a result, the memory cell is replaced by row relief. Of course, when the row overflow signal ROVF is activated, the error address information y0 included in the failure analysis data FMI <j> is selected as the relief address RADD, and the memory cell is replaced by the row relief. In the above example, when the error pattern information D is the “Sn” pattern, column repair is performed in principle. However, row repair may be performed in principle.

  As shown in FIG. 7C, when the error pattern information D is a “By” pattern, in principle, the error address information y0 included in the failure analysis data FMI <j> is selected as the repair address RADD. Thereby, the two memory cells are replaced by column relief. However, when the column overflow signal COVF is activated, the error address information x0, x1 included in the failure analysis data FMI <j> is selected as the relief address RADD. As a result, the two memory cells are row-relieved using the two redundant word lines RWL. When the row overflow signal ROVF is activated, the above principle is followed.

  As shown in FIG. 7D, when the error pattern information D is an “Ey” pattern, in principle, the error address information y0 included in the failure analysis data FMI <j> is selected as the repair address RADD. Thereby, the two or more memory cells are replaced by column relief. However, when the column overflow signal COVF is activated, the address of the main word line corresponding to the error address information x0, x1 included in the failure analysis data FMI <j> is selected as the relief address RADD. The main word line can be specified by an address obtained by deleting, for example, the lower 2 bits of the error address information x0 and x1. Thus, the two or more memory cells are relieved by replacing four word lines at a time in units of main word lines. When the row overflow signal ROVF is activated, the above principle is followed.

  As shown in FIG. 7E, when the error pattern information D is the “Cx” pattern, in principle, the error address information x0 included in the failure analysis data FMI <j> is selected as the repair address RADD. Thereby, the two or more memory cells are replaced by row relief. However, when the row overflow signal ROVF is activated, it is treated as an error because it cannot be repaired. This is because when the error pattern information D is a “Cx” pattern, the column address cannot be repaired because the column addresses of all defective memory cells are not necessarily included in the error address information. When the column overflow signal COVF is activated, the above principle is followed.

  As shown in FIG. 7F, when the error pattern information D is a “Cy” pattern, in principle, the error address information y0 included in the failure analysis data FMI <j> is selected as the repair address RADD. Thereby, the three or more memory cells are replaced by column relief. However, when the column overflow signal COVF is activated, an error is processed as unrepairable. This is because when the error pattern information D is a “Cy” pattern, the row address of some defective memory cells is not included in the error address information, so that row relief is impossible. When the row overflow signal ROVF is activated, the above principle is followed.

  As described above, since the semiconductor device 100 according to the present embodiment includes the row relief mode and the column relief mode, the redundant word line RWL or the redundant bit line RBL is frequently used for the primary relief. Even if it exists, it becomes possible to perform secondary relief correctly.

  FIG. 8 is a block diagram showing a configuration of a replacement address analysis circuit 146a according to a modification.

  8 replaces the mode signals RMODE and CMODE from the DFT circuit 145 with the remaining electric fuse sets AFR (N−x) to AFR (N) in the row relief remaining number counter 163. Not only the number but also the remaining number of the optical fuse sets LFR (Nx) to LFR (N) are loaded, and similarly, the column relief remaining number counter 164 has the electric fuse sets AFC (My) to AFC (M). 8 is different from the replacement address analysis circuit 146 shown in FIG. 8 in that not only the remaining number but also the remaining number of the optical fuse sets LFC (My) to LFC (M) are loaded. As a result, the actual remaining numbers of the electrical fuse sets AFR and AFC are loaded into the row repair remaining number counter 163 and the column repair remaining number counter 164, respectively. This makes it possible to perform optimum secondary relief without mode setting in advance using the mode signals RMODE and CMODE.

  Next, a second preferred embodiment of the present invention will be described. This embodiment is an example in which the present invention is applied to a stacked semiconductor device in which a plurality of stacked semiconductor chips are packaged in the same package.

  FIG. 9 is a schematic cross-sectional view for explaining the structure of the semiconductor device 10 according to the preferred second embodiment of the present invention.

  As shown in FIG. 9, the semiconductor device 10 according to the present embodiment has the same function as each other, and the four core chips CC0 to CC3 manufactured using the same manufacturing mask are different from the core chips CC0 to CC3. It has a structure in which one interface chip IF manufactured using a manufacturing mask and one interposer IP are stacked. The core chips CC0 to CC3 and the interface chip IF are semiconductor chips using a silicon substrate, and are stacked on the interposer IP in a face-down manner. The face-down method refers to a method in which a semiconductor chip is mounted such that a main surface on which an electronic circuit such as a transistor is formed faces downward, that is, the main surface faces the interposer IP side.

  However, the semiconductor device according to the present invention is not limited to this, and each semiconductor chip may be stacked in a face-up manner. The face-up method refers to a method in which a semiconductor chip is mounted so that a main surface on which an electronic circuit such as a transistor is formed faces upward, that is, the main surface faces away from the interposer IP. Further, semiconductor chips stacked by the face-down method and semiconductor chips stacked by the face-up method may be mixed.

  Of these semiconductor chips, the core chips CC1 to CC3 and the interface chip IF, excluding the core chip CC0 located at the uppermost layer, are provided with a large number of through silicon vias TSV (Through Silicon Via) penetrating the silicon substrate. A surface bump FB is provided on the main surface side of the chip and a back surface bump BB is provided on the back surface side of the chip at a position overlapping the through electrode TSV in a plan view as viewed from the stacking direction. The rear surface bump BB of the semiconductor chip located in the lower layer is bonded to the front surface bump FB of the semiconductor chip located in the upper layer, and thereby the semiconductor chips adjacent vertically are electrically connected.

  The reason why the penetrating electrode TSV is not provided in the uppermost core chip CC0 in this embodiment is that it is not necessary to form a bump electrode on the back surface side of the core chip CC0 because it is laminated in a face-down manner. Thus, when the through-hole electrode TSV is not provided in the uppermost core chip CC0, the uppermost core chip CC0 can be made thicker than the other core chips CC1 to CC3, so that the mechanical strength of the core chip CC0 is increased. It becomes possible. However, in the present invention, the through silicon via TSV may be provided in the uppermost core chip CC0. In this case, all the core chips CC0 to CC3 can be manufactured in the same process.

  The core chips CC <b> 0 to CC <b> 3 are semiconductor chips in which a so-called front-end unit that interfaces with the outside is deleted from circuit blocks included in a normal SDRAM (Synchronous Dynamic Random Access Memory) that operates alone. In other words, it is a memory chip in which only circuit blocks belonging to the back end unit are integrated. The circuit block included in the front end unit includes a parallel / serial conversion circuit that performs parallel / serial conversion of input / output data between the memory cell array and the data input / output terminals, and a DLL (Delay Locked) that controls the input / output timing of data. Loop) circuit.

  On the other hand, the interface chip IF is a semiconductor chip in which only a front end portion is integrated among circuit blocks included in a normal SDRAM operating alone. The interface chip IF functions as a common front end unit for the four core chips CC0 to CC3. Therefore, all external accesses are performed via the interface chip IF, and data input / output is also performed via the interface chip IF.

  On the other hand, the interposer IP is a circuit board made of resin, and a plurality of external terminals (solder balls) SB are formed on the back surface IPb thereof. The interposer IP functions as a rewiring board for ensuring the mechanical strength of the semiconductor device 10 and increasing the electrode pitch. That is, the substrate electrode 91 formed on the upper surface IPa of the interposer IP is drawn out to the back surface IPb by the through-hole electrode 92, and the pitch of the external terminals SB is expanded by the rewiring layer 93 provided on the back surface IPb. Of the upper surface IPa of the interposer IP, a portion where the substrate electrode 91 is not formed is covered with a resist 90a. Further, the portion of the back surface IPb of the interposer IP where the external terminal SB is not formed is covered with a resist 90b. Although only five external terminals SB are illustrated in FIG. 9, a large number of external terminals are actually provided. The layout of the external terminal SB is the same as that in the SDRAM defined by the standard. Therefore, it can be handled as one SDRAM from an external controller.

  A gap between the stacked core chips CC0 to CC3 and the interface chip IF is filled with an underfill 94, thereby ensuring mechanical strength. An NCP (Non-Conductive Paste) 95 is filled in a gap between the interposer IP and the interface chip IF. The entire package is covered with a mold resin 96. Thereby, each chip is physically protected.

  Most of the through silicon vias TSV provided in the core chips CC1 to CC3 are connected to the front bump FB and the rear bump BB provided at the same position in plan view.

  FIG. 10 is a block diagram showing the circuit configuration of the main part of the semiconductor device 10 according to the present embodiment.

  As shown in FIG. 10, the interposer IP includes an address terminal 12, a command terminal 13, and a data terminal 14 as external terminals. These external terminals are all connected to the interface chip IF and are not directly connected to the core chips CC0 to CC3. In addition, a clock terminal, a data strobe terminal, a calibration terminal, a power supply terminal, and the like are included, but these are not shown.

  The address terminal 12 is a terminal corresponding to the address terminal 112 shown in FIG. 1, and is supplied with an address signal ADD including an address A and a bank address BA. The address signal ADD is latched by the address latch circuit 22 in the interface chip IF. The command terminal 13 is a terminal corresponding to the command terminal 120 shown in FIG. 1, and the command signal CMD is decoded by the command decoder 23 in the interface chip IF. The data terminal 14 is a terminal corresponding to the data system terminal 131 shown in FIG. 1, and inputs / outputs read data or write data DQ0. The data terminal 14 is connected to the data input / output circuit 24 in the interface chip IF. The address latch circuit 22, the command decoder 23, and the data input / output circuit 24 are connected to the core chips CC0 to CC3 through the through silicon via TSV.

  As shown in FIG. 10, a secondary relief circuit block 40 is provided in the interface chip IF. The secondary relief circuit block 40 is a circuit block including an electrical fuse circuit 42, a defective address analysis circuit 43, an analysis memory 44, a DFT 45, and a replacement address analysis circuit 46. These circuits are shown in FIG. The fuse circuit 142, the defective address analysis circuit 143, the analysis memory 144, the DFT 145, and the replacement address analysis circuit 146 have the same configuration and function. Therefore, when the test mode is set in the mode register 25, the secondary relief operation by the secondary relief circuit block 40 is performed. The electrical fuse circuit 42 is connected to the core chips CC0 to CC3 through the through silicon via TSV.

  The core chips CC0 to CC3 include a memory cell array 50, a row decoder 51 for performing row access to the memory cell array 50, and a column decoder 52 for performing column access to the memory cell array 50. The row decoder 51 selects one of the word lines WL included in the memory cell array 50 based on an address signal ADD (row address XADD) supplied from the interface chip IF through the through silicon via TSV. On the other hand, the column decoder 52 selects any column switch included in the column control circuit 53 based on the address signal ADD (column address YADD) supplied from the interface chip IF via the through silicon via TSV. The column switch is a switch for connecting one of the sense amplifiers included in the sense amplifier row 54 to the column control circuit 53. When any one of the switches becomes conductive, a predetermined bit is passed through the corresponding sense amplifier. The line BL and the column control circuit 53 are connected. The column control circuit 53 is connected to the data input / output circuit 24 in the interface chip IF through the through silicon via TSV.

  When the row address XADD supplied from the interface chip IF matches the defective address held in the relief control circuit 61, the row decoder 51 replaces the original word line WL included in the memory cell array 50 with the redundant word line RWL. Alternate access to. Similarly, when the column address YADD supplied from the interface chip IF matches the defective address held in the relief control circuit 62, the column control circuit 53 replaces the original bit line BL included in the memory cell array 50, Alternative access is performed to the redundant bit line RBL. Although not shown in FIG. 10, in the present embodiment, the redundant word line RWL and the redundant bit line RBL are included in the memory cell array 50.

  The relief control circuit 61 is a circuit corresponding to the relief control circuit 140 described in FIG. 2 (a) of US Patent Application 13 / 200,649, which is incorporated herein by reference. It includes a latch circuit 61a for holding, and a latch circuit 61b for holding a defective address supplied from the electric fuse circuit 42.

  The relief control circuit 62 is a circuit corresponding to the relief control circuit 140 described in FIG. 2 (a) of US patent application 13 / 200,649 incorporated by reference in this document. It includes a latch circuit 62a for holding, and a latch circuit 62b for holding a defective address supplied from the electric fuse circuit 42.

  As shown in FIG. 10, the column control circuit 53 includes a data determination circuit 53a. The data determination circuit 53a is a circuit corresponding to the data determination circuit 107a shown in FIG. Therefore, the determination signal P / F obtained as a result of the determination at the time of secondary relief is supplied to the defective address analysis circuit 43 in the interface chip IF through the through silicon via TSV.

  The operation of the secondary relief circuit block 40 is basically the same as the operation of the corresponding circuit block in the first embodiment. In the present embodiment, determination of test data at the time of secondary repair is performed using the data determination circuit 53a in the core chips CC0 to CC3, while analysis of defective addresses, analysis of replacement addresses, and retention of defective addresses at the time of secondary repair. Is performed on the interface chip IF side. When the initialization operation is performed when the power is turned on, the defective address is transferred from the electrical fuse circuit 42 in the interface chip IF to the relief control circuits 61 and 62 in each of the core chips CC0 to CC3 through the through silicon via TSV. At this time, the row address written in the electrical fuse circuit 42 is written in the latch circuit 61b in the repair control circuit 61, and the column address written in the electrical fuse circuit 42 is stored in the latch circuit 62b in the repair control circuit 62. Written.

  Thus, the present invention can also be applied to a stacked semiconductor device. In the present embodiment, since the optical fuse circuits 71 and 72 are mounted on the core chips CC0 to CC3 and the electric fuse circuit 42 is mounted on the interface chip IF, in the stacking process of the core chips CC0 to CC3 and the interface chip IF. The newly generated defective memory cell can be secondarily repaired. Moreover, in the present embodiment, since all the secondary relief circuit blocks 40 are arranged in the interface chip IF, the chip area of the core chips CC0 to CC3 that require a higher degree of integration than the interface chip IF is reduced. Is possible.

  In the second embodiment, the type of semiconductor device in which the interface chip IF and the core chips CC0 to CC3 are stacked has been described. However, the stacked type semiconductor device is not limited to this. Therefore, the type and number of semiconductor chips to be stacked are not particularly limited.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  It should be noted that the disclosure of US Patent Application 13 / 200,649 is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept.

10, 100 Semiconductor device 12, 112 Address terminal 13, 120 Command terminal 14 Data terminal 22 Address latch circuit 23, 124 Command decoder 24 Data input / output circuit 25, 125 Mode register 40 Secondary relief circuit block 42, 142 Electrical fuse circuit 43 , 143 Defective address analysis circuit 44, 144 Analysis memory 45, 145 DFT circuit 46, 146, 146a Replacement address analysis circuit 50, 101 Memory cell array 51, 104 Row decoder 52, 105 Column decoder 53, 107 Column control circuit 53a, 107a Data determination circuit 54, 106 Sense amplifier row 61, 62, 140 Relief control circuit 61a, 61b, 62a, 62b, 151, 152, 154, 155 Latch circuit 71, 72, 141 Optical fuse circuit 9 a, 90b Resist 91 Substrate electrode 92 Through-hole electrode 93 Redistribution layer 94 Underfill 96 Mold resin 102 Row redundancy circuit 103 Column redundancy circuit 108 Data control circuit 109 Input / output buffer 110 Row address control circuit 111 Column address control circuit 113 Address buffer 121 control terminal 122 clock terminal 123 command buffer 126 control buffer 127 control logic 128 clock buffer 129 clock generation circuit 130 DLL circuit 131 data system terminals 153 and 156 selection circuit 161 relief address arithmetic circuit 162 selection circuit 163 row relief remaining counter 164 column Relief remaining number counter 165 Relief address selector AFR, AFC Electric fuse set CC0 to CC3 FMI Failure analysis data IF Interface chip IP Interposer LFR, LFC Optical fuse set RBL Redundant bit line RWL Redundant word line RYS Redundant column selection line TSV Through electrode

Claims (11)

A memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells selected by them;
A fuse circuit for storing a row address of a word line corresponding to a predetermined defective memory cell among the plurality of memory cells and a column address of a bit line corresponding to another defective memory cell among the plurality of memory cells;
A plurality of redundant word lines for replacing a word line specified by the row address stored in the fuse circuit;
A plurality of redundant bit lines for replacing a bit line specified by the column address stored in the fuse circuit;
A replacement address analysis circuit for writing the row address and the column address to the fuse circuit,
The fuse circuit includes an optical fuse circuit and an electrical fuse circuit,
When the first operation mode is selected, the replacement address analysis circuit is allowed to write both the row address and the column address to the electric fuse circuit, and the second operation mode is When selected, one of the row address writing and the column address writing to the electric fuse circuit is permitted, and the other is prohibited.   In the replacement address analysis circuit, when the third operation mode is selected, one of the row address writing and the column address writing to the electric fuse circuit is prohibited, and the other is permitted. The semiconductor device according to claim 1.   The replacement address analysis circuit writes another row address or another column address to the electric fuse circuit in a state where a predetermined row address and a predetermined column address are written to the optical fuse circuit. Item 3. The semiconductor device according to Item 1 or 2. A failure address analysis circuit for generating failure analysis data including error pattern information indicating a layout of one or more defective memory cells by analyzing an address of the defective memory cell;
4. The semiconductor device according to claim 1, wherein the replacement address analysis circuit writes the row address or the column address to the electric fuse circuit based on the failure analysis data. 5. The plurality of redundant word lines are assigned to both the optical fuse circuit and the electric fuse circuit, and thereby, the word line corresponding to the row address written in one of the optical fuse circuit and the electric fuse circuit. The first redundant word line that can be replaced with the optical fuse circuit without being assigned to the electric fuse circuit, thereby replacing the word line corresponding to the row address written in the optical fuse circuit A second redundant word line,
The plurality of redundant bit lines are assigned to both the optical fuse circuit and the electric fuse circuit, and thereby the bit line corresponding to the column address written in one of the optical fuse circuit and the electric fuse circuit. The first redundant bit line that can be replaced with the optical fuse circuit without being assigned to the electric fuse circuit, and thereby the bit line corresponding to the column address written in the optical fuse circuit can be replaced. 5. The semiconductor device according to claim 1, further comprising: a second redundant bit line.   The memory cell array, the redundant word line, the redundant bit line, the replacement address analysis circuit, the defective address analysis circuit, the optical fuse circuit, and the electrical fuse circuit are packaged in the same package. The semiconductor device according to claim 4 or 5. The memory cell array, the redundant word line, the redundant bit line, and the optical fuse circuit are integrated on a first semiconductor chip;
The replacement address analysis circuit, the defective address analysis circuit, and the electrical fuse circuit are integrated on a second semiconductor chip,
The semiconductor device according to claim 6, wherein the first and second semiconductor chips are packaged in the package. A through electrode provided through at least one of the first and second semiconductor chips;
8. The row address and the column address written in the electrical fuse circuit are transferred from the second semiconductor chip to the first semiconductor chip through the through electrode. Semiconductor device. Performing a first operation test on a wafer-state memory device;
Identifying a first defective word line and a first defective bit line by analyzing an address of a first defective memory cell detected by the first operation test;
Replacing the first defective word line and the first defective bit line with a first redundant word line and a first redundant bit line, respectively, in the wafer state;
Removing the memory chip in which the memory device is singulated by cutting the wafer;
Packaging one or more semiconductor chips including at least the memory chip;
Performing a second operation test on the packaged semiconductor device;
Generating failure analysis data by analyzing an address of a second defective memory cell detected by the second operation test;
Based on the defect analysis data, a second defective word line corresponding to the second defective memory cell is replaced with a second redundant word line, or a second defect corresponding to the second defective memory cell. Selecting whether to replace the bit line with a second redundant bit line;
Replacing the second defective word line or the second defective bit line with a second redundant word line or a second redundant bit line, respectively.
In the selecting step, when the first operation mode is selected, both the replacement by the second redundant word line and the replacement by the second redundant bit line are validated, and the second operation is performed. When the mode is selected, one of the replacement with the second redundant word line and the replacement with the second redundant bit line is validated, and the other is invalidated. . The memory chip includes at least a plurality of redundant word lines that can be used as the first redundant word line and at least a plurality of redundant bit lines that can be used as the first redundant bit line.
Each of the plurality of redundant word lines is assigned a different number,
Each of the plurality of redundant bit lines is assigned a different number,
In the step of replacing the first defective word line and the first defective bit line with the first redundant word line and the first redundant bit line, respectively, a redundant word line having a small assigned number and an assigned number are assigned. The redundant bit line with the smaller number is used preferentially,
In the step of replacing the second defective word line or the second defective bit line with the second redundant word line or the second redundant bit line, respectively, a redundant word line or assigned with a large assigned number is assigned. 10. The method of manufacturing a semiconductor device according to claim 9, wherein a redundant bit line having a large number is preferentially used.   11. The semiconductor device according to claim 9, wherein an address analysis of the second defective memory cell detected by the second operation test is performed by a defective address analysis circuit provided in the semiconductor device. Production method.

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