JP2013196644A - Storage device, and control method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device in which even when output timing of data is deviated, read-out abnormality can be resolved.SOLUTION: A storage device 1 according to the embodiment includes a memory part 3 and a controller 2 for controlling the memory part 3. The storage device 1 includes a provision part 5, an association part 9, and a comparison part 6. The provision part 5 provides a readout address from the controller 2 to the memory part 3. The association part 9 reads data specified by the readout address out of the memory part 3, associates the data with the address information corresponding to the data, and provides the data and address information from the memory part 3 to the controller 2 along a clock corresponding to the readout address. The comparison part 6 compares the readout address and the address information associated with the data read out at a clock corresponding to the readout address so as to perform error detection.

Description

  Embodiments described herein relate generally to a storage device and a control method thereof.

  New specifications of semiconductor memory devices are manufactured according to various needs and incorporated into many products.

  A conventional semiconductor memory device having an ECC (Error Checking and Correcting) function can correct data read from a memory cell array such as bit data or byte data.

JP-A-11-110964

  The present embodiment provides a storage device and a control method for the storage device that can eliminate a reading abnormality even when the data output timing is shifted.

  According to the embodiment, the storage device includes a memory unit and a controller that controls the memory unit. The storage device includes a providing unit, an associating unit, and a comparing unit. The providing unit provides a read address from the controller to the memory unit. The associating unit reads the data specified by the read address from the memory unit, associates the data with the address information corresponding to the data, and stores the data and the address information along the clock corresponding to the read address. To the controller. The comparison unit compares the read address with address information associated with the data read in the clock corresponding to the read address, and performs error detection.

1 is a block diagram showing an example of a configuration of a semiconductor memory device according to a first embodiment. 3 is a timing chart showing an example of a normal operation state and an abnormal operation state of a semiconductor memory device. 4 is a timing chart showing an example of signals output from the memory controller according to the present embodiment to the memory unit. 6 is a timing chart illustrating an example of a normal operation state in which addresses are determined to match by an address comparison unit. 6 is a timing chart illustrating a first example of an abnormal operation state in which addresses are determined not to match by an address comparison unit. 9 is a timing chart illustrating a second example of an abnormal operation state in which addresses are determined not to match by an address comparison unit. 9 is a timing chart illustrating a third example of an abnormal operation state in which addresses are determined not to match by an address comparison unit. FIG. 5 is a block diagram showing an example of a configuration of a semiconductor memory device according to a second embodiment. The timing chart which shows the 1st example of a frequency reduction process. The timing chart which shows the 2nd example of a frequency reduction process. The timing chart which shows an example of an output buffer change. The timing chart which shows an example in which the output of address information is performed by issuing an address correlation command. 9 is a flowchart illustrating an example of a read process of a semiconductor memory device according to a third embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, substantially the same or substantially the same functions and components are denoted by the same reference numerals, and will be described as necessary.

(First embodiment)
The present embodiment will be described using a semiconductor storage device which is a kind of storage device, but is similarly applicable to other storage devices such as a magnetic storage device.

  For example, in the preceding semiconductor memory device, even if the read data is corrected, the interface speed is slow, the output timing of the desired data is delayed, and the desired data may not be read properly. is there. In addition, for example, in the preceding semiconductor memory device, there is a case where a skew is generated between the clock signal and the data, the data to be read is skipped, and all subsequent readings of the data are shifted. . In contrast, the semiconductor memory device according to the present embodiment performs data read retry and subsequent processing at high speed when the data output timing is shifted. The semiconductor memory device according to this embodiment prevents a processing delay when a data erroneous latch occurs due to, for example, data skew.

  In the following, address mismatch at the time of data reading will be described. However, address mismatch at the time of data writing can also be monitored by the same method.

  FIG. 1 is a block diagram showing an example of the configuration of the semiconductor memory device according to the present embodiment.

  The semiconductor memory device 1 includes a memory controller 2 and a memory unit 3.

  The memory controller 2 executes control for retrying data output when the output timing is shifted due to, for example, skew and data corresponding to a desired address cannot be extracted. The memory controller 2 includes a signal generating unit 4, a command providing unit 5, and an address comparing unit 6.

  The signal generation unit 4 includes a chip enable signal CE (may be / CE), a clock signal RE (may be / RE) provided from the memory controller 2 to the memory unit 3, and a write enable indicating that writing is possible. A signal WE is generated and output to the memory unit 3.

  The command providing unit 5 generates various commands such as an address (address command), an address association command, and a retry command, and provides them to the memory unit 3 as an input / output signal I / O. For example, the command providing unit 5 provides a retry command to the memory unit 3 when notified from the address comparing unit 6 that data has not been normally read.

  The address comparison unit 6 compares the address specified in the memory unit 3 with the address information associated (incorporated) with the data read in the clock corresponding to this address, and corresponds to the address. It is determined whether the data has been read normally. The address comparison unit 6 notifies the command providing unit 5 of the result when the data is not read normally.

  The memory unit 3 includes a clock generation unit 7, a command interpretation unit 8, an address association unit 9, and a memory cell array 10.

  The clock generator 7 generates a clock signal DQS based on the clock signal RE received from the memory controller 2, and outputs the clock signal DQS to the memory controller 2.

  The command interpretation unit 8 interprets various commands such as an address command for designating or notifying an address, an address association command for ordering to return data associated with an address, a retry command for ordering a retry, and the like. For example, when an address correlation command is received, the command interpretation unit 8 notifies the address correlation unit 9 of the result.

  When the address correlating unit 9 is notified from the command interpreting unit 8 that the address correlating command has been received, the address correlating unit 9 associates the address information corresponding to the data with the data, and associates the address information with the data. To the memory controller 2 as an input / output signal I / O.

  Various types of storage media can be applied to the memory cell array, for example, NAND flash memory, NOR flash memory, DRAM (Dynamic Random Access Memory), FPM-DRAM, EDO-DRAM, SDRAM, MRAM (Magnetoresistive Random Access). Memory), FeRAM (Ferroelectric Random Access Memory), etc. can be used.

  Hereinafter, changes in signals between the memory controller 2 and the memory unit 3 will be described using a timing chart.

  First, the timing chart of the normal operation state and the abnormal operation state in the semiconductor memory device 1 will be compared and described.

  FIG. 2 is a timing chart showing an example of a normal operation state and an abnormal operation state of the semiconductor memory device 1.

  The signal generation unit 4 sets the chip enable signal CE that enables the memory unit 3 to low, and puts the memory unit 3 into an operating state.

  The signal generator 4 provides the clock signal RE from the memory controller 2 to the memory unit 3.

  The clock generation unit 7 provides the clock signal DQS from the memory unit 3 to the memory controller 2.

  The memory unit 3 provides data corresponding to the address designated by the memory controller 2 to the memory controller 2 as an input / output signal I / O.

  In the normal operation state, the input / output signal I / O is output according to the change of the clock signal DQS (for example, in synchronization with the clock signal DQS).

  In the first example of the abnormal operation state, the cycle time is short and the output of data is delayed with respect to the output timing, so that the specified address and the output data are deviated, and the specified address and the output data are subsequently output. Deviation continues. In this case, the ECC function of the memory controller 2 is judged as NG and a retry is executed. However, this deviation occurs based on interface delay or the like, and correction by the ECC function may not be performed properly even if a retry is made.

  In the second example of the abnormal state, data skew occurs, data output after the data skew occurs is shifted, and data is not acquired normally. Such a difference between the designated address and the output data occurs based on interface delay or the like, and correction by the ECC function may not be properly performed even if a retry is made.

  In the present embodiment, even when such a shift occurs, the shift is repaired at high speed.

  FIG. 3 is a timing chart illustrating an example of signals output from the memory controller 3 according to the present embodiment to the memory unit 4.

  The signal generator 4 of the memory controller 3 generates and outputs a chip enable signal CE and a write enable signal WE.

  The command providing unit 5 transmits a specific address association command to the memory unit 3.

  When the command interpretation unit 8 of the memory unit 3 recognizes the address association command, it notifies the address association unit 9 of the association of the address information.

  When the address association unit 9 is notified of the association of the address information, the address association unit 9 outputs data corresponding to the address to the memory controller 2 and outputs the scrambled address information between normal data outputs.

  The address comparison unit 6 of the memory controller 2 compares the address output from the memory controller 2 to the memory unit 3 with the address information scrambled by the data output from the memory unit 3 to the memory controller 2, and It is determined whether appropriate data is output at the output timing. The address comparison unit 6 notifies the command providing unit 5 of the determination result.

  The command providing unit 5 automatically retries reading of only the mismatched portion when the address does not match and the data reading is retried, or stores a retry command when a retry instruction is input. Output to part 3.

  FIG. 4 is a timing chart showing a first example of a normal operation state in which the address comparison unit 6 determines that the addresses match.

  If the addresses match, it is determined that no delay has occurred in the interface, and data is read as needed.

  FIG. 5 is a timing chart showing a first example of an abnormal operation state in which the address comparison unit 6 determines that the addresses do not match (NG).

  In the first example where the addresses do not match, the reading of other data (COL data) continues even after the address mismatch occurs, and after all the data has been read, the reading of only the portion where the addresses do not match is retried. The

  FIG. 6 is a timing chart showing a second example of an abnormal operation state in which the address comparison unit 6 determines that the addresses do not match (NG).

  In the second example in which the addresses do not match, reading of the portion where the interface is delayed is retried when the address mismatch occurs.

  FIG. 7 is a timing chart showing a third example of an abnormal operation state in which the address comparison unit 6 determines that the addresses do not match (NG).

  In the third example in which the addresses do not match, when a retry instruction is input and a replay command is issued, reading of the portion where the delay has occurred in the interface is retried.

  In the present embodiment described above, the address designated to the memory unit 3 by the memory controller 2 during data reading and the address information output from the memory unit 3 to the memory controller 2 at the timing corresponding to this address are obtained. It is determined whether or not they match. In the present embodiment, when the addresses do not match, the reading of the data corresponding to this address is retried, and the reading abnormality is eliminated.

  Therefore, an ECC error that could not be corrected due to interface delay or the like and an ECC error that required time for correction can be corrected effectively, and high-speed operation of the semiconductor memory device 1 can be realized.

  Note that the retry of reading can be performed at a low processing speed, for example, by increasing the clock cycle, thereby increasing the probability that the reading is normally executed.

  Even in the case where the processing speed is maintained at a high speed, it is possible to increase the probability that the reading is normally executed by retrying the reading only in the portion where the address mismatch occurs.

  In the preceding semiconductor memory device, when a deviation occurs in the data output timing, after the ECC function, NG (reading abnormality) is detected and a retry is performed. However, even in this retry, NG is detected in the same state, and there is a high possibility that the retry will be repeated, and the processing time becomes long. On the other hand, in this embodiment, when NG is detected in the read process and a retry is performed, it is possible to prevent NG from being detected in the same state, and to prevent repeated retries. This can prevent an increase in processing time.

  By performing the same address comparison as described above at the time of writing, it is possible to determine the abnormal operation state at the time of writing, and the same effect as at the time of reading can be obtained.

(Second Embodiment)
In this embodiment, at the time of retrying reading, the frequency adjustment function for reducing the frequency to prevent the error from recurring, and retrying the reading by changing the size (resistance value) of the output buffer, the specified address and A semiconductor memory device to which at least one of the output buffer adjustment function for preventing the currently read address from being inconsistent will be described.

  FIG. 8 is a block diagram showing an example of the configuration of the semiconductor memory device according to the present embodiment.

  The semiconductor memory device 11 includes a memory controller 12 and a memory unit 15.

  The memory controller 12 of the semiconductor memory device 11 further includes a frequency adjusting unit 13 in addition to the signal generating unit 4, the command providing unit 5, and the address comparing unit 6.

  If the address comparing unit 6 determines that the addresses do not match, the frequency adjusting unit 13 instructs the signal transmitting unit 4 and the command providing unit 5 to reduce the frequency.

  For example, the signal transmission unit 4 and the command providing unit 5 retry reading with the clock frequency of the interface lowered.

  The memory unit 15 of the semiconductor memory device 14 further includes an output buffer adjustment unit 16 in addition to the clock generation unit 7, the command interpretation unit 8, the address association unit 9, and the memory cell array 10.

  When receiving the retry command, the command interpretation unit 8 notifies the output buffer adjustment unit 16 of the fact.

  The output buffer adjustment unit 16 changes the size of the output buffer that handles signals output from the memory unit 15 to the memory controller 2 such as the clock signal DQS and the input / output signal I / O, for example, in the read retry, Increase the output value of the signal.

  FIG. 9 is a timing chart showing a first example of frequency reduction processing.

  In this example, the address does not match and the read of the part where the address does not match is retried, but if the address does not match even in this retry, a read retry with a reduced frequency is performed. Yes.

  FIG. 10 is a timing chart showing a second example of frequency reduction processing.

  In this example, a read retry with a reduced frequency is performed for a portion where the addresses do not match.

  When the cause of the difference between the designated address and the currently read address is in the frequency, there is a high possibility that the address will not match again even if the read is retried at the same frequency. However, in this embodiment, when there is a shift in the address, the frequency is lowered and the read is retried. Therefore, the designated address can be matched with the currently read address, and the ECC function is used. Corrections can be made appropriately.

  FIG. 11 is a timing chart showing an example of output buffer change.

  In this example, for the part where the addresses do not match, the size of the output buffer is changed and a read retry is performed.

  As described above, when the address is shifted, the data can be read from the designated address by changing the size of the output buffer and performing the read retry, and the ECC correction can be appropriately performed. .

  In the present embodiment, at the time of retry, only the frequency adjustment unit 13 may be used, only the output buffer adjustment unit 16 may be used, or both the frequency adjustment unit 13 and the output buffer adjustment unit 16 are used. May be.

  In each of the above embodiments, the output of address information from the memory units 2 and 15 to the memory controllers 2 and 11 may be automatically performed at preset timings or set units. According to the instruction, as shown in FIG. 12, an address correlation command may be issued.

  The reading according to each of the above embodiments can also be applied to multichip interleaving in which a memory controller controls a plurality of memory units.

  When the semiconductor device according to each of the above embodiments is turned on, a test signal is used as a signal provided from the memory controller to the memory unit and a signal provided from the memory unit to the memory controller. The reading may be started after the test based on the end. As a result, the operation of the semiconductor device when the power is turned on can be stabilized. First, a test pattern is issued, and after operating normally with respect to this test pattern, a command is appropriately issued to stabilize the system power supply, for example, by increasing the latency.

(Third embodiment)
In the present embodiment, a read processing flow of the semiconductor memory device according to each of the above embodiments will be specifically described. In the present embodiment, a description will be given of a case where rereading is performed by changing the frequency when an address mismatch occurs.

  FIG. 13 is a flowchart illustrating an example of a read process of the semiconductor memory device according to the present embodiment.

  In step S1, the semiconductor memory device performs the first mode in which reading is retried when an address mismatch occurs, or continues to read other data even after the address mismatch occurs, and after all data has been read. The mode is determined by receiving a mode selection command indicating whether the second mode in which reading of only a portion where the addresses do not match is retried or the third mode in which normal reading without address comparison is performed. If it is determined that the mode is the first mode, the process moves to step S2. If it is determined that the mode is the second mode, the process moves to step S9. When it is determined that the mode is the third mode, a normal reading process is executed.

  In the case of the first mode, in step S2, the semiconductor memory device reads data corresponding to an address designated as a read target.

  In step S3, the semiconductor memory device compares the designated address with address information associated with the data read at the timing corresponding to this address, and determines whether or not they match.

  If the result of the address comparison indicates a match, in step S4, the semiconductor memory device determines whether all data has been read.

  If all the data has not been read, in step S5, the semiconductor memory device reads the next data.

  When all the data has been read, the semiconductor memory device ends the reading process as the reading is completed.

  If the result of the address comparison indicates a mismatch, in step S6, the semiconductor memory device determines whether rereading has been performed a maximum number of times set in advance.

  When the re-read is performed the maximum number of times, the semiconductor memory device ends the read process as read NG.

  When the re-reading has not been performed the maximum number of times, in step S7, the semiconductor memory device changes the interface clock frequency and / or the output buffer size.

  In step S8, the semiconductor memory device rereads data, and the process returns to step S3.

  In the case of the second mode, in step S9, the semiconductor memory device reads data corresponding to the address designated as the read target.

  In step S10, the semiconductor memory device compares the designated address with address information associated with the data read at the timing corresponding to this address, and determines whether or not they match.

  If the result of the address comparison indicates a mismatch, in step S11, the semiconductor memory device stores the address where the error occurred, and the process moves to step S12.

  If the result of the address comparison indicates a match, the process moves to step S12.

  In step S12, the semiconductor memory device determines whether all data has been read.

  If all the data has not been read, the semiconductor memory device reads the next data in step S13.

  If all the data has been read, in step S14, the semiconductor memory device determines whether or not there is a mismatch in the address comparison.

  If there is no mismatch in the address comparison, the semiconductor memory device ends the read process as read completion.

  If there is a mismatch in the address comparison, in step S15, the semiconductor memory device changes the interface clock frequency and / or the output buffer size.

  In step S <b> 16, the semiconductor memory device executes data reading for the stored error address.

  In step S17, the semiconductor memory device compares the error address with the address information associated with the data read at the timing corresponding to the error address, and determines whether they match.

  When the comparison result regarding the error address indicates coincidence, the reading process is terminated as the reading is completed.

  If the comparison result regarding the error address indicates a mismatch, the semiconductor memory device updates the stored error address with the error address at which the mismatch occurred in step S18.

  In step S19, the semiconductor memory device determines whether or not rereading has been performed a preset maximum number of times.

  When the re-read is performed the maximum number of times, the semiconductor memory device ends the read process as read NG.

  If rereading has not been performed the maximum number of times, the process moves to step S15.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1,11,14 ... Semiconductor memory device, 2,12 ... Memory controller, 3,15 ... Memory part, 4 ... Signal generation part, 5 ... Command provision part, 6 ... Address comparison part, 7 ... Clock generation part, 8 ... Command interpreting unit, 9 ... address correlation unit, 10 ... memory cell array, 13 ... frequency adjustment unit, 16 ... output buffer adjustment unit.

Claims (6)

A memory section;
A controller for controlling the memory unit;
A providing unit for providing a read address from the controller to the memory unit;
The data specified by the read address is read from the memory unit, the data and the address information corresponding to the data are related, and the data and the address information are transferred along the clock corresponding to the read address. An associating unit provided from the memory unit to the controller;
A storage device comprising: a comparison unit that compares the read address with address information associated with data read at a clock corresponding to the read address and detects an error.   The storage device according to claim 1, wherein the providing unit retries reading of the read address when a comparison result by the comparison unit does not match.   The storage device according to claim 2, further comprising a frequency adjusting unit that reduces the frequencies of the memory unit and the controller when retrying reading.   4. The apparatus according to claim 2, further comprising an output value adjustment unit that increases an output value of the clock and the data provided from the memory unit to the controller when a read retry is performed. Storage devices.   The storage device according to claim 1, wherein the association unit outputs the scrambled address information during data output. In the storage device control method,
Providing a read address from a controller of the storage device to a memory unit of the storage device;
The data specified by the read address is read from the memory unit, the data and the address information corresponding to the data are related, and the data and the address information are transferred along the clock corresponding to the read address. Providing from the memory unit to the controller;
A control method comprising: comparing the read address with address information associated with data read in a clock corresponding to the read address and performing error detection.

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