JP2013196195A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To more accurately determine an order of processing among processors.SOLUTION: A multiprocessor system 1 includes: a plurality of processors 10; a timer 12 commonly provided for the plurality of processors 10; and a plurality of storage areas 11 which are provided in correspondence with the plurality of processors 10 and store a plurality of event logs respectively. The plurality of event logs include time stamps obtainable from a value of the timer 12. The multiprocessor system 1 is capable of referring to time intervals and order of processing that the plurality of processors 10 have performed, on the basis of the time stamp.

Description

  Embodiments described herein relate generally to a multiprocessor system.

  In recent years, since it can be expected that the processing performance of a data processing apparatus is drastically improved, development of a multiprocessor system in which a plurality of processors are connected via a shared bus is being promoted. In a multiprocessor system, since a plurality of processors can perform processing simultaneously, control in the system becomes complicated.

  In order to improve the performance of the multiprocessor system, system verification between processors is performed in the development stage, and software debugging is performed. At this time, in order to perform debugging and performance tuning more accurately, information indicating which processor performs processing in what order is very useful.

JP 2011-70365 A

  Embodiments provide a multiprocessor system that can more accurately determine the order of processing among processors.

  The multiprocessor system according to the embodiment includes a plurality of processors, a timer provided in common to the plurality of processors, and a plurality of memories provided corresponding to the plurality of processors and respectively storing a plurality of event logs. A region. The timer includes a first counter that measures time information, and a second counter that counts up each time the plurality of processors access the timer, and the plurality of event logs are based on the value of the timer. The obtained time stamp is included, and based on the time stamp, the time interval and order of processing performed by the plurality of processors can be referred to.

The block diagram of SSD which concerns on 1st Embodiment. 1 is a block diagram of one NAND flash memory. FIG. The circuit diagram of a memory cell array. The figure explaining the event log of a processor. The flowchart which shows operation | movement of a certain processor. The figure explaining the specific example of the event log of a processor. The block diagram of the timer which concerns on 2nd Embodiment. The figure which shows the structural example of an access counter and a timer counter.

  Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as actual ones. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is specified by the shape, structure, arrangement, etc. of components. Is not to be done. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
The present embodiment is a configuration example for realizing a multiprocessor system including a plurality of processors. In the present embodiment, a memory system including a NAND flash memory, that is, an SSD (Solid State Drive) will be described as an example of a multiprocessor system.

[1] Configuration of Multiprocessor System (SSD) FIG. 1 is a block diagram of the SSD 1 according to the first embodiment. The SSD 1 includes a plurality of processors 10, a timer 12, an interface controller (I / F controller) 13, a shared memory 15, a NAND controller 16, one or more NAND flash memories 17, a debug interface circuit 18, an encryption / decryption Circuit 40 and bus 19 are provided. A plurality of circuits in the SSD 1 are connected to each other via a bus 19. In the present embodiment, three processors 10-1 to 10-3 are illustrated, but the number of processors 10 can be arbitrarily set.

  Each processor 10 is composed of, for example, a CPU (Central Processing Unit). The processor 10 controls various operations in the SSD 1. For example, the processor 10 performs interpretation and execution of instructions, execution of programs, maintenance of the state of execution results, and the like. The processor 10 includes a RAM 11 as a work area in which the processor 10 can freely rewrite data. The RAM 11 is composed of a volatile RAM such as SRAM. The information stored in the RAM 11 includes an event log of the corresponding processor 10.

  The timer 12 measures time. The time measured by the timer 12 is used for a time stamp included in the event log. The timing at which the timer 12 starts measuring time is after the SSD 1 is activated (for example, after a power-on reset) and ready for normal operation, or when the SSD 1 is in operation, a reset signal is received from the processor 10 Such as the case. The timer 12 receives a reference clock from an element that generates a reference clock, for example, a crystal oscillator (not shown), and counts up the reference clock to measure time. That is, the timer 12 stores time information as a count value.

  The interface controller 13 is connected to the host controller by an interface (I / F) 14. The interface controller 13 executes interface processing with the host controller. As the interface 14, for example, SATA (Serial Advanced Technology Attachment) is used.

  The shared memory 15 is shared by the processors 10-1 to 10-3. In the shared memory 15, for example, information used in common by the processors 10-1 to 10-3 is stored. The shared memory 15 is also used as a write buffer that temporarily stores write data to be written to the NAND flash memory 17 and a read buffer that temporarily stores read data read from the NAND flash memory 17. Is done. The shared memory 15 is composed of a volatile RAM such as SRAM.

  The NAND controller 16 performs an interface process with the NAND flash memory 17. Specifically, the NAND controller 16 supplies commands and addresses to the NAND flash memory 17 and transmits and receives data to and from the NAND flash memory 17. When transmitting and receiving this data, the NAND controller 16 performs ECC (Error Checking and Correcting) processing. The NAND controller 16 interleaves a plurality of NAND flash memories 17.

  The encryption / decryption circuit 40 encrypts data transmitted from the host controller. Therefore, the encrypted data is stored in the NAND flash memory 17. The encryption / decryption circuit 40 decrypts data read from the NAND flash memory 17.

  The debug interface circuit 18 is provided so that a debug device can be connected to the SSD 1. The debug interface circuit 18 performs an interface process with the debug device. The debugging of the SSD 1 is performed by this debugging device.

  Next, the configuration of the NAND flash memory 17 will be described. FIG. 2 is a block diagram of one NAND flash memory 17.

  The memory cell array 20 is configured by arranging memory cells that can electrically rewrite data in a matrix. In the memory cell array 20, a plurality of bit lines, a plurality of word lines, and a common source line are arranged. Memory cells are arranged in the intersection region between the bit line and the word line.

  A word line control circuit 23 that functions as a row decoder is connected to a plurality of word lines, and selects and drives the word lines when reading, writing, and erasing data. The bit line control circuit 21 is connected to a plurality of bit lines, and controls the voltage of the bit line when reading, writing, and erasing data. The bit line control circuit 21 detects data on the bit line when reading data, and applies a voltage corresponding to the write data to the bit line when writing data. The column decoder 22 generates a column selection signal for selecting a bit line according to the address, and sends this column selection signal to the bit line control circuit 21.

  Read data read from the memory cell array 20 is sent from the data input / output terminal 26 to the NAND controller 16 via the bit line control circuit 21 and the data input / output buffer 27. Write data input from the NAND controller 16 to the data input / output terminal 26 is sent to the bit line control circuit 21 via the data input / output buffer 27.

  The memory cell array 20, bit line control circuit 21, column decoder 22, word line control circuit 23, and data input / output buffer 27 are connected to the control circuit 24. The control circuit 24 is based on the control signal input from the NAND controller 16 to the control signal input terminal 25, and the memory cell array 20, bit line control circuit 21, column decoder 22, data input / output buffer 27, and word line control circuit 23. A control signal and a control voltage for controlling the signal are generated.

  FIG. 3 is a circuit diagram of the memory cell array 20. The memory cell array 20 includes a plurality of blocks BLK. Each block BLK is composed of a plurality of memory cells, and data is erased in units of the block BLK. The block BLK includes n (n is a natural number) NAND strings NS.

  Each NAND string NS includes m (m is a natural number) memory cell transistors (memory cells) MT and two select transistors ST1 and ST2. Each memory cell transistor MT includes a stacked gate including a control gate and a charge storage layer, and stores data in a nonvolatile manner. The memory cell transistor MT changes its threshold voltage according to the number of charges stored in the charge storage layer, and stores data according to the difference in threshold voltage.

  The m memory cell transistors MT are arranged between the select transistors ST1 and ST2 so that their current paths are connected in series. The current path of the memory cell transistor on one end side of the series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor on the other end side is connected to one end of the current path of the selection transistor ST2. ing.

  The gates of the selection transistors ST1 in the same block BLK are commonly connected to the selection gate line SGD, and the gates of the selection transistors ST2 in the same block BLK are commonly connected to the selection gate line SGS. The control gates of the memory cell transistors MT for one row in the same block BLK are commonly connected to one word line WL.

  Of the NAND strings NS arranged in a matrix in the memory cell array 20, the other ends of the current paths of the select transistors ST1 of the NAND strings NS in the same row are commonly connected to one bit line BL. That is, the bit line BL commonly connects the NAND strings NS between the plurality of blocks BLK. The other end of the current path of the selection transistor ST2 is commonly connected to the source line SL. For example, the source line SL commonly connects the NAND strings NS between a plurality of blocks BLK.

  As described above, the data of the memory cell transistors MT in the same block BLK are erased collectively. On the other hand, data reading and writing are performed collectively for a plurality of memory cell transistors MT commonly connected to any word line WL in any block BLK. This unit is called “page”.

[2] Operation of SSD 1 The operation of the SSD 1 configured as described above will be described. FIG. 4 is a diagram for explaining an event log of the processor 10. Each processor 10 records the processing content in its own event log (log file) when executing some processing. The event log is stored in the RAM 11. Specifically, the processor 10 includes a calculation unit 10A, and when a certain process is executed by the processor 10, the calculation unit 10A records the processing content in an event log. In addition, the calculation unit 10A records the processing contents in the event log in the order of occurrence of events (events). The event log includes a time stamp T and a processing content LG. The time stamp is information indicating the time when a certain process is executed, and is an attribute of the event log.

  In the present embodiment, the SSD 1 includes one timer 12 that is provided in common to the plurality of processors 10. Then, when the processing contents are recorded in the event log, the plurality of processors 10 obtain time information with reference to one timer 12, and record this time information in the event log together with the processing contents as a time stamp.

  As described above, by configuring the plurality of processors 10 to use the common timer 12, for example, by referring to the event log recorded in the plurality of processors 10 when verifying the system, even between different processors. It is possible to grasp the time intervals and order of the processes recorded in the event log.

  FIG. 5 is a flowchart showing the operation of a certain processor 10. A certain processor 10 executes arbitrary processing according to its role (step S100). Subsequently, the processor 10 refers to the timer 12 and acquires the value of the timer 12 (step S101). Note that the timing at which the processor 10 refers to the timer 12 may be unified within the system, and may be when processing is started or when processing is completed.

  Subsequently, the processor 10 creates a time stamp based on the value of the timer 12 (step S102). Subsequently, the processor 10 records the time stamp and the processing content in its own event log (step S103). In this way, the event log recording operation is completed for one process.

  Next, an example of more specific operation of the processors 10-1 to 10-3 will be described. FIG. 6 is a diagram for explaining a specific example of the event log of the processor 10.

  In the example of FIG. 6, some data is recorded in the NAND flash memory 17 in an encrypted state. The data is read from the NAND flash memory 17 based on a request from the host controller, decrypted, and decrypted. It is an example of the operation | movement which sends data to a host controller. T1 to T14 are time stamps. Each processing content may actually be an identifier (ID: Identification Data) indicating that the program code has passed a certain point.

  The processor (PC1) 10-1 is configured to control the SATA controller (SATA-C) 13. The processor (PC2) 10-2 is configured to control the NAND controller (NAND-C) 16. The processor (PC3) 10-3 is configured to be able to control data encryption and decryption. As described above, the functions of the processors 10-1 to 10-3 are individually assigned. Each of the processors 10-1 to 10-2 records a time stamp and processing contents in the event logs 1 to 3.

  First, the processor PC1 receives an interrupt from the SATA-C and records this processing content in the event log 1 together with the time stamp T1. Subsequently, the processor PC1 receives a request from the SATA-C, and records this processing content in the event log 1 together with the time stamp T2. Subsequently, the processor PC1 places an instruction for the processor PC2 in the shared memory 15, interrupts the processor PC2, and records these processing contents in the event log 1 together with the time stamp T3.

  Subsequently, the processor PC2 receives an interrupt from the processor PC1, and records this processing content in the event log 2 together with the time stamp T4. Subsequently, the processor PC2 reads the instruction of the processor PC1 from the shared memory 15, and records the processing content in the event log 2 together with the time stamp T5. Subsequently, the processor PC2 operates the NAND-C to read the encrypted data from the NAND flash memory (NAND) 17, and records this processing content in the event log 2 together with the time stamp T6. Subsequently, the processor PC2 places an instruction to the processor PC3 in the shared memory 15, interrupts the processor PC3, and records these processing contents in the event log 2 together with the time stamp T7.

  Subsequently, the processor PC3 receives an interrupt from the processor PC2, and records this processing content in the event log 3 together with the time stamp T8. Subsequently, the processor PC3 reads the instruction of the processor PC2 from the shared memory 15, and records this processing content in the event log 3 together with the time stamp T9. Subsequently, the processor PC3 operates the encryption / decryption circuit 40 to decrypt the data read from the NAND flash memory (NAND) 17, and records this processing content in the event log 3 together with the time stamp T10. To do. Subsequently, the processor PC3 places the decrypted data in the shared memory 15, interrupts the processor PC1, and records these processing contents in the event log 3 together with the time stamp T11.

  Subsequently, the processor PC1 receives an interrupt from the processor PC3, and records this processing content in the event log 1 together with the time stamp T12. Subsequently, the processor PC1 reads data from the shared memory 15, and records the processing content in the event log 1 together with the time stamp T13. Subsequently, the processor PC1 operates SATA-C to send data to the host controller, and records this processing content in the event log 1 together with the time stamp T14. In this way, the processing of transmitting the data read from the NAND flash memory 17 to the host controller by the processors PC1 to PC3 is completed. Thus, the time stamps T1 to T14 recorded in the event logs 1 to 3 are unified in time series.

[3] Effect As described in detail above, in the first embodiment, the multiprocessor system (SSD) 1 includes a plurality of processors 10 and a timer provided in common to the plurality of processors 10. ing. Each processor 10 has an event log for recording processing contents, and the event log includes a time stamp obtained from the value of the timer 12. The plurality of processors 10 record a time stamp obtained from the value of the common timer 12 every time the process is executed in the event log.

  Therefore, according to the first embodiment, the event log of the processors 10-1 to 10-3 is read from a debugging device or the like at the time of debugging or performance tuning, and the time stamp and processing contents are based on the read event log. By confirming the above, it is possible to more accurately determine which processor among the processors 10-1 to 10-3 performs the processing in which order, and the processing time interval. As a result, debugging and performance tuning can be performed more accurately.

  For example, in a configuration in which multiple processors each have multiple timers, the time stamp sequence is different for each processor, making it difficult to grasp the processing order between different processors, and the processing time interval. And the order cannot be determined accurately. However, such a problem can be solved by using the configuration of the present embodiment.

  In addition, the use of the event log recording method of the present embodiment facilitates debugging and performance tuning of the multiprocessor system, so that (1) reduction in development cost of the multiprocessor system and (2) development period of the multiprocessor system. (3) Improvement of performance of the multiprocessor system can be obtained.

[Second Embodiment]
As described in the first embodiment, even when a common timer is arranged for a plurality of processors, if different processors read out the timer at a time interval shorter than the resolution of the timer, the processing context is distinguished. There is a risk that it will not be possible. Therefore, in the second embodiment, an access counter that counts up each time the processor accesses the timer is newly provided, and both the time information when the processing is executed and the order in which the processor accesses the timer are recorded in the event log. Like to do.

  FIG. 7 is a block diagram of the timer 12 according to the second embodiment. The configuration of the SSD 1 other than the timer 12 is the same as that in FIG. The timer 12 includes an access detection unit 30, an access counter 31A, and a timer counter 31B.

  The access detection unit 30 detects that the timer 12 (specifically, the access counter 31A and the timer counter 31B) is accessed from the processors 10-1 to 10-3, and counts up the access counter 31A for each access. . Therefore, the access counter 31A stores the number of times the processors 10-1 to 10-3 accessed the timer 12 as a count value.

  For example, the timer counter 31B receives a reference clock from a crystal oscillator (not shown) and counts up the reference clock to measure time. That is, the timer counter 31B stores time information as a count value. The access counter 31A and the timer counter 31B are connected to the bus 19.

  FIG. 8 is a diagram illustrating a configuration example of the access counter 31A and the timer counter 31B. One (n + 1) bit counter 31 is prepared for the access counter 31A and the timer counter 31B. Internally, an [m: 0] bit counter unit (access counter 31A) and an [n: m] bit counter unit (timer It is configured to have a counter 31B). n is a natural number, and n> m. Note that the bit allocation of the counter 31 is arbitrary. In the counter 31, the [m: 0] bit counter unit (access counter 31A) counts up for every counter read (counter access) operation, and the [n: m] bit counter unit (timer counter 31B) according to the reference clock. Works to count up. That is, the [m: 0] bit counter unit and the [n: m] bit counter unit individually perform a count-up operation.

  When referring to the timer 12, the processor 10 reads all bits of the access counter 31A and the timer counter 31B. Then, the processor 10 records the count values read from the access counter 31A and the timer counter 31B as time stamps in the event log.

  As described above in detail, in the second embodiment, the access counter 31A that counts up every time the processor 10 accesses the timer 12 is assigned to a specific bit in the counter 31. For this reason, the time stamp recorded in the event log includes time information when the process is executed and information indicating the order in which the processor accesses the timer. Accordingly, even when a plurality of processors access the timer at a time interval shorter than the resolution of the timer, the processing order can be accurately grasped by checking the count value of the access counter 31A. Further, even when processing with very short time intervals continues, the processing order can be accurately grasped.

  For example, when only the access counter 31A is used, the processing order can be grasped, but the processing time interval cannot be determined. However, in the present embodiment, since the timer counter 31B and the access counter 31A are used together, it is possible to grasp the processing time interval and order.

  When the count cycle of the counter 31 is later than the clock cycle of the bus 19, the same count value by the timer counter 31B may be recorded in a plurality of time stamps. Even in such a case, since the processing order can be determined in this embodiment, this embodiment is particularly effective when the count cycle of the counter 31 is slower than the clock cycle of the bus 19.

  In each of the above embodiments, the SSD has been described as an example of the multiprocessor system. However, the present invention is not limited to the SSD, and can be applied to various information processing apparatuses including a plurality of processors.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... SSD, 10 ... Processor, 11 ... RAM, 12 ... Timer, 13 ... Interface controller, 14 ... Interface, 15 ... Shared memory, 16 ... NAND controller, 17 ... NAND flash memory, 18 ... Interface circuit for debugging, 19 ...... Bus, 20 ... Memory cell array, 21 ... Bit line control circuit, 22 ... Column decoder, 23 ... Word line control circuit, 24 ... Control circuit, 25 ... Control signal input terminal, 26 ... Data input / output terminal, 27 ... Data input Output buffer, 30... Access detection unit, 31 A... Access counter, 31 B... Timer counter, 40.

Claims (5)

Multiple processors,
A timer provided in common to the plurality of processors;
A plurality of storage areas provided corresponding to the plurality of processors, each storing a plurality of event logs;
Comprising
The timer includes a first counter that measures time information, and a second counter that counts up each time the plurality of processors access the timer,
The plurality of event logs include a time stamp obtained from the value of the timer,
A multiprocessor system, wherein a time interval and a sequence of processing performed by the plurality of processors can be referred to based on the time stamp.   The multiprocessor system according to claim 1, wherein the timer further includes a detection unit that detects that the plurality of processors have accessed the timer.   The multiprocessor system according to claim 1, wherein the first counter counts up a reference clock. Multiple processors,
A timer provided in common to the plurality of processors;
A plurality of storage areas provided corresponding to the plurality of processors, each storing a plurality of event logs;
Comprising
The plurality of event logs include a time stamp obtained from the value of the timer,
A multiprocessor system, wherein a time interval and a sequence of processing performed by the plurality of processors can be referred to based on the time stamp. Non-volatile memory;
A memory controller that controls the nonvolatile memory in accordance with instructions from the plurality of processors;
The multiprocessor system according to claim 1, further comprising:

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