JP2013183430A - GaNFET BIAS CIRCUIT - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a GaNFET bias circuit that suppresses undesired oscillation of a GaNFET.SOLUTION: The GaNFET bias circuit includes: a positive constant voltage power supply 17 for outputting a driving voltage for a GaNFET 10; a drain voltage control switch 18; a negative constant voltage power supply 24 for outputting a pinch-off voltage for the GaNFET 10; voltage dividing resistances 25, 26 for dividing the pinch-off voltage to an on voltage for the GaNFET 10; and a gate voltage control switch 27. The drain voltage control switch 18 is connected between the positive constant voltage power supply 17 and a drain terminal 10d of the GaNFET 10 to supply the driving voltage to the drain terminal 10d for a predetermined time. The gate voltage control switch 27 is connected between the negative constant voltage power supply 24 and a gate terminal 10g of the GaNFET 10 and between the voltage dividing resistances 25, 26 and the gate terminal 10g to supply the on voltage to the gate terminal 10g while the driving voltage is applied to the drain terminal 10d.

Description

  Embodiments described herein relate generally to a GaN FET bias circuit.

  In recent years, GaN FETs that can apply a high voltage and output a high-power high-frequency signal have attracted attention. A bias circuit for applying a predetermined drain voltage and a predetermined gate voltage is connected to the GaN FET.

  In general, the GaNFET bias circuit includes a drain bias circuit for applying a predetermined drain voltage to the drain terminal of the GaNFET and a gate bias circuit for applying a predetermined gate voltage to the gate terminal of the GaNFET.

  The gate bias circuit always applies an ON voltage as a gate voltage to the gate terminal, and the drain bias circuit applies a drive voltage as a drain voltage to the drain terminal for a predetermined time. The GaNFET amplifies the high-frequency signal for a predetermined time during which the drive voltage is applied. Therefore, the GaNFET modulates and outputs a high-frequency signal having a constant intensity in a pulse shape.

  However, when the voltage of the drain terminal is increased from 0V to, for example, 25V, which is the driving voltage, by this conventional GaNFET bias circuit, the increase width is extremely large, so the drain voltage does not instantaneously reach 25V, and 25V It takes a predetermined time to reach In addition, when the drain voltage is lowered from 25 V to 0 V in order to finish the amplification of the high frequency signal, the fall width is also extremely large. Therefore, the drain voltage does not return to 0 V instantaneously, Time is needed. Therefore, in the process in which the drain voltage increases and decreases, a state in which a low voltage (for example, around 3 to 8 V) is applied to the drain terminal occurs. On the other hand, an on-voltage is always applied to the gate terminal. When a low drain voltage is applied in a state where an on-voltage is applied to the GaN FET, the value of mutual conductance increases, the gain increases, and the stability index deteriorates. As a result, the drain current flowing through the GaN FET oscillates unnecessarily.

JP 2005-235893 A

  An object of the embodiment is to provide a bias circuit for a GaN FET that can suppress unnecessary oscillation of the GaN FET.

  The bias circuit for GaN FET according to the embodiment is a bias circuit for GaN FET that applies a desired voltage to the GaN FET, and is a positive constant voltage power source, a drain voltage control switch, a negative constant voltage power source, a voltage dividing resistor, and a gate voltage. A control switch. The positive constant voltage power supply outputs a driving voltage for the GaN FET. The drain voltage control switch is connected between the positive constant voltage power source and the drain terminal of the GaNFET, and supplies the drive voltage output from the positive constant voltage power source to the drain terminal for a predetermined time. The negative constant voltage power supply outputs a pinch-off voltage of the GaN FET. The voltage dividing resistor divides the pinch-off voltage into the on-voltage of the GaN FET. The gate voltage control switch is connected between the negative constant voltage power source and the gate terminal of the GaNFET, and between the voltage dividing resistor and the gate terminal of the GaNFET, and the drive voltage is applied to the drain terminal. While the voltage is applied, the ON voltage is supplied to the gate terminal.

It is a circuit diagram which shows the bias circuit for GaNFET which concerns on embodiment. It is a circuit which shows an example of a drain voltage control switch. It is a circuit diagram which shows an example of a gate voltage control switch. A high-frequency signal input to the GaN FET (FIG. 1A), a high-frequency signal output from the GaN FET (FIG. 2B), and a drain voltage control control pulse supplied to the drain voltage control switch (FIG. c)), a drain voltage applied to the drain terminal of the GaNFET (FIG. (d)), a gate voltage control control pulse (FIG. (e)) supplied to the gate voltage control switch, and the gate of the GaNFET It is a figure which shows the relationship with the gate voltage (same figure (f)) applied to a terminal. It is a figure which shows the relationship between the voltage (drain voltage) applied to the drain terminal of GaNFET, and the electric current which flows into this GaNFET for every voltage (gate voltage) applied to the gate terminal of GaNFET.

  The GaN FET bias circuit according to the embodiment will be described below. FIG. 1 is a circuit diagram illustrating a GaN FET bias circuit according to an embodiment. As shown in FIG. 1, the GaN FET bias circuit according to the embodiment includes a drain bias circuit 11 connected to the drain terminal 10 d of the GaNFET 10 and a gate bias circuit 12 connected to the gate terminal 10 g of the GaNFET 10. . Note that the source terminal 10s of the GaNFET 10 is grounded.

  The GaNFET 10 is capable of outputting a high-power high-frequency signal by applying a higher voltage than a conventional FET such as a GaAsFET. The GaNFET 10 is an FET that stably amplifies when a drive voltage of 25 V is applied as a drain voltage and an on voltage of −1.5 V is applied as a gate voltage, for example, and a pinch-off voltage is −5 V, for example. is there.

  A drive voltage and an on-voltage are applied to the GaNFET 10 by a GaNFET bias circuit (drain bias circuit 11 and gate bias circuit 12). When a high frequency signal is input to the gate terminal 10g of the GaNFET 10 in this state via the DC cut capacitor 13, the power of the signal is amplified. The high frequency signal with amplified power is output from the drain terminal 10 d of the GaNFET 10. The output high-frequency signal is output to the outside via the DC cut capacitor 14.

  The drain bias circuit 11 is a bias circuit for applying a positive drive voltage to the drain terminal 10d of the GaNFET 10 for a predetermined time in order to amplify the power of the high-frequency signal input to the GaNFET 10 for a predetermined time.

  A quarter wavelength line 15 and a capacitor 16 are connected in series to the drain terminal 10 d of the GaNFET 10 in this order, and the drain bias circuit 11 is connected between the quarter wavelength line 15 and the capacitor 16. That is, the drain bias circuit 11 is connected to the drain terminal 10 d of the GaNFET 10 via the quarter wavelength line 15.

  Note that the quarter wavelength line 16 ideally acts as an infinite impedance line for the high-frequency signal output from the GaNFET 10. Therefore, the high-frequency signal output from the GaNFET 10 does not substantially flow into the drain bias circuit 11 and is propagated to the DC cut capacitor 14 side.

  The capacitor 16 is short-circuited with respect to the high-frequency signal and appears to be open with respect to the direct current. Therefore, the capacitor 16 suppresses the weak high-frequency signal that has been slightly propagated through the quarter wavelength line 15 from being input to the drain bias circuit 11, and the voltage output from the drain bias circuit 11. Can be efficiently applied to the drain terminal 10 d of the GaNFET 10.

  The drain bias circuit 11 connected between the quarter wavelength line 15 and the capacitor 16 is configured by a positive constant voltage power supply 17 and a drain voltage control switch 18.

  The positive constant voltage power supply 17 is a power supply for applying a drive voltage necessary for the GaNFET 10 to amplify the power of the high-frequency signal to the drain terminal 10d of the GaNFET 10, and for example, a power supply that outputs 25V. The positive constant voltage power supply 17 is connected to the quarter wavelength line 15 via the drain voltage control switch 18.

  The drain voltage control switch 18 controls the drive voltage output from the drain bias circuit 11 so that the drive voltage output from the positive constant voltage power supply 17 is applied to the drain terminal 10d of the GaNFET 10 for a predetermined time. Switch.

  The drain voltage control switch 18 is connected to a drain voltage control switch pulse source 19 for driving the switch 18 (hereinafter referred to as a pulse source 19). The pulse source 19 supplies a drain voltage control pulse 20 (hereinafter referred to as a control pulse 20) for controlling the opening and closing of the drain voltage control switch 18 to the drain voltage control switch 19. The pulse source 19 may be provided outside the drain bias circuit 11 or may be included in the drain bias circuit 11.

  FIG. 2 is a diagram illustrating an example of the drain voltage control switch 20. The drain voltage control switch is, for example, a MOSFET 21 as shown in FIG. When the MOSFET 21 is applied as the drain voltage control switch 20, the drain terminal 21 d of the MOSFET 21 is connected to the positive constant voltage power supply 17, and the source terminal 21 s of the MOSFET 21 is between the quarter wavelength line 1815 and the capacitor 16. Connected to. The gate terminal 21 g of the MOSFET 21 is connected to the pulse source 19.

  When the control pulse 20 is supplied from the pulse source 19 to the gate terminal 21g of the MOSFET 21, the MOSFET 21 is closed only while the control pulse 20 is supplied. As a result, the drive voltage output from the positive constant voltage power supply 17 is output only while the MOSFET 21 is closed, and is applied to the drain terminal 10d (FIG. 1) of the GaNFET 10.

  Refer to FIG. 1 again. Similarly to the drain terminal 10 d, the quarter wavelength line 22 and the capacitor 23 are connected in series in this order to the gate terminal 10 g of the GaNFET 10, and the gate bias circuit 12 Connected between. That is, the gate bias circuit 12 is connected to the gate terminal 10 g of the GaNFET 10 via the quarter wavelength line 22.

  The quarter wavelength line 22 and the capacitor 23 operate in the same manner as the quarter wavelength line 15 and the capacitor 16 connected to the drain terminal 10 d of the GaNFET 10.

  The gate bias circuit 12 includes a negative constant voltage power supply 24, first and second resistors 25 and 26 for voltage division, and a gate voltage control switch 27.

  The negative constant voltage power supply 24 is a power supply for applying the pinch-off voltage of the GaNFET 10 to the gate terminal 10g of the GaNFET 10, and is a power supply that outputs -5V, for example. The negative constant voltage power supply 24 is connected to the quarter wavelength line 22 via a gate voltage control switch 27.

  The first and second resistors 25 and 26 for voltage division are resistors for dividing the pinch-off voltage output from the negative constant voltage power supply 24, and the first resistor 25 having a constant resistance value and a predetermined resistance value. And a second resistor 26, which is a semi-fixed resistor that can be set to a resistance value of. One end of the first resistor 25 is connected to a negative constant voltage power supply 24. One end of the second resistor 26 is connected to the other end of the first resistor 25, and the other end of the second resistor 26 is connected to the gate voltage control switch 27. The other end of the second resistor 26 is grounded. The other end of the first resistor 25 and one end of the second resistor 26 are connected to the ¼ wavelength line 22 via the gate voltage control switch 27.

  In the voltage dividing first and second resistors 25 and 26, when a pinch-off voltage is applied to one end of the first resistor 25, an on-voltage appears between the first resistor 25 and the second resistor 226.

  The gate voltage control switch 27 is a switch for outputting either the pinch-off voltage or the on-voltage, and is a switch for applying the on-voltage to the gate terminal 10d of the GaNFET 10 for a predetermined time.

  The gate voltage control switch 27 is connected to a gate voltage control switch pulse source 28 (hereinafter referred to as a pulse source 28) for switching the switch 27. The pulse source 28 supplies a gate voltage control pulse 29 (hereinafter referred to as a control pulse 29) for controlling the switching of the gate voltage control switch 27 to the gate voltage control switch 27. When the control pulse 29 is supplied to the gate voltage control switch 27, the gate voltage control switch 27 outputs an on-voltage only during that time. On the contrary, while the control pulse 29 is not supplied to the gate voltage control switch 27, the gate voltage control switch 27 outputs a pinch-off voltage. The pulse source 28 may be provided outside the gate bias circuit 12 or may be included in the drain bias circuit 11.

  FIG. 3 is a circuit diagram illustrating an example of the gate voltage control switch 20. As shown in FIG. 3, the gate voltage control switch 28 includes, for example, first and second MOSFETs 30 and 31 and an inverting circuit 32. When the circuit shown in FIG. 3 is applied as the gate voltage control switch 28, the drain terminal 30 d of the first MOSFET 30 is connected between the quarter wavelength line 22 and the capacitor 23. The source terminal 30 s of the first MOSFET 30 is connected to one end of the first resistor 25, and the gate terminal 30 g of the first MOSFET 30 is connected to the pulse source 28 via the inverting circuit 32.

  The second MOSFET 31 is arranged in parallel to the first MOSFET 30, and the drain terminal 31 d of the second MOSFET 31 is connected between the quarter wavelength line 22 and the capacitor 23. The source terminal 31 s of the second MOSFET 31 is connected between the first resistor 25 and the second resistor 26, and the gate terminal 31 g of the second MOSFET 31 is connected to the pulse source 28.

  When the control pulse 29 is supplied to the gate voltage control switch 27 from the pulse source 28, the control pulse 29 is branched into two, one of which is inverted by the inverting circuit 32 and supplied to the gate terminal 30g of the first MOSFET 30. Is done. The other branched control pulse 29 is supplied to the gate terminal 31 g of the second MOSFET 31. Then, the first MOSFET 30 is opened and the second MOSFET 31 is closed. As a result, the ON voltage is applied to the gate terminal 10g (FIG. 1) of the GaNFET 10 only while the second MOSFET 31 is closed.

  On the contrary, while the control pulse 29 is not supplied to the gate voltage control switch 27, the first MOSFET is closed and the second MOSFET is open. As a result, the pinch-off voltage is applied to the gate terminal 10g (FIG. 1) of the GaNFET 10 only while the first MOSFET 30 is closed.

  If the pulse width of the gate voltage control pulse 29 is Tg and the pulse width of the drain voltage control pulse 20 is Td, the gate voltage control pulse 29 is Tg ≦ Td−Tv1 (where Tv1 is the drain voltage). A pulse having a pulse width that satisfies a time from when the voltage control switch 18 is closed to when the drain voltage reaches the drive voltage is applied. The reason for this will be described later.

  The bias circuit for GaN FET according to the embodiment described above applies an on-voltage as a gate voltage only while a drive voltage is applied as a drain voltage to the GaNFET 10. Hereinafter, the operation of the GaNFET 10 to which the GaNFET bias circuit according to the embodiment is connected will be described with reference to FIG. Here, as described above, the driving voltage of the GaNFET 10 is 25 V, the on-voltage is −1.5 V, the pinch-off voltage is −5 V, the output voltage of the positive constant voltage power supply 17 is 25 V, and the negative constant voltage power supply 24 is used. The operation of the GaNFET 10 when the output voltage of -5V is −5V and the voltage divided by the first resistor 25 and the second resistor 26 is −1.5V will be described.

  FIG. 4 shows a high-frequency signal input to the GaNFET 10 (FIG. 4A), a modulated high-frequency signal output from the GaNFET 10 (FIG. 4B), and a drain voltage supplied to the drain voltage control switch 18. The control pulse 20 (FIG. 2C), the drain voltage applied to the drain terminal 10d of the GaNFET 10 (FIG. 3D), and the gate voltage control pulse 29 supplied to the gate voltage control switch 27 It is a figure which shows the relationship between the figure (e)) and the gate voltage (the figure (f)) applied to the gate terminal 10g of GaNFET10.

  First, when the drain voltage control switch 18 is open and the gate voltage control switch 28 is in a state of outputting a pinch-off voltage, a high-frequency signal (CW wave) having a constant intensity is applied to the gate terminal 10g of the GaNFET 10 (FIG. 4A). ) Is entered. At this time, −5V, which is a pinch-off voltage, is applied to the gate terminal 10g of the GaNFET 10, and no voltage is applied to the drain terminal 10d. Therefore, the GaNFET 10 is not in a state where it can amplify the high frequency signal, and the high frequency signal input to the GaNFET 10 is not amplified (FIG. 4B).

  In a state where a high-frequency signal is input to the GaNFET 10, a drain voltage control pulse 20 having a pulse width Td is supplied from the drain voltage control pulse source 19 to the drain voltage control switch 18 (FIG. 4C). Then, the drain voltage control switch 18 is closed for the time of the pulse width Td, and a positive drain voltage is applied to the drain terminal 10 d of the GaNFET 10.

  The drain voltage does not become the driving voltage of 25 V at the same time as the drain voltage control switch 18 is closed, but starts to increase from the moment when the drain voltage control switch 18 is closed, and becomes 25 V after a predetermined time Tv1 has elapsed. Further, the drain voltage does not become 0 V at the same time when the drain voltage control switch 18 is opened, but starts to decrease from the moment when the drain voltage control switch 18 is opened, and becomes 0 V after a predetermined time Tv2 has elapsed (FIG. 4). (D)).

  As shown in FIG. 4D, the drain voltage does not change following the drain voltage control pulse 20 because the amount of change in the drain voltage is large. In the case of GaNFET 10, such a phenomenon occurs because the device is used by applying a large voltage in this way. However, in the case of a device such as GaAsFET that cannot apply a large voltage, the drain voltage is used for controlling the drain voltage. The phenomenon of not changing following the pulse 20 does not occur.

  On the other hand, a gate voltage control pulse 29 having, for example, a pulse width Tg (= Td−Tv1) is supplied from the gate voltage control pulse source 28 to the gate voltage control switch 27 in a state where a high-frequency signal is input to the GaNFET 10. To do. The gate voltage control pulse 29 is input to the gate voltage control switch 27, for example, at the moment when the drain voltage reaches 25 V, which is the drive voltage (FIG. 4E). Then, the gate voltage control switch 27 outputs the on-voltage for the time (Td−Tv1) from the moment when the drain voltage reaches 25V to the moment when the drain voltage starts to drop from 25V.

  The gate voltage control switch 27 only needs to output the on-voltage while the drain voltage is the drive voltage. Therefore, a gate voltage control pulse whose pulse width is shorter than Tg may be input to the gate voltage control switch 27 after the drain voltage reaches 25 V, which is the drive voltage. As described above, the reason why the gate voltage control switch 27 should output the on-voltage only while the driving voltage is applied to the GaNFET 10 will be described later.

  The gate voltage becomes −1.5 V which is the ON voltage at the same time when the control pulse 29 is supplied to the gate voltage control switch 27. Further, the gate voltage becomes −5 V which is the pinch-off voltage at the same time when the supply of the control pulse 29 is finished (FIG. 4F). As shown in FIG. 4F, the gate voltage changes following the gate voltage control pulse 29 because the change amount of the gate voltage is extremely small with respect to the change amount of the drain voltage. .

  When the drain voltage and the gate voltage are applied to the GaNFET 10 as described above, the GaNFET 10 can stably amplify the high-frequency signal for the time (= time Tg) in which the drain voltage is the drive voltage and the gate voltage is the on-voltage. It becomes a state. Therefore, the high frequency signal is amplified only during this Tg (FIG. 2B). That is, a high-frequency signal (CW wave) having a constant intensity input to the GaN FET is modulated into a pulse signal having a pulse width Tg.

  Here, with reference to FIG. 5, the reason why the gate voltage control switch 27 only needs to output the on-voltage while the drive voltage is applied to the GaNFET 10 will be described. FIG. 5 is a diagram showing the relationship between the drain voltage and the current flowing in the GaN FET (drain current) for each gate voltage.

  In the case of a FET that is used by applying a high voltage, such as a GaN FET, the FET is designed and manufactured so that a desired gain can be stably obtained when a high voltage is applied as a drain voltage to the drain terminal. Therefore, when a low voltage is applied as a drain voltage to the drain terminal of such a GaNFET, the mutual conductance increases and a gain larger than a desired gain is obtained.

  As shown by the solid line in FIG. 5, when the gate voltage control switch 27 outputs an on-voltage (−1.5 V) and this voltage is applied to the GaNFET 10, when a drain voltage is applied to the GaNFET 10, A drain current flows accordingly. When the drain voltage is low, a gain larger than the desired gain can be obtained, so that the drain current gains a large gain and amplifies and eventually oscillates.

  That is, when a low drain voltage is applied to the GaNFET 10 in a state where the gate voltage control switch 27 outputs an on-voltage, the relationship is unstable on the graph (FIG. 5) showing the relationship between the drain voltage and the drain current. Unnecessary oscillation occurs because it passes through the region. Since this oscillation is superimposed on the high frequency signal output from the GaNFET 10, the quality of the output waveform is degraded.

  However, even if a drain voltage is applied to the GaNFET 10 in a state where the gate voltage control switch 27 outputs a pinch-off voltage (−5V) and this voltage is applied to the GaNFET 10 as shown by a dotted line in FIG. The drain current that flows with the voltage is smaller than the drain current that flows when the GaNFET 10 is in an amplifiable state. Furthermore, since the GaNFET 10 is not in an amplifiable state, the drain current is not amplified with gain. Therefore, the oscillation of the drain current is suppressed.

  That is, even when a low drain voltage is applied to the GaNFET 10 in a state where the gate voltage control switch 27 outputs a pinch-off voltage, the relationship is shown on the graph (FIG. 5) showing the relationship between the drain voltage and the drain current. Since it does not pass through the unstable region, unnecessary oscillation is suppressed. In other words, if the gate voltage control switch 27 is in a state of outputting the pinch-off voltage when a low drain voltage is applied to the GaNFET 10, unnecessary oscillation is suppressed. Therefore, the GaN FET bias circuit according to this embodiment may control the gate voltage control switch 27 so that the ON voltage is applied only while the drive voltage is applied to the GaNFET 10. In order to realize this, the gate voltage control pulse 29 having a pulse width Tg satisfying Tg ≦ Td−Tv1 is supplied to the gate voltage control switch 27 only while the drive voltage is applied to the GaNFET 10. Good.

  On the other hand, the conventional bias circuit for GaNFET is a bias circuit in which an on-voltage is always applied to the GaNFET and a drain voltage as shown in FIG. 4D is applied to the drain terminal of the GaNFET in that state. It was. Therefore, a low drain voltage is applied to the drain terminal of the GaN FET at the stage where the drain voltage starts to rise and before the drain voltage finishes dropping. As a result, the drain current oscillates, and this oscillation is superimposed on the high-frequency signal output from the GaN FET, degrading the quality of the output waveform.

  As described above, the GaN FET bias circuit according to the present embodiment applies the ON voltage as the gate voltage only while the drive voltage is applied as the drain voltage to the GaNFET 10. Therefore, according to the bias circuit for a GaNFET according to the present embodiment, unnecessary oscillation can be suppressed and the GaNFET 10 can output a high-quality signal having a high-quality output waveform.

  Although the embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 ... GaNFET
10d ... Drain terminal 10g ... Gate terminal 10s ... Source terminal 11 ... Drain bias circuit 12 ... Gate bias circuits 13, 14 ... DC cut capacitors 15, 22 ... 1 / 4 wavelength line 16, 23 ... capacitor 17 ... positive constant voltage power supply 18 ... drain voltage control switch 19 ... pulse source 20 (for drain voltage control switch) ... drain voltage control Pulse (control pulse)
21 ... MOSFET
21d ... Drain terminal 21s ... Source terminal 21g ... Gate terminal 24 ... Negative constant voltage power supply 25 ... First resistor 26 for voltage division ... Second resistor 27 for voltage division ... Gate voltage control switch 28 ... Pulse source 29 (for gate voltage control switch) ... Gate voltage control pulse (control pulse)
30: First MOSFET
31 ... Second MOSFET
30d, 31d ... drain terminals 30g, 31g ... gate terminals 30s, 31s ... source terminals 32 ... inverting circuit

Claims (6)

A bias circuit for a GaNFET that applies a desired voltage to the GaNFET,
A positive constant voltage power source for outputting the driving voltage of the GaN FET;
A drain voltage control switch connected between the positive constant voltage power source and the drain terminal of the GaNFET, and supplying the drive voltage output from the positive constant voltage power source to the drain terminal for a predetermined time;
A negative constant voltage power supply that outputs the pinch-off voltage of the GaN FET;
A voltage dividing resistor that divides the pinch-off voltage into an on-voltage of the GaN FET;
Between the negative constant voltage power supply and the gate terminal of the GaNFET, and between the voltage dividing resistor and the gate terminal of the GaNFET, while the drive voltage is applied to the drain terminal, A gate voltage control switch for supplying the ON voltage to the gate terminal;
A bias circuit for a GaNFET, comprising: The gate voltage control switch includes a first MOSFET connected between the negative constant voltage power source and the gate terminal of the GaN FET;
A second MOSFET connected between the voltage dividing resistor and the gate terminal of the GaNFET;
An inverting circuit connected to the gate terminal of the first MOSFET;
The GaN FET bias circuit according to claim 1, comprising: A pulse source for a drain voltage control switch for supplying a drain voltage control pulse for closing the switch to the drain voltage control switch;
A pulse source for a gate voltage control switch for supplying a gate voltage control pulse having a narrower pulse width than the drain voltage control pulse for causing the gate voltage control switch to output the on-voltage from the switch;
Further comprising
The pulse voltage source for the gate voltage control switch supplies the gate voltage control pulse to the gate voltage control switch at a timing while the drain voltage control pulse is supplied to the drain voltage control switch. The bias circuit for a GaN FET according to claim 1, wherein the bias circuit is a GaN FET bias circuit. The gate voltage control switch includes a first MOSFET connected between the negative constant voltage power source and the gate terminal of the GaN FET;
A second MOSFET connected between the voltage dividing resistor and the gate terminal of the GaNFET;
An inverting circuit connected to the gate terminal of the first MOSFET;
Comprising
The pulse source for the gate voltage control switch has an inverted pulse of the gate voltage control pulse applied to the first MOSFET at a timing while the drain voltage control pulse is supplied to the drain voltage control switch. 4. The bias circuit for a GaNFET according to claim 3, wherein the gate voltage control pulse is supplied to the second MOSFET while being supplied.   The gate voltage control switch is configured to open the first MOSFET by supplying an inversion pulse of the gate voltage control pulse while the drive voltage is applied to the drain terminal, and to control the gate voltage. The on-voltage is supplied to the gate terminal while the driving voltage is applied to the drain terminal by closing the second MOSFET by supplying a working pulse. 4. A bias circuit for a GaNFET as described in 4.   The time for which the driving voltage is applied to the drain terminal of the GaNFET and the time for which the on-voltage is applied to the gate terminal of the GaNFET are substantially equal to each other. The bias circuit for GaNFET in any one.

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