JP2013178787A - Flash memory device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash memory device configured to allow a cache read operation of preceding page data.SOLUTION: The flash memory device includes an array of memory cells for storing data pages, one or more buffers for retrieving the data pages, and a logic mechanism that, responsive to a plurality of commands, transfers the data pages between the buffers and a host. Each command subsequent to a first command instructs retrieval of a data page whose address either precedes or exceeds by more than 1, the address of the data page retrieved by the immediately preceding command, and at least one command does not explicitly specify the address of its retrieved data page. Another similar flash memory device uses two buffers to implement cache reads of data pages whose addresses are specified arbitrarily in the commands subsequent to the first command.

Description

  The present invention relates to the field of flash memory devices, and more particularly to the use of cache read operations in flash memory devices.

  Flash memory devices have been known for many years. Standard flash memory devices known in the art store data in a memory array arranged in groups called pages or blocks.

  An example of a NAND flash memory device known in the art is the device number MT29F2G08AABWP from Micron Technologies. The device data sheet (DS in the text below) is hereby fully incorporated by reference for all purposes.

  When a host connected to a flash memory device (eg, a computer, controller or other similar device connected to flash memory) exchanges data with the flash memory device, an internal buffer (usually called a page buffer) Or a register), the entire data page is written to or read from the memory array simultaneously in a single operation.

  When the host asserts a request to direct the flash memory device to read a page of data, that page of data is transferred from the memory array to the page buffer. Only after the page's data has been completely read into the page buffer, the host can assert a request to direct the flash memory device to begin a new operation.

  The time required for data exchange between the host and the flash memory device includes both the host to buffer and buffer to memory array transfer periods. As the data page size of existing flash memory devices increases, the host⇔buffer transfer time increases as well, corresponding to the buffer⇔memory array transfer time.

  For example, in a NAND flash memory device known in the art with 2 kilobytes of data pages, the host⇔buffer transfer time is typically 50-100 microseconds per page and the buffer⇔memory array Page read time is 20-50 microseconds per page and buffer memory array page program (write) time is 200-800 microseconds per page.

  Thus, to increase system throughput, some flash memory devices include an additional data buffer, or cache buffer. This allows simultaneous data transfer between the host and this cache buffer and between the page buffer and the memory array.

With a cache buffer in the flash memory device, page data is read from the memory array to the page buffer and then immediately transferred to the cache buffer. This “frees” the page buffer to receive the next page data from the memory array. In other words, the host can assert a request to the flash memory device to read the next page data from the memory array even before the previous page data has been completely transferred from the cache buffer. .

  Thus, implementing a cache buffer for page read operations substantially reduces transfer delay time and increases system throughput.

  Read operations using the cache buffer are referred to as “cache read” or “read in cache” or “cache mode page read” (all depending on the particular flash device vendor). Read operations respond to specific commands issued by the host.

  In practice, flash memory devices are provided for reading large amounts of data that are written sequentially to flash memory. An example is a group of file systems containing several kilobytes of data that are always written to and read from a flash memory device by the operating system as a single “bulk”. Other examples include information “streamed” by multimedia sources (eg, video and audio recoding systems), or images taken with a digital camera.

  In these cases, the next page data requested to be read from the flash memory device is likely to be physically contiguous page data stored in the memory array. Flash memory devices known in the art make use of this assumption when implementing a cache buffer for page read operations. For example, if the current read operation is reading page data from memory array address N, the next cache read operation will always read page data from memory array address N + 1.

  However, it is possible that the speculation of “next consecutive page” is no longer valid. One such case is an application that needs to read data pages in "reverse" order. For example, a LIFO (Last In First Out) procedure is executed. Systems that require the option of recording different types of events over time and sometimes retrospecting specific types of events from recent records may require implementation of such applications. In such a system, it would be very beneficial to use the address of the last record (ie, page data) to quickly read “previous” page data.

  Existing flash memory devices used for cache read operations are not configured to respond to such a need. In other words, flash memory devices known in the art that include a cache buffer provide for reading page data in an "reverse" (ie, decreasing page-to-page address) order. I can't. To accomplish reading the “previous” page data, existing methods simply apply “regular” (non-cached) page read operations and do not utilize a cache buffer.

  However, applying “regular” page read operations reduces system throughput when compared to regular cache read operations.

Accordingly, a primary object of the present invention is to overcome the disadvantages of the prior art by introducing a flash memory device configured to allow cache read operations of previous page data. The flash memory device according to the present invention is further configured to allow cache read operations at any address.

  The logic mechanism reacts to commands received from the host to transfer data pages between the flash memory device and the host. The logic mechanism responds to two different commands: a “normal” cache read command (ie, an address incremented by 1) and a “reverse” cache read command (ie, an address decremented by 1).

  In accordance with the present invention, a flash memory device is provided that includes: (A) An array of memory cells for storing a plurality of data pages. (B) At least one buffer for retrieving a plurality of data pages. And (c) a logic mechanism that reacts to multiple commands to transfer multiple data pages for retrieval to the host. In this case, each of the second and subsequent commands directs the flash memory device to retrieve the data page at the address that precedes the address of the data page retrieved by the previous command in the array. And at least one of the commands lacks an explicitly specified address of the data page to be retrieved.

  According to the first flash memory device according to the invention, the decrementing of the address of the data page that is read continuously is applied without requiring that the address of the data page be explicitly specified. . The first flash memory device includes an array of memory cells for storing data pages, one or more buffers for retrieving data pages, and buffering data pages retrieved by previous commands. Contains a logic mechanism for transfer between the host and the host.

  This last limitation, as described herein in accordance with the present invention, that at least one command lacks an explicitly specified address, and similar limitations of other methods and flash memory devices, make this invention all This distinguishes it from the conventional technique of explicitly specifying an address and thus implicitly specifying all increments.

  Preferably, the address of the data page fetched by the second and subsequent commands precedes the address of the data page fetched by the previous command by a fixed decrement. Most preferably, the fixed decrement is physically assembled at -1.

  Each of the second and subsequent commands includes a parameter value that specifies how far the address of the data page retrieved by that command precedes the address of the data page retrieved by the previous command. It is preferable.

  The flash memory device preferably includes two buffers, a page buffer and a cache buffer. This allows simultaneous data transfer of two data pages, one of the two data pages being transferred between the array of memory cells and the page buffer, and the other of the two data pages. Are transferred between the cache buffer and the host.

In accordance with the present invention, there is also provided a method for reading a data page from flash memory comprising the following steps. (A) issuing a first command by the host to instruct the flash memory to retrieve the first data page; (B) In response to the first command, fetching the first data page by the logic mechanism of the flash memory. (C) issuing at least one second command by the host that instructs the flash memory to retrieve the data page corresponding to the address preceding the address of the data page retrieved in response to the previous command; . Note that at least one second command lacks explicit designation of the address of the corresponding data page. And (d) retrieving a corresponding data page by a logic mechanism in response to each of the second commands.

  The address of each data page fetched by the command following the data page fetched by the first command is located in the flash memory array immediately before the address of the data page fetched by the previous command. Is preferred.

  Each of the second commands preferably includes a parameter value that specifies how far the address of the data page retrieved by that command precedes the address of the data page retrieved by the immediately preceding command.

  Each of the second commands is preferably executed as a cache read command.

  In accordance with the present invention, there is also provided a flash memory device comprising: (A) An array of memory cells for storing a plurality of data pages. (B) At least one buffer for retrieving a plurality of data pages. And (c) a logic mechanism that reacts to multiple commands to transfer multiple data pages for retrieval to the host. In this case, each of the second and subsequent commands causes the flash memory device to fetch a data page at an address greater than 1 to the address of the data page fetched by the previous command in the array. Direct to. And at least one of the subsequent commands lacks an explicitly specified address of the data page to be retrieved.

  Each of the second and subsequent commands includes a parameter value that specifies how much the address of the data page retrieved by that command exceeds the address of the data page retrieved by the previous command. It is preferable.

  The flash memory device preferably includes two buffers, a page buffer and a cache buffer. This allows simultaneous data transfer of two data pages, one of the two data pages being transferred between the array of memory cells and the page buffer, and the other of the two data pages. Are transferred between the cache buffer and the host.

  In accordance with the present invention, there is also provided a method for reading a data page from flash memory comprising the following steps. (A) issuing a first command by the host to instruct the flash memory to retrieve the first data page; (B) In response to the first command, fetching the first data page by the logic mechanism of the flash memory. (C) directs the flash memory to retrieve the corresponding data page at an address greater than 1 to the address of the data page retrieved by the host in response to the previous command; The step of issuing a command. Note that at least one of the at least one second command lacks an explicit designation of the address of the corresponding data page. And (d) retrieving a corresponding data page by a logic mechanism in response to each of the second commands.

Each of the second commands preferably includes a parameter value that specifies how much the address of the corresponding data page retrieved by that command exceeds the address of the data page retrieved by the previous command. .

  Each of the second commands is preferably executed as a cache read command.

  In accordance with the present invention, there is also provided a flash memory device comprising: (A) An array of memory cells for storing a plurality of data pages. (B) Two buffers. In order to retrieve a plurality of data pages, one of the buffers is a page buffer and the other buffer is a cache buffer. This at least partially enables simultaneous data transfer of two data pages, one of the two data pages being transferred between the array of memory cells and the page buffer, and two data pages The other is transferred between the cache buffer and the host. And (c) a logic mechanism responsive to multiple commands for transferring at least two of the multiple data pages retrieved to the host. The transfer is executed through the page buffer and through the cache buffer. Then, each of the second and subsequent commands of the plurality of commands directs the flash memory device to retrieve a data page from an arbitrarily designated address.

  Each of the second and subsequent commands includes a parameter value that specifies how different the address of the corresponding data page retrieved by that command is from the address of the data page retrieved by the previous command. It is preferable.

  Any address is preferably specified explicitly.

  In accordance with the present invention, there is also provided a method for reading a data page from flash memory comprising the following steps. (A) issuing a first command by the host to instruct the flash memory to retrieve the first data page; (B) In response to the first command, fetching the first data page by the logic mechanism of the flash memory. (C) The host issues at least one cache read command that instructs the flash memory to retrieve the corresponding data page from an arbitrarily designated address. And (d) retrieving a corresponding data page by a logic mechanism in response to each of the second commands.

  Each of the cache read commands preferably includes a parameter value that specifies how different the address of the corresponding data page retrieved by that command is from the address of the data page retrieved by the immediately preceding command.

  Each cache read command preferably explicitly specifies the address of the corresponding data page retrieved by the command.

  In accordance with the present invention, there is also provided a flash memory device comprising: (A) An array of memory cells for storing a plurality of data pages. (B) Page buffer. (C) Cache buffer. And (d) one of the plurality of data pages between the array of memory cells and the page buffer, while the other of the plurality of data pages is transferred between the cache buffer and the host. , A logic mechanism that reacts to multiple commands to at least partially transfer at the same time. Note that the address of the data page transferred between the array of memory cells and the page buffer precedes the address of the data page transferred between the cache buffer and the page host in the array. .

  The address of the data page transferred between the array of memory cells and the page buffer precedes the address of the data page transferred between the cache buffer and the host in the array by a fixed decrement. It is preferable. The fixed decrement is more preferably -1.

  According to the present invention, a method including the following steps is also provided. (A) issuing a first command by the host to instruct the flash memory to retrieve the first data page; (B) issuing a second command by the host to instruct the flash memory to retrieve the second data page; (C) in response to the first and second commands, at least a portion of the second data page from the array of memory cells to the page buffer and the first data page from the cache buffer to the host. Removing substantially simultaneously. Note that the address of the second data page precedes the address of the first data page in the array.

  The address of the second data page is preferably located in the array immediately before the address of the first data page.

  In accordance with the present invention, there is also provided a flash memory device comprising: (A) An array of memory cells for storing a plurality of data pages. (B) Page buffer. (C) Cache buffer. And (d) one of the plurality of data pages between the array of memory cells and the page buffer, while the other of the plurality of data pages is transferred between the cache buffer and the host. , A logic mechanism that reacts to multiple commands to at least partially transfer at the same time. Note that the address of the data page transferred between the array of memory cells and the page buffer is the address of the data page transferred between the cache buffer and the page host in the array. Greater exceed.

  According to the present invention, a method including the following steps is also provided. (A) issuing a first command by the host to instruct the flash memory to retrieve the first data page; (B) issuing a second command by the host to instruct the flash memory to retrieve the second data page; (C) in response to the first and second commands, at least a portion of the second data page from the array of memory cells to the page buffer and the first data page from the cache buffer to the host. Removing substantially simultaneously. Note that the address of the second data page exceeds the address of the first data page by more than 1 in the array.

  Other features and advantages of the present invention will become apparent from the following drawings and description.

For a better understanding of the present invention in connection with its embodiments, reference is made to the accompanying drawings. In the drawings, like numerals refer to corresponding sections or elements throughout.
1 is a block diagram illustrating a flash memory device according to the present invention. FIG. FIG. 6 is a timing diagram of the method of the present invention representing a process applied between a host and flash memory to read a previous data page.

The present invention is a flash memory device and method configured to allow cache read operations for both previous and next data pages in a block. Such a configuration is required, for example, for systems that require the option of recording different types of events over time, and sometimes retrospectively reading specific types of events from recent records.

  Existing methods that address such a need apply regular (non-cached) page read operations. Thus, unlike regular read commands according to the prior art, the configuration of the flash memory device according to the present invention addresses the need to read data pages in any order while taking advantage of the advantages of the cache buffer. .

  A flash memory device according to the present invention includes a memory array of memory cells for storing data pages. A host device connected to the flash memory device transfers a data page via a data signal through an input / output (I / O) interface unit.

  The flash memory device according to the present invention includes two buffers, a page buffer and a cache buffer. The entire data page is written from the page buffer to the memory array and read from the memory array to the page buffer, but the cache buffer is between the host device and the cache buffer, and Provided to allow simultaneous data transfer between the page buffer and the memory array. Simultaneous data transfer improves the overall throughput of the flash memory device.

  The logic mechanism is responsive to a cache read command received from the host to transfer a data page between the flash memory device and the host. The cache read command in this text is defined as a command that instructs a flash memory device to use both a page buffer and a cache buffer. The logic mechanism is a “normal” cache read command (ie, a positive increment that is an indication of an address incremented by one) and a “reverse” cache read command (ie, an indication of an address that is decremented by one). Reacts to two different commands (negative increments).

  Thus, upon receipt of a “read in cache” command from the host, the address to the last fetched data page is decremented or incremented by 1 for use by subsequent read operations. Such a method increases design flexibility while maintaining maximum throughput.

  For the exemplary command codes and sequences described herein, reference is made to a scheme in which the Micron Technologies part number MT29F2G08AABWP device has been modified in accordance with the principles of the present invention. However, it will be apparent to those skilled in the art that the principles of the present invention can be commonly used on similar command codes and sequences to modify any flash memory device in the industry.

The “reverse” cache read command operation scheme follows the “normal” cache read command operation scheme known in the art, the only difference being that the “normal” cache read command is While the logic mechanism is activated to increase the address of the data page to be fetched by one, a “reverse” cache read command activates the logic mechanism to decrease this address by one. Except this, both caches (including the function of ready / busy signal and execution of command code 0x30 for legitimate read command and command code 0x3F to retrieve the last requested data page) The execution of the read command is based on the same logic.

  One way to provide two “normal” and “reverse” cache read commands is to use similar command codes. For example, a 0x32 read command code may create a pair of cache read commands as follows: A 0x31 command code indicating a "normal" cache read command and a 0x32 command code indicating a "reverse" cache read command. Creating such a pair of cache read commands is not vendor specific and can be applied to modify any flash device cache read command set known in the art.

  Reference is made to FIG. 1, which is a block diagram illustrating a flash memory device 10 according to the present invention. The flash memory device 10 includes a memory array 12 consisting of C1 to Cn memory cells for storing data pages. The host 18 connected to the flash memory device transfers the data page via the data signal 22 through the input / output (I / O) interface unit 28.

  The entire data page is written from page buffer 14 to memory array 12 or read from memory array 12 to page buffer 14. The flash memory device 10 includes an additional data buffer, the cache buffer 16. This is to allow simultaneous data transfer between the host 18 and the cache buffer 16 and between the page buffer 14 and the memory array 12.

  A logic mechanism 20 is also provided for transferring data pages between the flash memory device and the host 18. The logic mechanism 20 responds to “normal” and “reverse” cache read commands received from the host 18 via control signals 24 and data signals 22.

  Optionally, status information is provided from the memory status register 27 connected to the logic mechanism 20 to the host 18 informing the host 18 that the page “N” is ready for the host 18 to read. Status information is transferred from the memory status register 27 to the host device 20 through an input / output (I / O) interface unit 28.

  Reference is now made to FIG. 2, which is a timing diagram 30 of the method of the present invention. This shows the signals exchanged between the host 18 and the flash memory device 10 to read the previous data page.

  Upon receipt of a “ready” signal 32 from the flash memory device 10 that informs the host 18 that the flash memory device 10 is available for reading, the host 18 sends a regular read to the flash memory device 10 along with five ADDRESS cycles. Sends command 34 (eg, as command code 0x30), requests flash memory device 10 to retrieve the data page stored at address “N” (referred to as page “N” in the text), and completes reading Wait for.

  Upon receipt of a legitimate read command 34 from the host 18, the flash memory device 10 retrieves the data page “N” from the memory array to the page buffer (process 36) (typically lasting 30 μs).

  After completely retrieving the data page “N” from the memory array to the page buffer, the flash memory device 10 notifies the host 18 that the page “N” is ready for the host 12 to read. A second “ready” signal 38 is transmitted. Alternatively, host 18 polls memory status register 27 implemented in flash memory device 10 that informs host 18 that page “N” is ready for host 18 to read. .

  At this point, instead of reading the page “N” from the page buffer, the host 18 sends the next command to the flash memory device 10, ie, the previous data page (page “N−1”) from the flash memory device 10. ")" Is requested to the flash memory device 10 to retrieve (eg, as command code 0x32) and a "reverse" cache read command 40 is issued.

  This “reverse” cache read command 40 causes the flash memory device 10 to copy the contents of page “N” (which stores the data of the page most recently read from the memory array) from the page buffer to the cache buffer. Are transferred (process 42). This procedure typically takes 1.5 μs.

  After the page “N” is completely transferred from the page buffer to the cache buffer, the data page address is decremented by 1 (ie, the data page address becomes N−1). The flash memory device 10 then transmits a third “ready” signal 44 that notifies the host 18 that the page “N” is ready for reading by the host 18. At this point, flash memory device 10 sends a third “ready” signal 44 and simultaneously fetches the previous data page (page “N−1”) from the memory array to the page buffer (process 46). ).

  Upon receiving a third “ready” signal 44 from flash memory device 10, host 18 reads page “N” from the cache buffer (process 48). This read operation is performed by the host 18 simultaneously with fetching page “N−1” from the memory array to the page buffer (process 46).

  After host 18 has completely read page “N” from the cache buffer, host 18 issues a second “reverse” cache read command 50 to flash memory device 10 from flash memory device 10. Request to retrieve previous data page (page "N-2").

  The second “reverse” cache read command 50 sends the page buffer to cache buffer from the page buffer only after the transfer of page “N−1” from the memory array to the page buffer is complete. The contents of the page “N-1” are transferred (process 52).

  After the page “N−1” is completely transferred from the page buffer to the cache buffer, the data page address is decremented by 1 (ie, the data page address becomes N−2). The flash memory device 10 then transmits a fourth “ready” signal 54 that notifies the host 18 that the page “N−1” is ready for reading by the host 18. At this point, flash memory device 10 sends a fourth “ready” signal 54 and simultaneously fetches the previous data page (page “N−2”) from the memory array to the page buffer (process 56). ).

Upon receipt of a fourth “ready” signal 54 from flash memory device 10, host 18 reads page “N−1” from the cache buffer. This read operation is performed by the host 18 simultaneously with fetching page “N-2” from the memory array to the page buffer (process 56).

  To end the sequence of “reverse” cache read operations, the host 18 sends the flash memory device 10 the last requested data page from the flash memory device 10 (eg, page “N-M”, in this case). , M> 2) (for example, as a 0x3F command code), issue a cache read end command 60.

  The end cache read command 60 causes the flash memory device 10 to transfer the contents of page “NM” from the page buffer to the cache buffer (process 62).

  After completely transferring the page “NM” from the page buffer to the cache buffer, the flash memory device 10 notifies the host 18 that the page “NM” is ready for the host 18 to read. A final “ready” signal 64 is transmitted.

  At the final stage, upon receiving the final “ready” signal 64 from the flash memory device 10, the host 18 begins to read the last page “NM” from the cache buffer (process 68).

  According to a second embodiment, a flash memory device according to the present invention employs both a page buffer and a cache buffer to increase any address increment between consecutively read data pages received from the host. Operates in response to a cache read command that identifies (ie, a non-zero integer). Thus, the logic mechanism is not only physically incorporated as in the case of the prior art, but also physically incorporated as in the first embodiment of the present invention. It is configured to respond to a cache read command that directs the flash memory device to fetch a data page from any address increment as well as a -1 decrement.

  Note that the target address by any increment must be within memory array size constraints. It should also be noted that a negative address “increment” is defined as address decrement in the text.

  For example, sending a +5 address increment to the flash memory instructs the flash memory to return the page stored at address "N", "N + 5", "N + 10", etc. until the cache read is terminated. . Also, sending an address increment of −5 to the flash memory means that the page stored in the address “N”, “N-5”, “N-10”, etc., will be sent to the flash memory until the cache read is terminated. Instruct to return.

  Preferably, the host sets an arbitrary address increment and sends it as a parameter command to the flash memory device. This parameter command is relevant to all subsequent cache read commands until invalidated.

This can be accomplished, for example, by first sending to the flash memory device a command code 0xAA that identifies any address increment value (eg, “5”) to the flash memory device. In that case, all subsequent cache read commands (either “reverse” or “normal”) are associated with this value. In the case of a “reverse” cache read command, the value received via command code 0xAA is the decrement (“−
In the case of a “normal” cache read command, this value is an indication of an increment number (“+5”). Such a procedure continues as long as successive cache read commands received from the host are accompanied by an address increment command (or until a cache read end command is asserted).

  Alternatively, each cache read command received from the host is accompanied by a configuration parameter command that identifies the address increment for the cache read command. Such a case can be performed, for example, by sending a command code 0xAA to the flash memory device after each cache read command.

  Alternatively, each of the parameters associated with each cache read command received from the host is an explicit specific data page address indication rather than an address increment. Since all read commands following the first read command are executed as a cache read command, this alternative execution of the second embodiment is a prior art non-cache read command that identifies an explicit address. Different.

  Thus, unlike regular read commands according to the prior art, the configuration of the flash memory device according to the present invention addresses the need to read data pages in any order while taking advantage of the cache buffer. .

  It should be noted that the present invention relates to NAND flash memory devices. However, it will be appreciated that other embodiments are possible within the scope of the present invention, and thus relate to any device and method that can be adapted to operate in response to a cache read command received from a host.

  Although the present invention has been described with respect to specific embodiments thereof, it should be understood that the above description is not meant to be limiting, as further modifications will be possible to those skilled in the art. Such modifications are also intended to be covered within the scope of the appended claims.

Claims (1)

(A) an array of memory cells for storing a plurality of data pages;
(B) comprising at least one buffer for retrieving the plurality of data pages; and (c) a logic mechanism responsive to a plurality of commands for transferring the retrieved plurality of data pages to a host. A flash memory device,
Each of the second and subsequent commands directs the flash memory device to retrieve a data page at an address in the array that precedes the address of the data page retrieved by the previous command; and A flash memory device, wherein at least one of the plurality of commands lacks an explicitly specified address of the retrieved data page.

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