JP2013172267A - Digital data transmitter, digital data receiver, and digital data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital data transmission system in which a data signal and a clock signal can be transmitted so that phase rotation in the propagation path can be dealt with, without requiring a clock reproduction circuit on the reception side.SOLUTION: In the transmitter, a QPSK modulation signal for transmitting a signal, obtained by performing differential coding of a data signal twice, as an in-phase component, and transmitting a strobe signal, formed of the clock signal and a signal subjected to differential coding, as a quadrature component is formed. In the receiver, the data signal is extracted by performing differential decoding twice for the in-phase component signal obtained by demodulating the QPSK modulation signal received, and the clock signal is extracted from the in-phase component signal and the quadrature component signal obtained by demodulation. Even if the in-phase component signal and the quadrature component signal obtained by demodulation have a phase rotation, a correct data signal can be extracted and a clock signal having alternating logical values can be extracted.

Description

  The present invention relates to a digital data transmitting apparatus, a digital data receiving apparatus, and a digital data transmission system, and in particular, can facilitate clock recovery on the receiving side.

  In a digital communication system, it is necessary to determine a received digital data signal (hereinafter simply referred to as a data signal) at a correct timing, specifically, at a timing when the eye pattern is most open. The timing shift is a major cause of symbol (bit value) determination errors. Therefore, in wired digital communication, a clock signal is transmitted in parallel with the transmission signal from the transmission side to the reception side, or a clock signal is transmitted from the reception side to the transmission side and a data signal is transmitted in synchronization therewith. There are many cases where a method such as doing is taken.

  However, in wireless communication, the transmission band is limited, and the clock signal is generally regenerated from the received signal. As a clock recovery circuit for recovering a clock signal, there are a band-pass filter method, a closed loop method, and the like. Both methods recover a clock signal from a received signal.

  The bandpass filter method and the closed loop method have the following problems.

  First, in order to regenerate the clock signal, it is necessary to transmit a signal that does not include communication information called a preamble at a head portion of the data signal for a certain period of time. Preamble transmission results in degradation of transmission efficiency. In particular, the overhead becomes particularly noticeable when a short data signal is transmitted.

  Second, when the same symbol is continued in the data signal, the received signal is not changed, and the clock cannot be reproduced well. In order to avoid this, in wired communication, it is common to perform coding so that the same symbols do not continue. For example, 64B / 66B encoding is adopted in 10 Gigabit Ethernet (registered trademark). In addition, 4B / 5B, 8B / 10B encoding, and the like are employed in various communication methods. The total number of bits increases in the encoded data signal, and the transmission efficiency deteriorates. In ETC (non-stop automatic toll collection system), Manchester encoding is performed so that the waveform always changes. This is equivalent to sending 1-bit data in 2 symbol periods. Yes, the transmission capacity with respect to frequency is reduced.

  In order to solve these problems, Patent Document 1 proposes that a clock signal is applied to form a strobe signal and then sent in parallel with the data signal. This method eliminates the need for a clock recovery circuit for recovering a clock signal from a received signal that does not directly include clock information on the receiving side, and accordingly, in digital communication such as an increase due to a preamble or data encoding. Transmission of the overhead part is also unnecessary. The technology described in Patent Document 1 is configured to send 1-bit information in a data signal using two symbols (symbols of in-phase component (I channel) and quadrature component (Q channel)) related to the data signal and the strobe signal. However, since the phase determined by the combination of two symbols is shifted so that the constellation indicating the phase and amplitude of the signal does not pass through the center of the coordinates, the variation in amplitude is small and the band is easily narrowed.

JP 2000-196688 A

  However, in the technique described in Patent Document 1, it is necessary to match the absolute phases of the transmission side and the reception side. In wireless communication, since the phase rotates in the propagation path, it is necessary to prepare a header portion and align the axes of the I channel and the Q channel in order to match the absolute phase. However, this reduces the transmission efficiency and increases the circuits and processing.

  Therefore, a digital data transmission device, digital data reception device, and digital data transmission system capable of transmitting a data signal and a clock signal so as to be able to cope with phase rotation in the propagation path without requiring a clock recovery circuit on the reception side are desired. It is rare.

  A first aspect of the present invention is a digital data transmitting apparatus for forming and transmitting a digital modulation signal including information of a data signal and a clock signal having a cycle of two symbol periods of the data signal, and (1) Differential encoding repetition means for performing differential encoding on the data signal a predetermined number of times, and (2) a differential encoding repetition signal that is an output signal from the differential encoding repetition means and the clock signal, Strobe signal forming means for forming a strobe signal that does not change when the symbol of the differential encoding repetition signal changes but does not change when the symbol of the differential encoding repetition signal does not change, and (3) the differential encoding One of the repetitive signal and the strobe signal is input to its own in-phase component input terminal, and the other is input to its own quadrature component input terminal. And having a digital modulation means for forming a digital modulation signal to cause the phase change by a combination of items.

  The second aspect of the present invention is a digital data receiving apparatus for receiving a digital modulation signal transmitted by the digital data transmitting apparatus of the first aspect of the present invention, wherein (1) the received digital modulation signal is demodulated and an in-phase component signal and A digital demodulating means for outputting a quadrature component signal; (2) performing differential decoding a predetermined number of times on a signal that is a differentially encoded repeated signal among the in-phase component signal and the quadrature component signal; A differential decoding repetition means for extracting a data signal to be transmitted by the digital data transmission device; and (3) a signal that is a strobe signal among the in-phase component signal and the quadrature component signal. And a clock extracting means for extracting a clock signal to be transmitted.

  The digital data transmission system of the third aspect of the present invention is characterized in that the digital data transmission apparatus of the first aspect of the present invention and the digital data reception apparatus of the second aspect of the present invention are opposed to each other via a propagation path. To do.

  According to the digital data transmission device, digital data reception device, and digital data transmission system of the present invention, the data signal and the clock signal can be used so that the reception side can cope with the phase rotation in the propagation path without using the clock recovery circuit. Can be transmitted.

It is a block diagram which shows the structure of the digital data transmitter which concerns on 1st Embodiment. It is a block diagram which shows the structure of the digital data receiver which concerns on 1st Embodiment. It is explanatory drawing which shows the constellation in the QPSK modulator of 1st Embodiment. It is explanatory drawing which described each part timing chart in the digital data transmitter of 1st Embodiment in the format of a truth table. It is explanatory drawing which showed each part timing chart of the digital data receiver of 1st Embodiment in case a phase rotation is 0 degree | times by description with truth table. It is explanatory drawing which showed each part timing chart of the digital data receiver of 1st Embodiment in case a phase rotation is 90 degree | times by description with truth table. It is explanatory drawing which showed each part timing chart of the digital data receiver of 1st Embodiment in case a phase rotation is 180 degree | times by description with truth table. It is explanatory drawing which showed the timing chart of each part of the digital data receiver of 1st Embodiment in case a phase rotation is 270 degree | times by truth table description. It is a block diagram which shows the structure of the digital data transmitter which concerns on 2nd Embodiment. It is a block diagram which shows the structure of the digital data receiver which concerns on 2nd Embodiment.

(A) First Embodiment Hereinafter, a first embodiment of a digital data transmitting device, a digital data receiving device, and a digital data transmission system according to the present invention will be described with reference to the drawings.

(A-1) Configuration of First Embodiment A digital data transmission system according to the first embodiment includes a digital data transmission device 1 according to the first embodiment and a digital data reception device according to the first embodiment. 2 and facing each other across the propagation path 3.

  FIG. 1 is a block diagram showing a configuration of the digital data transmitting apparatus 1 according to the first embodiment, and FIG. 2 is a block diagram showing a configuration of the digital data receiving apparatus 2 according to the first embodiment.

  In FIG. 1, a digital data transmitting apparatus 1 according to the first embodiment includes three 2-input exclusive OR circuits 11, 13, and 16, two 1-symbol period delay circuits 12 and 14, and QPSK (quadrature phase shift). A keying) modulator 15 and a transmitter 17.

  Each of the exclusive OR circuits 11, 13 and 16 performs an exclusive OR operation on the two input signals and outputs a signal resulting from the operation. Each of the one-symbol period delay circuits 12 and 14 delays an input signal to itself by one symbol period (one time slot) in the data signal.

  The exclusive OR circuit 11 is supplied with the data signal DIN input to the digital data transmitting apparatus 1 and the output signal S12 of the one symbol period delay circuit 12. The 1-symbol period delay circuit 12 is supplied with the output signal S11 of the exclusive OR circuit 11. Therefore, the set of the exclusive OR circuit 11 and the one symbol period delay circuit 12 constitutes a differential encoding circuit, and this differential encoding circuit differentially encodes the data signal DIN.

  The exclusive OR circuit 13 is supplied with the output signal S11 of the exclusive OR circuit 11 and the output signal S14 of the one symbol period delay circuit 14. The 1-symbol period delay circuit 14 is supplied with the output signal S13 of the exclusive OR circuit 13. Therefore, the set of the exclusive OR circuit 13 and the one symbol period delay circuit 14 constitutes a differential encoding circuit, and this differential encoding circuit outputs the output signal S11 of the exclusive OR circuit 11 as a differential encoding. It is to become.

  As described above, in the digital data transmitting apparatus 1 according to the first embodiment, the data signal DIN is continuously subjected to differential encoding by the cascaded two-stage differential encoding circuit.

  The exclusive OR circuit 16 is supplied with a clock signal CLK that defines the phase of the data signal DIN and the output signal S13 of the exclusive OR circuit 13 in synchronization with the data signal DIN. In the case of the first embodiment, one cycle of the clock signal CLK is equal to two symbol periods in the data signal DIN. The exclusive OR circuit 16 forms the strobe signal STB by obtaining an exclusive OR of the clock signal CLK and the output signal S13 of the exclusive OR circuit 13.

  IEEE 1394 defines the same as the formation of the strobe signal STB in the first embodiment. When the symbol changes in the output signal S13 of the exclusive OR circuit 13, the strobe signal STB does not change (continues the same symbol), and the symbol does not change in the output signal S13 of the exclusive OR circuit 13 In the strobe signal STB, the symbol changes. The output signal S13 of the exclusive OR circuit 13 and the strobe signal STB have a relationship that does not change the symbols at the same time. Further, since the strobe signal STB is formed by a logical operation that also uses the clock signal CLK, it includes clock information.

  The output signal S13 (I channel signal) of the exclusive OR circuit 13 is input to the I channel input terminal of the QPSK modulator 15, and the strobe signal STB (Q channel signal) is input to the Q channel input terminal of the QPSK modulator 15. Entered. The QPSK modulator 15 performs QPSK modulation on the two input signals S13 and STB to itself.

  FIG. 3 shows constellations in the QPSK modulator 15 of the first embodiment. In FIG. 3, of the two symbol combinations (0, 0), (0, 1), (1, 1), (1, 0), the value on the left is the I channel signal (of the exclusive OR circuit 13). This is a symbol of the output signal S13), and the value on the right side is the symbol of the Q channel signal (strobe signal STB). By using the strobe signal STB that does not change the symbol simultaneously with the output signal S13 of the exclusive OR circuit 13, as shown in FIG. 3, the transition between (0, 1) and (1, 0) , (0,0) and (1,1) cannot be transitions.

  The transmission unit 17 transmits the QPSK modulation signal S15 output from the QPSK modulator 15 to the propagation path 3. If the propagation path 3 is a wireless propagation path, the transmission unit 17 radiates a transmission signal from the built-in transmission antenna to the air by power amplification or the like. If the propagation path 3 is a wired propagation path, the transmission unit 17 sends a transmission signal to the propagation path 3. The wired propagation path may be an optical fiber. In this case, the transmission unit 17 also performs processing for converting an electrical signal into an optical signal. As described above, the transmission unit 17 has a different internal configuration depending on the propagation path 3 to be applied.

  In FIG. 2, the digital data receiving apparatus 2 of the first embodiment includes a receiving unit 21, a QPSK demodulator 22, three two-input exclusive OR circuits 24, 26, and 27, and two one-symbol period delay circuits 23. , 25 and an error detection circuit 28.

  The receiving unit 21 receives and processes a signal (QPSK modulated signal) transmitted from the digital data transmitting apparatus 1 that has arrived from the propagation path 3. The receiving unit 21 has a symmetric configuration with the transmitting unit 17 described above. If the propagation path 3 is a wireless propagation path, the reception unit 21 performs preamplification, band limitation, and the like on the signal captured by the built-in reception antenna. If the propagation path 3 is a wired propagation path, the receiving unit 21 captures a signal from the propagation path 3. The wired propagation path may be an optical fiber. In this case, the receiving unit 21 performs processing for converting an optical signal into an electrical signal. As described above, the receiving unit 21 has a different internal configuration depending on the propagation path 3 to be applied.

  The QPSK demodulator 22 demodulates the received signal S21 to obtain an I channel signal S22I and a Q channel signal S22Q. Here, since the QPSK demodulator 22 can extract the clock signal at a later stage as will be described later, it may be of quasi-synchronous detection.

  Similar to the transmission side, each of the exclusive OR circuits 24, 26, and 27 performs an exclusive OR operation on two input signals and outputs a signal resulting from the operation, and is delayed by one symbol period. Each of the circuits 23 and 25 delays an input signal to itself by one symbol period in the data signal.

  The SI channel signal S22I is input to the 1 symbol period delay circuit 23, and the 1 symbol period delay circuit 23 delays the I channel signal S22I by one symbol period and supplies the delayed signal S23 to the exclusive OR circuit 24. It is. The exclusive OR circuit 24 also receives the I channel signal S22I itself. Therefore, the set of the exclusive OR circuit 24 and the one symbol period delay circuit 23 constitutes a differential decoding circuit, and this differential decoding circuit differentially decodes the I channel signal S22I.

  The output signal S24 of the exclusive OR circuit 24 is input to the 1 symbol period delay circuit 25, and the 1 symbol period delay circuit 25 delays the output signal S24 of the exclusive OR circuit 24 by one symbol period. The delay signal S25 is given to the exclusive OR circuit 26. The exclusive OR circuit 26 also receives the output signal S24 of the exclusive OR circuit 24 itself. Therefore, the set of the exclusive OR circuit 26 and the one symbol period delay circuit 25 constitutes a differential decoding circuit, and this differential decoding circuit differentially decodes the output signal S24 of the exclusive OR circuit 24. It is.

  As described above, in the digital data receiving device 2 of the first embodiment, the I channel signal S22I obtained by QPSK demodulation is continuously subjected to differential decoding by the cascaded two-stage differential decoding circuit. As a result, the data signal DOUT is reproduced.

  The exclusive OR circuit 27 is provided with an I channel signal S22I and a Q channel signal S22Q. The Q channel signal S22Q is a reproduction of the strobe signal described above. The exclusive OR circuit 27 extracts the clock signal CKOUT from the clock information included in the Q channel signal S22Q by obtaining an exclusive OR of the I channel signal S22I and the Q channel signal S22Q.

  The error detection circuit 28 monitors whether or not the series of symbol values of the clock signal CKOUT is an alternating series of 0 and 1, and if not, the error detection circuit 28 generates a signal S28 indicating that an error has occurred. Output.

  Although omitted in FIG. 2, a circuit for determining a symbol value by applying the data signal DOUT and the clock signal CKOUT is provided at the subsequent stage of the configuration part shown in FIG. 2. This determination circuit functions to determine the symbol value at the most open timing of the eye pattern related to the data signal DOUT. In the case of the first embodiment, since one cycle of the clock signal CKOUT is equal to two symbol periods in the data signal DOUT, the relative value between the data signal DOUT and the clock signal is used to determine the symbol value. When adjusting a correct phase (timing), it is preferable to use the clock signal CKOUT by multiplying the frequency of the clock signal CKOUT by 2 rather than using the clock signal CKOUT as it is. In addition to the adjustment described above, it is preferable to apply a clock signal obtained by multiplying the clock signal CKOUT by 2 as a clock signal when a circuit that processes the data signal DOUT executes processing. Therefore, as will be described later, even if the clock signal CKOUT is extracted after being inverted from the normal phase, a correct symbol value can be determined.

(A-2) Operation of the First Embodiment Next, the operation of the digital data transmission system according to the first embodiment will be described in the order of the operation of the digital data transmission device 1 and the operation of the digital data reception device 2.

  A data signal DIN and a clock signal CLK are input to the digital data transmission device 1 in parallel.

  The data signal DIN is subjected to differential encoding successively by two stages of cascade-connected differential encoding circuits 11, 12, 13 and 14, and is input to the I channel input terminal of the QPSK modulator 15.

  The clock signal is supplied to the exclusive OR circuit 16 together with the signal S13 (I channel signal) after the two-stage differential encoding, and the exclusive OR circuit 16 outputs the strobe signal STB (Q channel signal). ) And input to the Q channel input terminal of the QPSK modulator 15.

  The two input signals S13 and STB input to the QPSK modulator 15 are QPSK modulated, and the obtained QPSK modulated signal S15 is given to the transmission unit 17 and transmitted to the propagation path 3.

  A signal (QPSK modulated signal) transmitted from the digital data transmitting device 1 arrives at the digital data receiving device 2 from the propagation path 3.

  A signal (QPSK modulated signal) arriving from the propagation path 3 is subjected to reception processing by the receiving unit 21 and is given to the QPSK demodulator 22, and QPSK demodulated to obtain an I channel signal S22I and a Q channel signal S22Q.

  The I channel signal S22I obtained by QPSK demodulation is subjected to differential decoding successively by two stages of cascade-connected differential decoding circuits 23, 24, 25 and 26, thereby extracting the data signal DOUT. .

  The I channel signal S22I and the Q channel signal S22Q obtained by the QPSK demodulation are supplied to the exclusive OR circuit 27, and the exclusive OR of these signals is obtained to obtain the clock information included in the Q channel signal S22Q. Is used to extract the clock signal CKOUT.

  When the symbol value series of the extracted clock signal CKOUT is not an alternating series of 0 and 1, the transmission error signal S28 is output from the transmission error detection circuit 28.

  Hereinafter, the operations of the digital data transmitting apparatus 1 and the digital data receiving apparatus 2 will be described by giving specific examples of the data signal DIN.

  FIG. 4 is an explanatory diagram showing a timing chart of each part of the digital data transmitting apparatus 1 with a truth table description.

  The series of data signals DIN to be transmitted is 100101110... As shown in the first line of FIG. In the case of the first embodiment, since the clock signal CLK has two symbol periods as one cycle, as shown in the fourth row of FIG. 4, 1 and 0 alternate in every symbol period. It has become.

  The output signal S11 of the first-stage differential encoding circuit that differentially encodes the data signal DIN is 111001011... As shown in the second row of FIG. However, the calculation is performed assuming that the bit value (default value of the signal S11) before the first bit (first symbol) in the second row is zero. The output signal S13 (I channel signal) of the second-stage differential encoding circuit that differentially encodes the signal S11 is 101110010... As shown in the third row of FIG. Here, the calculation is performed assuming that the bit value (default value of the signal S13) before the first bit (first symbol) in the third row is zero. The strobe signal STB (Q channel signal) obtained from the signal S13 and the clock signal CLK becomes 000100111... As shown in the fifth row of FIG.

  When the above-described I channel signal S13 and Q channel signal STB are viewed in combination for each symbol period (time unit), (1, 0), (0, 0), (1, 0), (1, 1), (1, 0), (0, 0), (0, 1), (1, 1), (0, 1)..., And the I channel signal S13 and the Q channel signal STB by the function of the strobe signal. It can be seen that there is no case in which the symbol values of the symbols change simultaneously. Thus, since the QPSK modulator 15 does not pass through the center of the constellation, the QPSK modulation signal has a small amplitude variation and a narrow band.

  In the propagation path 3, the phase may be rotated. A quasi-synchronous detection type can also be applied as the QPSK demodulator 22, and when a quasi-synchronous detection type is applied, the I channel signal S22I and the Q channel from the QPSK demodulator 22 are subjected to phase rotation in the propagation path 3. Signal S22Q can also have a phase rotation of 0 degrees, 90 degrees, 180 degrees, or 270 degrees.

  FIG. 5 is an explanatory diagram showing a timing chart of each part of the digital data receiving apparatus 2 in a truth table description when the phase rotation is 0 degree (no phase rotation).

  When the phase rotation is 0 degree, the I channel signal S22I and the Q channel signal S22Q from the QPSK demodulator 22 are supplied to the QPSK modulator 15 as shown in the first and fourth lines of FIG. It becomes the same as channel signal S13 and Q channel signal STB (provided that no transmission error has occurred).

  Since the I channel signal S22I is 1011110010 ..., the output signal S24 of the first stage differential decoding circuit that differentially decodes the I channel signal S22I is 111001011 ... as shown in the second row of FIG. Become. However, the calculation is performed assuming that the bit value (default value of the signal S22I) before the first bit (first symbol) in the first row is zero. The output signal DOUT of the second-stage differential decoding circuit that differentially decodes the signal S24 is 100101110... As shown in the third row of FIG. Here, the calculation is performed assuming that the bit value (default value of the signal S24) before the first bit (first symbol) in the third row is zero. The clock signal CKOUT extracted from the Q channel signal S22Q (strobe signal) using the I channel signal S22I is 1010101101 as shown in the fifth row of FIG. 5, and is equal to the clock signal CLK on the transmission side. .

  FIG. 6 is an explanatory diagram showing a timing chart of each part of the digital data receiving device 2 when the phase rotation is 90 degrees with a truth table description.

  Now, a combination for each symbol period of the transmission side I channel signal and Q channel signal is represented by Tx (Ich, Qch), and a combination for the symbol period of the reception side I channel signal and Q channel signal is represented by Rx (I'ch , Q′ch).

  In the case where the phase rotation is 90 degrees, when I′ch and Q′ch on the receiving side are represented by Ich and Qch on the transmitting side, Rx (Ich, Qch) = Tx (−Qch, Ich). This will be explained using the constellation of FIG. 3. Each coordinate on the transmission side is a coordinate rotated 90 degrees clockwise on the reception side. That is, the coordinate (0, 0) on the transmission side is (1, 0) on the reception side, the coordinate (1, 0) on the transmission side is (1, 1) on the reception side, and the coordinates (1, 1) on the transmission side. ) Is (0, 1) on the receiving side, and the coordinates (0, 1) on the transmitting side are (0, 0) on the receiving side.

  Therefore, when a 90 degree phase rotation occurs, the I channel signal S22I and the Q channel signal S22Q from the QPSK demodulator 22 are 111011000..., As shown in the first and fourth lines of FIG. 101110010... When differential decoding is repeated twice for such an I channel signal S22I, 100101110... Is obtained as shown in the third row of FIG. 6, and the obtained signal DOUT is transmitted by the transmission side. It is equal to the data signal DIN. That is, even if the phase rotation of 90 degrees occurs, a correct data signal can be obtained on the receiving side. Further, the clock signal CKOUT extracted from the Q channel signal S22Q (strobe signal) using the I channel signal S22I becomes 010101010... As shown in the fifth row of FIG. The alternating signal is inverted in phase and can be used as a clock signal.

  FIG. 7 is an explanatory diagram showing a timing chart of each part of the digital data receiving device 2 in the case where the phase rotation is 180 degrees, in a truth table description, and FIG. 8 is a case where the phase rotation is 270 degrees. It is explanatory drawing which showed the timing chart of each part of the digital data receiver 2 by truth table description.

  When phase rotation of 180 degrees occurs, there is a relationship of Rx (Ich, Qch) = Tx (-Ich, Qch) between the I channel signal and the Q channel signal on the transmission side and the reception side. Although detailed description is also avoided when the phase rotation of 180 degrees occurs, as shown in the third row of FIG. 7, the signal DOUT obtained by the two differential decoding operations is the data that the transmission side has attempted to transmit. It is equal to the signal DIN. Further, as shown in the fifth line of FIG. 7, the clock signal CKOUT becomes 01010101010, becomes an alternating signal obtained by inverting the phase of the clock signal CLK on the transmission side, and can be used as the clock signal.

  Further, when phase rotation of 270 degrees occurs, there is a relationship of Rx (Ich, Qch) = Tx (Qch, -Ich) between the I channel signal and the Q channel signal on the transmission side and the reception side. Although detailed description is also avoided when the phase rotation of 270 degrees occurs, as shown in the third row of FIG. 8, the signal DOUT obtained by the differential decoding twice is the data which the transmission side is going to transmit. It is equal to the signal DIN. Further, as shown in the fifth line of FIG. 8, the clock signal CKOUT becomes 010101010... Becomes an alternating signal obtained by inverting the phase of the clock signal CLK on the transmission side, and can be used as the clock signal.

  As described above, the extracted clock signal CKOUT repeats alternating between 1 and 0 regardless of whether the phase rotation is 0 degree, 90 degrees, 180 degrees, or 270 degrees. When a symbol series that does not repeat alternating 1 and 0 is generated as the clock signal CKOUT, the error detection circuit 28 detects this and a signal S28 indicating that the extracted data signal DOUT has an error. Is output.

(A-3) Effect of First Embodiment According to the first embodiment, there is phase rotation in the propagation path, and the I channel signal and Q channel signal from the QPSK demodulator are Even if the phase is rotated from the Q channel signal, a correct data signal can be extracted and a clock signal functioning as a clock signal can be extracted.

  Therefore, on the receiving side, it is possible to extract the clock signal from the received signal and determine the symbol value with a simple circuit without using the clock recovery circuit that recovers the clock signal even if the clock information is not transmitted. . In addition, a signal such as a preamble added to the head of transmission data or encoding for preventing the same signal from continuing is not required. In addition, since the clock information is sent in parallel with the data signal, the clock signal is not lost due to fading or the like. In addition, since the modulation is such that the symbol values of the I channel signal and the Q channel signal do not change at the same time, the bandwidth can be narrowed, and the expansion of the transmission bandwidth accompanying parallel transmission can be minimized.

  In addition, according to the first embodiment, the error detection circuit 28 has an error in the data signal DOUT based on whether or not the extracted clock signal CKOUT is one obtained by repeating alternating 1 and 0. Can be detected. That is, an error in the data signal DOUT can be easily detected.

(B) Second Embodiment Next, a second embodiment of the digital data transmitting apparatus, digital data receiving apparatus, and digital data transmission system according to the present invention will be described with reference to the drawings.

  In the digital data transmission system according to the second embodiment, the digital data transmission device 1A according to the second embodiment and the digital data reception device 2A according to the first embodiment face each other across the propagation path 3. Consists of.

  FIG. 9 is a block diagram showing the configuration of the digital data transmitting apparatus 1A according to the second embodiment. The same reference numerals are given to the same and corresponding parts as those in FIG. 1 according to the first embodiment. Yes. FIG. 10 is a block diagram showing the configuration of the digital data receiving apparatus 2A according to the second embodiment. The same reference numerals are given to the same and corresponding parts as those in FIG. 1 according to the first embodiment. Show.

  The clock signal CLK in the first embodiment described above has one cycle equal to two symbol periods in the data signal DIN, and the change (symbol change) of the clock signal CLK is the same time (time slot) as the change (symbol) of the data signal. ).

  However, in many data processing circuits, the clock signal is an alternating signal having a cycle of one symbol period (one time slot) of the data signal and rising (or falling) at the center of the symbol period.

  The second embodiment corresponds to the clock signal CLK2 of an alternating signal that rises (or falls) in the center of the symbol period with one symbol period of the data signal DIN as a cycle.

  The digital data transmitting apparatus 1A according to the second embodiment includes a 1/2 frequency dividing circuit 18 in addition to the configuration of the digital data transmitting apparatus 1 according to the first embodiment. The 1/2 frequency dividing circuit 18 receives the clock signal CLK2, and divides the clock signal CLK2 by 1/2. The frequency-divided signal (symbol CLK is used in FIG. 9) is the same signal as the clock signal in the first embodiment, and is input to the exclusive OR circuit 16. An existing configuration can be applied as the ½ divider circuit 18. For example, a ½ frequency divider consisting of a shift register and a decode circuit that decodes the outputs of a plurality of predetermined stages of the shift register to obtain a frequency-divided signal, a T-type flip-flop, or a D-type flip-flop is used. A 1/2 divider circuit can be applied.

  The digital data receiving apparatus 2A according to the second embodiment includes a frequency doubler circuit 29 in addition to the configuration of the digital data receiving apparatus 2 according to the first embodiment. A signal CKOUT output from the exclusive OR circuit 27 is input to the frequency doubler circuit 29. This signal CKOUT is the extracted clock signal in the first embodiment. The frequency doubler circuit 29 doubles the frequency of the signal CKOUT, and outputs the doubled signal CKOUT2 as an extracted clock signal. An existing configuration can be applied as the frequency doubler circuit 29. FIG. 10 shows an example of the frequency doubling circuit 29 that includes a 1/2 symbol period delay circuit 29A and an exclusive OR circuit 29B.

  According to the second embodiment, even if the clock signal is a clock signal of an alternating signal that rises (or falls) in the center of the symbol period with one symbol period of the data signal as a period, the first embodiment The same effect can be achieved.

(C) Other Embodiments In the above embodiments, the digital modulation scheme is the QPSK modulation scheme, but the digital modulation scheme is not limited to the QPSK modulation scheme. In short, a single digital modulation signal is obtained from an in-phase component signal (I channel signal) and a quadrature component signal (Q channel signal), and the digital modulation signal is obtained by a combination of the in-phase component signal and the quadrature component signal. The present invention can be applied to any digital modulation system that causes a phase change. For example, the digital modulation method may be a π / 4 shift QPSK modulation method.

In each of the above embodiments, two stages of differential encoding and differential decoding are performed so that the axes of the I channel and the Q channel are aligned. However, the number of stages of differential encoding and differential decoding is reduced. It may be other than two stages. Note that the error rate generally improves when the number of stages of differential encoding and differential decoding is small. On the decoding side, differential decoding can be omitted by analyzing the contents of the received signal, and the number of stages on the decoding side can be made smaller than the number of stages on the encoding side. .

  In each of the above embodiments, the output signal S13 of the exclusive OR circuit 13 is input to the I channel input terminal of the QPSK modulator 15, and the output signal STB of the exclusive OR circuit 16 is input to the Q channel input of the QPSK modulator 15. Although what is input to the terminal is shown, it may be input in reverse. That is, the output signal STB of the exclusive OR circuit 16 is input to the I channel input terminal of the QPSK modulator 15, and the output signal S13 of the exclusive OR circuit 13 is input to the Q channel input terminal of the QPSK modulator 15. You may do it.

  In the description of each of the above embodiments, it has been described that all elements are configured by hardware. However, a part of the configuration is realized by a software configuration including a CPU and a program executed by the CPU. Also good.

  In the second embodiment, a circuit having a 1/2 frequency divider or a frequency doubler is shown. However, depending on the frequency of the original clock signal (original clock signal), the frequency division ratio and the multiplication number are as described above. It is not limited to things. A frequency division ratio that is the same as that in the first embodiment may be applied to the frequency when the exclusive OR circuit 16 is input, and the multiplication number may be the reciprocal of the frequency division ratio.

1, 1A ... digital data transmission device,
11, 13, 16 ... 2-input exclusive OR circuit, 12, 14 ... 1 symbol period delay circuit, 15 ... QPSK modulator, 17 ... transmitter, 18 ... 1/2 divider circuit,
2, 2A ... Digital data receiver,
DESCRIPTION OF SYMBOLS 21 ... Reception part, 22 ... QPSK demodulator, 24, 26, 27 ... 2-input exclusive OR circuit, 23, 25 ... 1 symbol period delay circuit, 28 ... Transmission error detection circuit, 29 ... Frequency doubler circuit,
3 ... propagation path.

Claims (6)

A digital data transmitting apparatus that forms and transmits a digital modulation signal including information of a data signal and a clock signal having a cycle of two symbol periods of the data signal,
Differential encoding repetition means for performing differential encoding on the data signal a predetermined number of times;
The differential encoding repetition signal which is an output signal from the differential encoding repetition means and the clock signal are not changed when the symbol of the differential encoding repetition signal changes, and the differential encoding repetition signal Strobe signal forming means for forming a strobe signal that changes when the symbol does not change;
One of the differentially encoded repeated signal and the strobe signal is input to its own in-phase component input terminal, and the other is input to its own quadrature component input terminal, and the phase changes depending on the combination of the in-phase component signal and the quadrature component signal And a digital modulation means for forming a digital modulation signal for generating the digital data.   An original clock signal, which is an alternating signal that changes in the center of the symbol period, is input with a cycle of one symbol period of the data signal, and the original clock signal is divided by half to form the clock signal 1 The digital data transmitting apparatus according to claim 1, further comprising a / 2 frequency divider. A digital data receiving apparatus for receiving a digital modulation signal transmitted by the digital data transmitting apparatus according to claim 1 or 2,
Digital demodulation means for demodulating the received digital modulation signal and outputting an in-phase component signal and a quadrature component signal;
Of the in-phase component signal and the quadrature component signal, differential decoding is performed a predetermined number of times on the signal that is a differentially encoded repeated signal, and the data signal that the digital data transmitting device intends to transmit is extracted. Differential decoding repetition means;
A digital data receiving apparatus comprising: clock extracting means for extracting a clock signal to be transmitted by the digital data transmitting apparatus from a signal which is a strobe signal among the in-phase component signal and the quadrature component signal. .   It is monitored whether or not the clock signal extracted by the clock extracting means is an alternating signal for determining a logical value for each symbol period of the data signal. If the clock signal is not an alternating signal, an error is detected in the extracted data signal. 4. The digital data receiving apparatus according to claim 3, further comprising error detection means for determining that there is a data.   5. The frequency doubler according to claim 3, further comprising a frequency doubler that doubles the frequency of the clock signal extracted by the clock extraction unit and obtains an original clock signal to be transmitted by the digital data transmission device. Digital data receiver.   A digital data transmission system, wherein the digital data transmission device according to claim 1 and the digital data reception device according to any one of claims 3 to 5 are opposed to each other via a propagation path. .

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