JP2013171608A - Semiconductor device, method for testing semiconductor device, and test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which information on defective memory elements in a redundancy area can be used in later test processes, so as to prevent an increase in screening costs which is caused when a test for the redundancy area is required in the later test processes because information indicating that there is a defective redundant memory element cannot be stored when the defective redundant memory element is found to exist in the redundancy area.SOLUTION: A semiconductor device comprises: memory elements that store data; a defective memory element that is one of the memory elements and determined to be defective; a redundant memory element with which replacement can be done; and a first nonvolatile storage element that stores, when the redundant memory element is determined to be defective, information on the address of the defective redundant memory element.

Description

  The present invention relates to a semiconductor device, a test method for a semiconductor device, and a test circuit. In particular, the present invention relates to a semiconductor device including a redundant memory element capable of replacing a defective memory element, a test method for a semiconductor device, and a test circuit.

  The integration of semiconductor devices is progressing year by year. For example, in the case of a semiconductor device such as a DRAM (Dynamic Random Access Memory), an increase in memory elements is remarkable. Therefore, the probability that a defect of the memory element occurs in the manufacturing process is increased, and the yield is deteriorated when such a semiconductor device is handled as a defective product.

  Therefore, as a method for relieving a defective memory element (bit) determined to have a defect, the defective memory element is replaced with another memory element (redundant memory element). A fuse is used to replace the defective memory element and the redundant memory element. In order to replace the defective memory element and the redundant memory element, a fuse is cut by a laser in a wafer process or the like. Whether or not the redundant memory element is to be used is determined based on the state of the fuse (connection / disconnection).

  However, such a method of connecting a fuse by laser cutting must be performed before sealing in a package, and cannot be replaced with a redundant memory element after sealing in a package. Therefore, replacement with a redundant memory element is performed by using an antifuse that can be programmed (change in state) by applying a predetermined voltage. Further, even when an antifuse is used, there are a method of replacing a defective memory element with a latch circuit and a method of using a redundancy area. However, using a redundancy area is more advantageous than using a latch circuit from the viewpoint of the chip area of a semiconductor device because the required layout area is small.

  Here, Patent Document 1 discloses a semiconductor device capable of performing a roll call test for determining whether or not redundancy is used.

JP 7-65595 A

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  The semiconductor device test process (screening process) is composed of a plurality of processes. That is, only a semiconductor device determined to be a non-defective product in a certain test process is transferred to the next test process, and only a semiconductor device finally determined to be a non-defective product in all test processes can be shipped.

  Therefore, when a defective memory element is detected in a certain test process and replaced with a redundant memory element, it is necessary to perform the test process again to guarantee the quality of the cell including the redundant memory element. In addition, if the test including the redundant memory element is not performed in the test process before the test process, it is necessary to test the previous test process again. Such sorting increases the cost required for sorting semiconductor devices.

  Therefore, it is desired to test the normal area including the normal memory element and the redundancy area including the redundant memory element from the initial test process to guarantee the quality. However, since the information that the defective memory element exists in the redundancy area is not carried over to the later test process, the redundancy area is tested again in the later test process. That is, a defective memory device that is apparently unusable will be tested again, wasting time and cost in the testing process. Therefore, a semiconductor device, a semiconductor device test method, and a test circuit that can use information of a defective memory element in a redundancy area in a later test process is desired.

  According to a first aspect of the present invention, a memory element that stores data, a defective memory element that is determined to have a defect, the redundant memory element that can be replaced, and the redundant memory element When it is determined that a defect exists, a semiconductor device is provided that includes a first nonvolatile memory element that stores information related to the address of the redundant memory element in which the defect exists.

  According to a second aspect of the present invention, a memory element that stores data, a defective memory element that is determined to be defective in the memory element, a redundant memory element that can be replaced, and a redundant memory element A semiconductor device test method comprising: a first nonvolatile memory element that stores information related to an address of a redundant memory element in which a defect exists when it is determined that a defect exists; Performing a first test on the redundant memory element; changing a state of the first nonvolatile memory element when the redundant memory element is defective in the first test; and And a step of determining whether or not to perform a second test on the redundant memory element according to a state of the one nonvolatile memory element.

  According to a third aspect of the present invention, there is provided a semiconductor device comprising: a memory element that stores data; a defective memory element that is a memory element that has been determined to have a defect; and a redundant memory element that can be replaced. A test circuit to be tested, the test circuit being provided with a test circuit that passes a result when testing a plurality of the semiconductor devices at the same time regardless of a test result related to the redundant memory element included in the semiconductor device. Is done.

  According to each aspect of the present invention, a semiconductor device, a semiconductor device test method, and a test circuit that can use information of a defective memory element in a redundancy area in a later test process are provided.

It is a figure for demonstrating the outline | summary of one Embodiment of this invention. 1 is a diagram illustrating an example of an overall configuration of a semiconductor device 1 according to a first embodiment. It is a figure for demonstrating replacement of a memory element. It is a figure which shows an example of a structure at the time of implementing a parallel test. It is a figure which shows an example of the internal structure of the test circuit 2 which concerns on 2nd Embodiment. 6 is a diagram illustrating an example of a waveform during a parallel test using a test circuit 2. FIG.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, when a normal area including a normal memory element and a redundancy area including a redundant memory element are tested together, it may be found that the redundant memory element included in the redundancy area has a defect. In such a case, information indicating that a defect exists in the redundant memory element cannot be stored, and a redundancy area test is required in a later test process. However, such testing is a waste of test time and cost. Therefore, a semiconductor device that can use the information of the defective memory element in the redundancy area in a later test process is desired.

  Therefore, as an example, the semiconductor device 100 illustrated in FIG. 1 is provided. The semiconductor device 100 includes a memory element 101 that stores data, a defective memory element 102 that is a memory element that has been determined to have a defect, a redundant memory element 103 that can be replaced, and a defect in the redundant memory element 103. A first nonvolatile memory element 104 that stores information relating to the address of the redundant memory element in which the defect exists when it is determined.

  When it is found that the redundant memory element 103 has a defect, the state of the first nonvolatile memory element 104 is changed, and information indicating that the use of the defective redundant memory element is prohibited is stored. To do. As a result, it is possible to provide a semiconductor device that can use information on a defective memory element (redundant memory element 103) in the redundancy area in a later test process.

  In the present invention, the following modes are possible.

  [Mode 1] As in the semiconductor device according to the first aspect.

  [Mode 2] The semiconductor device includes a second nonvolatile memory element that stores information related to an address of the defective memory element, information that is stored in the first nonvolatile memory element, and the second nonvolatile memory. It is preferable to include a redundancy control circuit that replaces the defective memory element and the redundant memory element based on information stored in the element.

  [Mode 3] It is preferable that the redundancy control circuit changes the state of the second nonvolatile memory element or the first nonvolatile memory element in accordance with an externally input command.

  [Mode 4] It is preferable that at least one of the first nonvolatile memory element or the second nonvolatile memory element is an antifuse.

  [Mode 5] The test method of the semiconductor device according to the second aspect.

  [Mode 6] The semiconductor device includes a second nonvolatile memory element that stores information related to an address of the defective memory element, and when the presence of the defective memory element is found in the first test, It is preferable to include a step of changing the state of the second nonvolatile memory element.

  [Mode 7] A test circuit according to the third aspect.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
The first embodiment of the present invention will be described in more detail with reference to the drawings.

  FIG. 2 is a diagram illustrating an example of the overall configuration of the semiconductor device 1 according to the present embodiment. For simplicity, FIG. 2 shows only modules related to the semiconductor device according to the present embodiment.

  The semiconductor device 1 includes command terminals (/ RAS, / CAS, / WE), an address terminal ADD, and the like. The semiconductor device 1 includes a command input circuit 10, a command decode circuit 11, an address input circuit 12, an address latch circuit 13, a memory cell array 14, a column decoder 15, a row decoder 16, a redundancy control circuit 17, It is composed of

  A command for the semiconductor device 1 is received by the command input circuit 10 via a command terminal. Specifically, a command composed of a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and the like is input. A command constituted by these signals is decoded by the command decoding circuit 11, and the decoding result is output to the column decoder 15, the row decoder 16 and the redundancy control circuit 17. Further, the command input circuit 10 accepts not only commands related to the normal operation of the semiconductor device 1 but also commands related to the test operation of the semiconductor device 1.

  An address signal issued from the outside is received by the address input circuit 12 and latched by the address latch circuit 13. The address signal is supplied to the column decoder 15, the row decoder 16 and the redundancy control circuit 17.

  The memory cell array 14 includes a plurality of memory elements that hold data. The memory cell array 14 is divided into a normal area 20 and a redundancy area 21. Normally, a memory element arranged in the normal area 20 is used, and a memory element arranged in the redundancy area 21 is prepared as a redundant memory element.

  The column decoder 15 and the row decoder 16 decode the address signal and control access to the memory cell array 14.

  The redundancy control circuit 17 replaces addresses of the memory elements included in the normal area 20 and the memory elements included in the redundancy area 21. In consideration of the repair efficiency, the redundancy area 21 is not a column area but a row area.

  FIG. 3 is a diagram for explaining replacement of a memory element. As shown in FIG. 3, it is assumed that a defective memory element (“x” in FIG. 3) exists in the normal area 20. In this case, it is necessary to replace the entire row including the defective memory element with the row included in the redundancy area 21. The redundancy control circuit 17 generates an address for replacing a defective memory element with a redundant memory element.

  The redundancy control circuit 17 includes a replacement antifuse (corresponding to the second nonvolatile memory element described above) that stores a row address corresponding to a defective memory element included in the normal area 20. That is, the redundancy control circuit 17 includes a plurality of replacement antifuses, and the row address of the defective memory element to be converted into a redundant memory element can be grasped by the state (conductive / nonconductive) of the replacement antifuse. It is.

  Further, the redundancy control circuit 17 includes a use prohibition antifuse (corresponding to the first nonvolatile memory element described above) that stores a row address corresponding to a defective memory element included in the redundancy area 21. In other words, the redundancy control circuit 17 includes a plurality of use-prohibited antifuses, and a defective memory that cannot be used to replace a defective memory element included in the normal area 20 depending on the state (conduction / non-conduction) of the use-prohibited antifuse. The row address of the element can be grasped.

  As described above, the redundancy control circuit 17 includes two types of antifuses. The redundancy control circuit 17 uses these antifuses to replace a defective memory element existing in the normal area 20 with a redundant memory element in the redundancy area 21. More specifically, the redundancy control circuit 17 receives the row address output from the address latch circuit 13 and determines whether or not it is necessary to replace the received row address. In this case, a replacement antifuse is used. As a result of the determination, if it is necessary to replace the row address of the redundant memory element included in the redundancy area 21, the row address of the redundant memory element to be replaced is determined. At that time, the state of the prohibited anti-fuse is confirmed, and an address that cannot be used as a redundant memory element is not adopted as a replacement row address. That is, the redundancy control circuit 17 selects only the row address whose replacement is not prohibited by the use prohibition antifuse, and outputs it to the row decoder 16.

  The row decoder 16 accesses a redundant memory element included in the redundancy area 21 based on the row address output from the redundancy control circuit 17. The replacement of the defective memory element and the redundant memory element is called AF (Anti Fuse) replacement, and the following description will be given.

  In each test process, when a defect is found in the memory element included in the normal area 20, the insulating film of the replacement antifuse corresponding to the row address of the defective memory element is dissolved. Similarly, when a defect is found in the memory element included in the redundancy area 21 in each test process, the insulating film of the prohibited antifuse corresponding to the row address of the defective memory element is dissolved. The replacement anti-fuse and the use-prohibited anti-fuse included in the redundancy control circuit 17 are melted based on an instruction from the command decode circuit 11 that has received a command signal issued from the outside.

  Next, a test process performed on the semiconductor device 1 will be described. Here, a case where AF replacement is performed for the row address in the test process will be described.

  When the memory cell array 14 (normal area 20 and redundancy area 21) of the semiconductor device 1 is tested, four types of results can be assumed.

  First, the memory elements included in the normal area 20 and the redundancy area 21 are both non-defective.

  Secondly, the memory element included in the normal area 20 is a good product, but the memory element included in the redundancy area 21 is defective.

  Third, the memory element included in the normal area 20 has a defect, but the memory element included in the redundancy area 21 is a non-defective product.

  Fourth, the memory elements included in the normal area 20 and the redundancy area 21 are both defective.

  In the case of the first result, the result in the test process is passed (PASS). On the other hand, in the case of the fourth result, the result in the test process is rejected (FAIL). In the case of the second result, since at least the memory elements included in the normal area 20 are non-defective, the result in the test process is acceptable. However, since the memory element included in the redundancy area 21 cannot be used, the corresponding use-prohibited antifuse insulating film is dissolved. Then, it progresses to the next test process.

  Furthermore, in the case of the third result, the test process cannot be passed as it is. Therefore, the defective memory element and the redundant memory element are replaced (AF replacement is performed). After the AF replacement, the test process is performed again, and if it passes, the process proceeds to the next test process. Even if AF replacement is performed, if the test fails, the failure in the test process is determined.

  Next, a test process for the semiconductor device 1 in which the insulating film of the prohibited antifuse is dissolved or the semiconductor device 1 in which the insulating film of the replacement antifuse is dissolved will be described.

  Here, the test is performed on both the semiconductor device 1 in which the insulating film of the prohibited antifuse is dissolved and the semiconductor device 1 in which the insulating film of the replacement antifuse is dissolved in the same manner as the normal semiconductor device 1. At that time, if there is a possibility of performing AF replacement in the test process after the test process, not only the normal area 20 but also the redundancy area 21 is tested. Further, if there is a defect in the memory element included in the normal area 20, the corresponding replacement antifuse insulating film is dissolved. Similarly, if there is a defect in the memory element included in the redundancy area 21, the corresponding use-prohibited antifuse insulating film is dissolved.

  As described above, the redundancy area 21 is tested by testing the semiconductor device 1 in which the insulating film of the prohibited antifuse is dissolved and the semiconductor device 1 in which the insulating film of the replacement antifuse is dissolved. It is possible to guarantee not only the test of the test process but also the quality of the test items of the test process performed before that. In other words, the quality of the memory elements included in the normal area 20 and the redundancy area 21 in the semiconductor device 1 that has advanced to a specific test process before the test process is that the insulating film of the replacement anti-fuse and the use-prohibited anti-fuse is dissolved. If not, it is guaranteed. As a result, even if the defective memory element in the normal area 20 is replaced with a redundant memory element in the test process, it is not necessary to perform the previous test process again. Therefore, the selection cost of the semiconductor device 1 can be suppressed.

  Further, it is obvious that the memory element included in the redundancy area 21 corresponding to the row address in which the insulating film of the prohibited antifuse is dissolved cannot be used. Therefore, when such a semiconductor device 1 is tested, it is confirmed whether or not the insulating film of the prohibited antifuse is dissolved (conducting / non-conducting of the prohibited antifuse). There is no need to test the redundancy area 21 to be performed. Also from this point, the selection cost of the semiconductor device 1 can be suppressed.

  In the present embodiment, the first and second nonvolatile memory elements described above are both assumed to be antifuses. However, it is not intended to limit these nonvolatile memory elements to antifuses. These nonvolatile memory elements may be fuses or combinations of fuses and antifuses.

  As described above, the quality of the memory elements included in the normal area 20 and the redundancy area 21 can be guaranteed by testing the normal area 20 and the redundancy area 21 in the same test process. In addition, the use of a prohibited antifuse can shorten the test process time and contributes to a reduction in sorting costs.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings.

  As described in the first embodiment, by using the use-prohibited antifuse, it is possible to select a redundancy area as a replacement destination. Therefore, the meaning of the test result of the redundancy area in each test process varies depending on whether the insulating film of the prohibited antifuse is dissolved.

  As described above, not only the normal area 20 but also the redundancy area 21 is tested in the same test process. Here, a test process of the semiconductor device 1 subjected to AF replacement will be considered. A defective memory element exists in the normal area 20 of the semiconductor device 1 subjected to the AF replacement (see FIG. 3). In such a normal area 20 of the semiconductor device 1, when “0” data is read and then a test for writing “1” data is performed, “1” is written to the memory elements included in the redundancy area 21. Then, if the same test is performed on the redundancy area 21 after the test on the normal area 20 is completed, “0” cannot be read. Therefore, such a test for the redundancy area 21 is rejected.

  In order to avoid such a problem, it can be considered that the normal area 20 and the redundancy area 21 are separately tested independently. However, when testing the redundancy area 21 alone, the state of the cells and bit lines adjacent to the redundant memory element is different from the original use state, so that the quality of the normal area 20 and the redundancy area 21 are equivalent. It is difficult to keep on. Furthermore, when there are test items for performing rewrite operation (Disturb) repeatedly, it is necessary to perform the rewrite operation many times in the redundancy area 21 alone, which leads to a long time for the test process. Thus, there is a problem in performing the test in which the normal area 20 and the redundancy area 21 are separated. In view of the above, it is desirable to test the normal area 20 and the redundancy area 21 simultaneously from the viewpoint of the quality of the redundancy area 21 and the reduction of the test time.

  Therefore, in the test process (for example, parallel test) in which the normal area 20 and the redundancy area 21 are simultaneously tested with respect to the memory element subjected to AF replacement, the test result of the memory element included in the redundancy area 21 is forcibly passed. There is a need.

  That is, when testing the redundancy area 21, the test result of the redundant memory element is forcibly passed, and the quality of the redundant memory element forcibly passed is ensured by the test on the normal area 20 side. More specific measures are taken by changing the configuration of the test circuit used in the parallel test.

  FIG. 4 is a diagram illustrating an example of a configuration when the parallel test is performed. As shown in FIG. 4, in the parallel test, a plurality of semiconductor devices 1 are tested simultaneously. The test circuit 2 accepts data RD1 to RDn (where n is an integer of 2 or more, and the same applies hereinafter) read from the semiconductor device 1.

  The test circuit 2 also sets the AF_E signal that is set to H level when testing the semiconductor device 1 that may have undergone AF replacement, and TRAXT that is set to H level when the redundancy area 21 is selected. And a signal. The test circuit 2 determines the result of the parallel test using the data RD1 to RDn output from the plurality of semiconductor devices 1, the AF_E signal, and the TRAXT signal. The test circuit 2 outputs a PARA_R signal as a determination result.

  FIG. 5 is a diagram illustrating an example of the internal configuration of the test circuit 2. The test circuit 2 includes a comparison circuit 30, NAND circuits NAND01 and NAND02, and an inverter circuit INV01. Further, the comparison circuit 30 is composed of OR circuits OR01 and OR02 and a NOR circuit NOR01. Note that the test circuit 2 shown in FIG. 5 enables four semiconductor devices 1 to be tested simultaneously (n = 4).

  FIG. 6 is a diagram illustrating an example of a waveform at the time of a parallel test using the test circuit 2. Between time t01 and t03 is a test for the normal area 20, and between time t03 and t04 is a test for the redundancy area 21.

  As shown in FIG. 6, when the normal area 20 is tested, the TRAXT signal is not set to the H level (maintains the L level). Therefore, if there is a mismatch in the data RD1 to RD4, the PARA_R signal becomes the L level. More specifically, in the test between times t02 and t03 in FIG. 6, since the data RD3 is unacceptable data, the result of the parallel test also fails (PARA_R signal is at L level). However, when testing the redundancy area 21, the TRAXT signal is set to the H level, so that the PARA_R signal becomes the H level even if there is a mismatch in the data RD1 to RD4. That is, the data RD4 between times t03 and t04 in FIG. 6 is data that is determined to be unacceptable, but the PARA_R signal is at the H level, and the entire parallel test is determined to be acceptable.

  As described above, the test of the normal area 20 and the redundancy area 21 can be performed simultaneously by using the test circuit 2.

  The disclosure of the cited patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the claims of the present invention, Selection is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1,100 Semiconductor device 2 Test circuit 10 Command input circuit 11 Command decode circuit 12 Address input circuit 13 Address latch circuit 14 Memory cell array 15 Column decoder 16 Row decoder 17 Redundancy control circuit 20 Normal area 21 Redundancy area 30 Comparison circuit 101 Memory element 102 Defective memory element 103 Redundant memory element 104 First nonvolatile memory element INV01 Inverter circuit NAND01, NAND02 NAND circuit NOR01 NAND circuit OR01, OR02 OR circuit

Claims (7)

A memory element for storing data;
A defective memory element that is determined to be defective and is a redundant memory element that can be replaced;
A first non-volatile storage element that stores information regarding the address of the redundant memory element in which the defect is present when it is determined that the redundant memory element has a defect;
A semiconductor device comprising: A second non-volatile storage element that stores information regarding the address of the defective memory element;
A redundancy control circuit that replaces the defective memory element and the redundant memory element based on information stored in the first nonvolatile memory element and information stored in the second nonvolatile memory element;
A semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein the redundancy control circuit changes a state of the second nonvolatile memory element or the first nonvolatile memory element in accordance with an externally input command.   4. The semiconductor device according to claim 2, wherein at least one of the first nonvolatile memory element or the second nonvolatile memory element is an antifuse. A memory element for storing data;
A defective memory element that is determined to be defective and is a redundant memory element that can be replaced;
A first non-volatile storage element that stores information regarding the address of the redundant memory element in which the defect is present when it is determined that the redundant memory element has a defect;
A method for testing a semiconductor device comprising:
Performing a first test on the memory element and the redundant memory element;
Changing a state of the first nonvolatile memory element when the redundant memory element has a defect in the first test; and
Determining whether to perform a second test on the redundant memory element according to a state of the first nonvolatile memory element;
A method for testing a semiconductor device, comprising: The semiconductor device includes a second nonvolatile memory element that stores information related to an address of the defective memory element,
6. The method of testing a semiconductor device according to claim 5, further comprising a step of changing a state of the second nonvolatile memory element when the presence of the defective memory element is found in the first test. A memory element for storing data;
A defective memory element that is determined to be defective and is a redundant memory element that can be replaced;
A test circuit for testing a semiconductor device comprising:
The test circuit is characterized in that, regardless of a test result related to the redundant memory element included in the semiconductor device, a result when the plurality of semiconductor devices are tested simultaneously is passed.

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