JP2013168660A - Semiconductor integrated circuit device and layout method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that has at least two image data interfaces and is provided with an effective arrangement of the image data interfaces and memory interfaces from the point of view of reliability.SOLUTION: A first image data interface 110 is arranged in an electrode region 210 and an I/O buffer region 220 provided along a first side 230 of a semiconductor chip 200. A second image data interface 130 is arranged in the electrode region 210 and the I/O buffer region 220 provided along a second side 240. A first memory interface 160 is arranged in the electrode region 210 and the I/O buffer region 220 provided along a third side 250. A second memory interface 170 is arranged in the electrode region 210 and the I/O buffer region 220 provided along a fourth side 260.

Description

  The present invention relates to a semiconductor integrated circuit device, a data recording device, and a layout method for a semiconductor integrated circuit device.

  The image data during driving of the car is recorded in the primary storage device at regular time intervals, and when an event such as an accident occurs, the image data for a certain time before and after the event is transferred from the primary storage device such as SDRAM to the CF memory. Drive recorders that transfer and record to secondary storage devices such as cards are used. Conventionally, in order to record the state of an accident, image data has been captured by a single camera facing the front of a running car. On the other hand, for the purpose of improving the driver's awareness of accident prevention by taking a picture of the driver while driving, it is equipped with two cameras and records not only the front image but also the image in the car at the same time Drive recorders have come into use. When two cameras are installed, it is important to ensure the reliability of the image data taken by both cameras and to record the image data taken at the same time in association with each other. In addition, if the image data captured by both cameras interfere with each other and the image data is destroyed, the recorded image cannot be used as evidence.

JP 2005-259041 A

  Therefore, in a data recording apparatus such as a drive recorder in which evidence capability is regarded as important, not only the reliability of image data is systematically guaranteed but also the layout of a semiconductor integrated circuit device used in the data recording apparatus. You must also give due consideration.

  The present invention has been made in view of the above problems, and has at least two image data interfaces, and performs effective arrangement of the image data interface and the memory interface from the viewpoint of image data reliability. Another object is to provide a semiconductor integrated circuit device.

(1) The present invention
An electrode region having a square or rectangular shape and for arranging a plurality of electrode portions in the peripheral portion along each side, and an input / output buffer region for arranging a plurality of input / output buffers along the electrode region A semiconductor integrated circuit device including a semiconductor chip having:
A first image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
A second image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
The plurality of electrode units and the plurality of input / output buffers of the first image data interface unit are
Disposed in at least a part of the electrode region and the input / output buffer region provided along the first side of the semiconductor chip;
The plurality of electrode units and the plurality of input / output buffers of the second image data interface unit are
The semiconductor chip is arranged in at least a part of an electrode region and an input / output buffer region provided along a second side facing the first side of the semiconductor chip.

  The image data may be, for example, image data taken by a camera module or the like, or image data obtained by subjecting the image data to conversion processing such as JPEG encoding or IP conversion (interlace / progressive conversion). Also good.

  The semiconductor integrated circuit device including the semiconductor chip may be, for example, the semiconductor chip itself, a semiconductor device in which the semiconductor chip is packaged, or a semiconductor device on which the semiconductor chip according to the present invention and another semiconductor chip are mounted. It may be.

  According to the present invention, it goes without saying that the signal lines are connected by hand wiring by arranging the first image data interface unit and the second image data interface unit in the peripheral part along opposite sides. Even if the automatic wiring tool is used for wiring, the wiring region for wiring connected to the first image data interface unit and the wiring region for wiring connected to the second image data interface unit Overlapping parts can be reduced. As a result, the wiring efficiency is increased and the wiring area can be reduced, so that the area cost of the semiconductor chip can be reduced. Further, by reducing the overlapping portion of the wiring area, interference between the two image data supplied from the first image data interface unit and the second image data interface unit to the inside of the semiconductor chip and the image data can be reduced. Superposition of noise can be effectively prevented, and an increase in signal propagation delay due to the parasitic capacitance of the wiring can be suppressed, so that high-speed operation can be realized.

  Further, when the semiconductor integrated circuit device according to the present invention is used for a data recording device and the front and rear images are taken, it is connected to the first image data interface unit on the substrate of the data recording device. If the semiconductor integrated circuit device according to the present invention is arranged between the first external device (camera module or the like) and the second external device (camera module or the like) connected to the second image data interface unit, each external device It is not necessary to cross the wiring formed between the device and the semiconductor integrated circuit device according to the present invention on the substrate. Therefore, the design of the substrate becomes easy, the number of layers of the substrate can be reduced, and the effect of cost reduction can be obtained.

(2) A semiconductor integrated circuit device according to the present invention includes:
The plurality of electrode units and the plurality of input / output buffers of the second image data interface unit are
The plurality of electrode units and the plurality of input / output buffers of the first image data interface unit are arranged to face each other.

  According to the present invention, since the length of the wiring connected to the first image data interface unit and the length of the wiring connected to the second image data interface unit can be made substantially equal, the parasitic capacitance of these wirings can be reduced. The accompanying signal propagation delay can be made approximately equal. As a result, even when the image data supplied from the first image data interface unit and the image data supplied from the second image data interface unit are processed asynchronously, they are processed synchronously inside the semiconductor chip. Even in such a case, the conversion process can be performed without mistaken correspondence between the image data of the two and recorded in the primary storage device.

(3) A semiconductor integrated circuit device according to the present invention includes:
A plurality of electrode units and a plurality of input / output buffers are provided, and the first image data interface unit and the second image data interface unit perform conversion processing on the image data supplied to the semiconductor chip or the image data. A first memory interface unit for recording a recorded image data in a primary storage device external to the semiconductor chip and providing a primary storage interface for reading the recorded image data from the primary storage device;
At least some of the plurality of electrode portions and at least some of the plurality of input / output buffers of the first memory interface portion are:
It is arranged in an electrode region and an input / output buffer region provided along the third side of the semiconductor chip.

  The plurality of electrode units and the plurality of input / output buffers of the first memory interface unit are provided along the third side and the electrode region and the input / output buffer region provided along the first side. It may be arranged in the electrode region and the input / output buffer region.

  The plurality of electrode units and the plurality of input / output buffers of the first memory interface unit are provided along the third side and the electrode region and the input / output buffer region provided along the second side. It may be arranged in the electrode area and the input / output buffer area.

  The plurality of electrode units and the plurality of input / output buffers of the first memory interface unit are provided along the electrode region and the input / output buffer region provided along the first side and the second side. The electrode region and the input / output buffer region may be disposed in the electrode region and the input / output buffer region provided along the third side.

  According to the present invention, since the first memory interface unit is arranged along a side different from the side where the first image data interface unit and the second image data interface unit are arranged, the first image data interface unit In addition, the wiring of the data line from the second image data interface unit to the first memory interface unit does not need to pass near the center where there is a high possibility of being crowded with other modules and wirings, so that the wiring efficiency is increased. As well as reducing the possibility of noise being superimposed on the image data.

  In addition, on a substrate of a data recording apparatus using the semiconductor integrated circuit device according to the present invention, a first external device (camera module or the like) connected to the first image data interface unit, a second image data interface unit If the second external device (camera module, etc.) and the primary storage device (SDRAM, etc.) connected to the semiconductor chip are respectively arranged to face the first side, the second side, and the third side of the semiconductor chip, It is not necessary to cross the wiring formed between the first external device, the second external device, the primary storage device, and the semiconductor integrated circuit device according to the present invention on the substrate. Therefore, the design of the substrate becomes easy, the number of layers of the substrate can be reduced, and the effect of cost reduction can be obtained.

(4) A semiconductor integrated circuit device according to the present invention includes:
The plurality of electrode units and the plurality of input / output buffers of the first image data interface unit are arranged in the electrode region and the input / output buffer region near the first side and the third side of the semiconductor chip. And
The plurality of electrode units and the plurality of input / output buffers of the second image data interface unit are arranged in the electrode region and the input / output buffer region near the intersection of the second side and the third side of the semiconductor chip. It is characterized by being.

  The fact that the first side and the third side of the semiconductor chip are arranged close to each other means that when the side facing the third side of the semiconductor chip is the fourth side, at least the first side What is necessary is just to be arrange | positioned near the vicinity which a 1st edge | side and a 3rd edge | intersection cross rather than the vicinity where an edge | side and a 4th edge | side cross | intersect. For example, in the plurality of electrode units and the plurality of input / output buffers of the first image data interface unit, the distance from the center point of the majority of the electrode units to the vertex at which the first side and the third side intersect is the first. You may make it arrange | position in an electrode area | region and an input / output buffer area | region so that it may become shorter than the distance to the vertex which an edge | side and a 4th edge | intersection cross. Preferably, the plurality of electrode units and the plurality of input / output buffers of the first image data interface unit have a predetermined range of electrode regions and input / outputs close to a vertex at which the first side and the third side of the semiconductor chip intersect. It is good to arrange in the buffer area. For example, the plurality of electrode portions are electrode regions that are as close as possible to the vertexes except for an electrode region in the vicinity of the vertex where the first side and the third side cannot be arranged due to difficulty in bonding. It is preferable to arrange them in order. Further, the plurality of input / output buffers are as close as possible to the vertexes except for an input / output buffer region near the vertex where the first side and the third side cannot be arranged for layout reasons. It is preferable to arrange them in order in the input / output buffer region so as to correspond to the electrode portions.

  Similarly, when the second side and the third side of the semiconductor chip are arranged close to each other, when the side facing the third side of the semiconductor chip is the fourth side, at least, It suffices if the second side and the third side are arranged closer to the vicinity where the second side and the fourth side intersect than the vicinity where the second side and the fourth side intersect. For example, in the plurality of electrode units and the plurality of input / output buffers of the second image data interface unit, the distance from the center point of the majority of the electrode units to the vertex at which the second side and the third side intersect is the second. You may make it arrange | position in an electrode area | region and an input / output buffer area | region so that it may become shorter than the distance to the vertex which an edge | side and a 4th edge | intersection cross. Preferably, the plurality of electrode units and the plurality of input / output buffers of the second image data interface unit have a predetermined range of electrode regions and input / outputs close to a vertex at which the second side and the third side of the semiconductor chip intersect. It is good to arrange in the buffer area. For example, the plurality of electrode portions are electrode regions that are as close as possible to the vertexes except for an electrode region near the vertex where the second side and the third side cannot be arranged due to difficulty in bonding. It is preferable to arrange them in order. Further, the plurality of input / output buffers are as close as possible to the vertexes except for an input / output buffer region in the vicinity of the vertex where the second side and the third side intersect where the input / output buffer cannot be arranged due to layout. It is preferable to arrange them in order in the input / output buffer region so as to correspond to the electrode portions.

  According to the present invention, the distance between the first image data interface unit and the second image data interface unit and the first memory interface unit can be shortened. Therefore, the image data supplied from the first external device (camera module or the like) and the second external device (camera module or the like) via the first image data interface unit and the second image data interface unit, respectively, Assuming that recording is performed in the primary storage device via the first memory interface unit, the length of the wiring connected to the first image data interface unit and the second image data interface unit can be shortened. Therefore, the wiring efficiency can be increased. Further, since the recording operation to the primary storage device can be speeded up by reducing the length of the wiring, the number of image data that can be stored per unit time can be increased. If the semiconductor integrated circuit device according to the above is used, a data recording device with high reliability and high evidence capability can be provided.

(5) A semiconductor integrated circuit device according to the present invention includes:
In the input / output buffer region near the first side and the third side of the semiconductor chip, the power supply line of the first image data interface unit and the power supply line of the first memory interface unit are separated. And
In the input / output buffer region near the second side and the third side of the semiconductor chip, the power supply line of the second image data interface unit and the power supply line of the first memory interface unit are separated. It is characterized by being.

  According to the present invention, even when the operating voltage of the first image data interface unit and the second image data interface unit is different from the operating voltage of the first memory interface unit, the vicinity of the corner that cannot be used effectively. Power supply isolation can be realized using the input / output buffer area.

(6) A semiconductor integrated circuit device according to the present invention includes:
In any of claims 3 to 5,
The first memory interface unit includes:
Secondary storage for recording the primary storage interface and image data recorded in the primary storage device or image data obtained by converting the image data in a secondary storage device outside the semiconductor chip It includes at least one electrode unit for outputting a selection signal for selecting and providing one of the interfaces for use to the outside of the semiconductor chip.

  According to the present invention, a data line from the first memory interface unit to the second memory interface unit is not necessary, and the wiring area can be reduced, so that the wiring efficiency can be increased.

(7) A semiconductor integrated circuit device according to the present invention includes:
Image data recorded in the primary storage device or image data obtained by converting the image data is recorded in a secondary storage device outside the semiconductor chip, including a plurality of electrode units and a plurality of input / output buffers. A second memory interface unit providing a secondary storage interface for
At least part of the electrode part of the second memory interface part and at least part of the plurality of input / output buffers are
The semiconductor chip is disposed in an electrode region and an input / output buffer region provided along a fourth side facing the third side of the semiconductor chip.

  The plurality of electrode units and the plurality of input / output buffers of the second memory interface unit are provided along the electrode side and the input / output buffer region provided along the first side and the fourth side. It may be arranged in the electrode region and the input / output buffer region.

  The plurality of electrode units and the plurality of input / output buffers of the second memory interface unit are provided along the electrode side and the input / output buffer region provided along the second side and the fourth side. It may be arranged in the electrode area and the input / output buffer area.

  The plurality of electrode units and the plurality of input / output buffers of the second memory interface unit are provided along the second side and the electrode region and the input / output buffer region provided along the first side. The electrode region and the input / output buffer region may be disposed in the electrode region and the input / output buffer region provided along the fourth side.

  According to the present invention, the wiring area for the data line from the first image data interface unit and the second image data interface unit to the first memory interface unit, and the second memory from the first memory interface unit It is possible to effectively reduce the overlapping portion of the wiring area for the data line toward the interface unit.

  When the integrated circuit device according to the present invention is used for a data recording device, generally, the recording operation for the primary storage device (SDRAM or the like) is performed for the secondary storage device (CF memory card, SD memory card or the like). Although it is necessary to perform overwhelmingly high speed as compared with the operation, the first memory interface is arranged by arranging the first image data interface unit and the second image data interface unit near the first memory interface unit. The operation of recording the image data in the primary storage device via the unit can be speeded up.

  Furthermore, on the substrate of the data recording apparatus using the semiconductor integrated circuit device according to the present invention, a first external device (such as a camera module) connected to the first image data interface unit, a second image data interface unit The second external device (camera module, etc.) connected to the primary storage device and the secondary storage device are respectively opposed to the first side, the second side, the third side, and the fourth side of the semiconductor chip. If arranged in this manner, the wiring formed between the first external device, the second external device, the primary storage device, the secondary storage device and the semiconductor integrated circuit device according to the present invention must be crossed on the substrate. Absent. Therefore, the design of the substrate becomes easy, the number of layers of the substrate can be reduced, and the effect of cost reduction can be obtained.

(8) A semiconductor integrated circuit device according to the present invention includes:
A third memory interface unit including a plurality of electrode units and a plurality of input / output buffers, and providing the secondary storage interface or the primary storage interface;
At least part of the electrode part of the third memory interface part and at least part of the plurality of input / output buffers are
It is arranged in an electrode area and an input / output buffer area provided along the fourth side.

  According to the present invention, when the third memory interface unit provides the secondary storage interface, the data from the first image data interface unit and the second image data interface unit to the first memory interface unit. It is possible to effectively reduce the overlapping portion of the wiring area for the line and the wiring area for the data line from the first memory interface unit to the third memory interface unit.

  Further, when the third memory interface unit provides the secondary storage interface, the third memory interface unit is connected to the first image data interface unit on the substrate of the data recording apparatus using the semiconductor integrated circuit device according to the present invention. A first external device (camera module, etc.), a second external device (camera module, etc.) connected to the second image data interface unit, a primary storage device, and a secondary storage device are respectively connected to the first semiconductor chip. The second external device, the second external device, the primary storage device, the secondary storage device and the present invention. There is no need to cross wirings formed between such semiconductor integrated circuit devices on the substrate. Therefore, the design of the substrate becomes easy, the number of layers of the substrate can be reduced, and the effect of cost reduction can be obtained.

(9) A semiconductor integrated circuit device according to the present invention comprises:
A part of the electrode part of the third memory interface part and a part of the plurality of input / output buffers are arranged in an electrode area and an input / output buffer area provided along the first side. And

  The plurality of electrode units and the plurality of input / output buffers of the third memory interface unit are provided along the electrode side and the input / output buffer region provided along the first side and the fourth side. It may be arranged in the electrode region and the input / output buffer region.

  The plurality of electrode units and the plurality of input / output buffers of the second memory interface unit are provided along the electrode side and the input / output buffer region provided along the second side and the fourth side. The plurality of electrode units and the plurality of input / output buffers of the third memory interface unit are arranged in the electrode region and the input / output buffer region that are provided along the first side. You may make it arrange | position to the buffer area | region and the electrode area | region and input-output buffer area | region provided along the 4th edge | side.

  The secondary storage device or primary storage device connected to the third memory interface unit may be, for example, a USB memory. In this case, the USB controller is arranged near the corner where the fourth side and the first side intersect, and a part of the electrode part of the third memory interface part and a part of the input / output buffer are arranged along the fourth side. The electrode area and the input / output buffer area are provided, and the remaining part of the electrode part of the third memory interface part and the remaining part of the input / output buffer are provided along the first side. It may be arranged in the area and the input / output buffer area. By arranging in this way, the length of the wiring connecting the USB controller and the third memory interface unit can be shortened.

(10) A semiconductor integrated circuit device according to the present invention includes:
A first image processing unit that performs conversion processing on image data supplied to the inside of the semiconductor chip by the first image data interface unit;
A second image processing unit that performs conversion processing on image data supplied to the inside of the semiconductor chip by the second image data interface unit;
The first image processing unit is arranged next to the first image data interface unit, and the second image processing unit is arranged next to the second image data interface unit. To do.

  According to the present invention, the length of the data line wiring from the first image data interface unit to the first image processing unit and the length of the data line wiring from the second image data interface unit to the second image processing unit. Therefore, the wiring area can be reduced and the image processing speed can be increased.

(11) A semiconductor integrated circuit device according to the present invention comprises:
A first AD converter for performing processing for converting analog image data supplied to the inside of the semiconductor chip by the first image data interface unit into digital image data;
A second AD conversion unit that performs processing for converting analog image data supplied to the inside of the semiconductor chip by the second image data interface unit into digital image data;
The first AD conversion unit is arranged next to the first image data interface unit, and the second AD conversion unit is arranged next to the second image data interface unit. To do.

  According to the present invention, the length of the data line wiring from the first image data interface unit to the first AD conversion unit and the length of the data line wiring from the second image data interface unit to the second AD conversion unit. Therefore, the wiring area can be reduced.

(12) A semiconductor integrated circuit device according to the present invention includes:
A first image processing unit that performs a conversion process on the digital image data converted by the first AD conversion unit;
A second image processing unit that performs a conversion process on the digital image data converted by the second AD conversion unit,
The first image processing unit is arranged next to the first image data interface unit, and the second image processing unit is arranged next to the second image data interface unit. To do.

  According to the present invention, even if the first image data interface unit and the second image data interface unit can input both analog image data and digital image data, the first image data Data line wiring from the interface unit to the first AD conversion unit, data line wiring from the first image data interface unit to the first image processing unit, and second AD conversion from the second image data interface unit It is possible to reduce all the lengths of the wiring of the data lines going to the part and the lengths of the wirings of the data lines going from the second image data interface part to the second image processing part. Accordingly, the wiring area can be reduced, and the wiring efficiency can be increased.

(13) A semiconductor integrated circuit device according to the present invention includes:
The first image data interface unit includes:
Providing an interface for supplying image data taken by the first camera module outside the semiconductor chip or image data obtained by converting the image data into the semiconductor chip;
The second image data interface unit includes:
An interface is provided for supplying image data taken by a second camera module outside the semiconductor chip or image data obtained by converting the image data into the semiconductor chip.

(14) The present invention provides:
A data recording apparatus comprising the semiconductor integrated circuit device described above, a first camera module, a second camera module, a primary storage device, and a secondary storage device.

(15) The present invention provides:
An electrode region having a square or rectangular shape and for arranging a plurality of electrode portions in the peripheral portion along each side, and an input / output buffer region for arranging a plurality of input / output buffers along the electrode region A semiconductor integrated circuit device layout method including a semiconductor chip having:
The semiconductor integrated circuit device includes:
A first image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
A second image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
A plurality of electrode units and a plurality of input / output buffers are provided, and the first image data interface unit and the second image data interface unit perform conversion processing on the image data supplied to the semiconductor chip or the image data. A first memory interface unit for recording the recorded image data in a primary storage device outside the semiconductor chip and providing an interface for reading the recorded image data from the primary storage device;
A plurality of electrode portions and a plurality of input / output buffers of the first image data interface portion are disposed in at least a part of the electrode region and the input / output buffer region provided along the first side of the semiconductor chip;
A plurality of electrode portions and a plurality of electrode portions of the second image data interface portion are provided in at least a part of the electrode region and the input / output buffer region provided along the second side facing the first side of the semiconductor chip. I / O buffer is arranged,
A plurality of electrode portions and a plurality of input / output buffers of the first memory interface portion are disposed in at least a part of an electrode region and an input / output buffer region provided along the third side of the semiconductor chip; Features.

1 is a functional block diagram of a semiconductor integrated circuit device of an embodiment. FIG. 6 is a diagram for explaining an example of an operation flow when the semiconductor integrated circuit device of this embodiment is applied to a data recording device. FIG. 6 is a diagram for explaining an arrangement example of a first camera interface unit and a second camera interface unit in the semiconductor integrated circuit device of the present embodiment. FIG. 6 is a diagram for explaining another arrangement example of the first camera interface unit and the second camera interface unit in the semiconductor integrated circuit device of the present embodiment. 4 is a diagram for explaining an arrangement example of a first camera interface unit, a second camera interface unit, and a first memory interface unit in the semiconductor integrated circuit device of the present embodiment. FIG. 4 is a diagram for explaining an arrangement example of a first camera interface unit, a second camera interface unit, a first memory interface unit, and a second memory interface unit in the semiconductor integrated circuit device of the present embodiment. FIG. Arrangement example of the first memory interface unit in the case where the first memory interface unit in the semiconductor integrated circuit device of the present embodiment selects and provides the primary storage interface and the secondary storage interface by the selection signal The figure for demonstrating. 4A and 4B are diagrams for describing an arrangement example of a first AD conversion unit, a first image processing unit, a second AD conversion unit, and a second image processing unit in the semiconductor integrated circuit device of this embodiment. FIG. 10 is a diagram for explaining another arrangement example of the first memory interface unit and the second memory interface unit in the semiconductor integrated circuit device of this embodiment. FIG. 10 is a diagram for explaining another arrangement example of the first memory interface unit and the second memory interface unit in the semiconductor integrated circuit device of this embodiment. 10 is another example of a functional block diagram of the semiconductor integrated circuit device of this embodiment. FIG. 10 is a diagram for explaining an arrangement example of a third memory interface unit in the semiconductor integrated circuit device of the present embodiment; 1 shows an example of a block diagram of a data recording device including a semiconductor integrated circuit device.

The semiconductor integrated circuit device of the present embodiment is
An electrode region having a square or rectangular shape and for arranging a plurality of electrode portions in the peripheral portion along each side, and an input / output buffer region for arranging a plurality of input / output buffers along the electrode region A semiconductor integrated circuit device including a semiconductor chip having:
A first camera interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data captured by a first camera module outside the semiconductor chip to the inside of the semiconductor chip When,
A second camera interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data captured by a second camera module outside the semiconductor chip to the inside of the semiconductor chip Including
The plurality of electrode units and the plurality of input / output buffers of the first camera interface unit are
Disposed in at least a part of the electrode region and the input / output buffer region provided along the first side of the semiconductor chip;
The plurality of electrode units and the plurality of input / output buffers of the second camera interface unit are:
The semiconductor chip is arranged in at least a part of an electrode region and an input / output buffer region provided along a second side facing the first side of the semiconductor chip.

  The semiconductor integrated circuit device including the semiconductor chip may be, for example, the semiconductor chip itself, a semiconductor device in which the semiconductor chip is packaged, or a semiconductor on which the semiconductor chip of this embodiment and another semiconductor chip are mounted. It may be a device.

  According to this embodiment, it goes without saying that the signal lines are connected by hand wiring by arranging the first camera interface unit and the second camera interface unit in the peripheral part along the opposing sides. Even when the wiring is performed by the automatic wiring tool, the overlapping portion of the wiring area for wiring connected to the first camera interface unit and the wiring area for wiring connected to the second camera interface unit Can be reduced. As a result, the wiring efficiency is increased and the wiring area can be reduced, so that the area cost of the semiconductor chip can be reduced. In addition, by reducing the overlapping portion of the wiring area, interference between two image data supplied from the first camera interface unit and the second camera interface unit to the inside of the semiconductor chip and noise in the image data are reduced. Superposition can be effectively prevented and an increase in signal propagation delay due to the parasitic capacitance of the wiring can be suppressed, so that high-speed operation can be realized.

  Further, when the semiconductor integrated circuit device of the present embodiment is used for a data recording device and the front and rear images are taken, the present embodiment is provided between two camera modules on the substrate of the data recording device. If the semiconductor integrated circuit device according to the embodiment is arranged, it is not necessary to cross wirings formed between the camera modules and the semiconductor integrated circuit device according to the present embodiment on the substrate. Therefore, the design of the substrate becomes easy, the number of layers of the substrate can be reduced, and the effect of cost reduction can be obtained.

The semiconductor integrated circuit device of the present embodiment is
The plurality of electrode units and the plurality of input / output buffers of the second camera interface unit are:
The plurality of electrode units and the plurality of input / output buffers of the first camera interface unit are arranged to face each other.

  According to the present embodiment, since the length of the wiring connected to the first camera interface unit and the wiring connected to the second camera interface unit can be made substantially equal, the parasitic capacitance of these wirings can be reduced. The accompanying signal propagation delay can be made approximately equal. As a result, both image data captured by the first camera module and the second camera module are processed asynchronously or processed in synchronization within the semiconductor chip. Can be converted and recorded in the primary storage device without mistaking the correspondence relationship.

The semiconductor integrated circuit device of the present embodiment is
Image data that includes a plurality of electrode units and a plurality of input / output buffers and that is supplied to the inside of the semiconductor chip by the first camera interface unit and the second camera interface unit, or an image obtained by performing a conversion process on the image data A first memory interface unit for recording data in a primary storage device outside the semiconductor chip and providing a primary storage interface for reading the recorded image data from the primary storage device;
The plurality of electrode units and the plurality of input / output buffers of the first memory interface unit are
It is characterized in that it is disposed in at least a part of an electrode region and an input / output buffer region provided along the third side of the semiconductor chip.

  According to the present embodiment, the first memory interface unit is arranged along a side different from the side where the first camera interface unit and the second camera interface unit are arranged. Since the wiring of the data line from the second camera interface unit to the first memory interface unit does not have to pass through the vicinity of the center where there is a high possibility of being crowded with other modules and wirings, the wiring efficiency can only be increased. In addition, it is possible to reduce the possibility of noise being superimposed on the image data.

  Further, on the substrate of the data recording apparatus using the semiconductor integrated circuit device of this embodiment, the first camera module, the second camera module, and the primary storage device are respectively connected to the first side and the second side of the semiconductor chip. If the first camera module, the second camera module, the primary storage device, and the semiconductor integrated circuit device of the present embodiment are arranged on the substrate There is no need to cross. Therefore, the design of the substrate becomes easy, the number of layers of the substrate can be reduced, and the effect of cost reduction can be obtained.

The semiconductor integrated circuit device of the present embodiment is
The plurality of electrode units and the plurality of input / output buffers of the first camera interface unit are arranged in the electrode region and the input / output buffer region near the first side and the third side of the semiconductor chip. ,
The plurality of electrode units and the plurality of input / output buffers of the second camera interface unit are disposed in the electrode region and the input / output buffer region near the second side and the third side of the semiconductor chip. It is characterized by that.

  The fact that the first side and the third side of the semiconductor chip are arranged close to each other means that when the side facing the third side of the semiconductor chip is the fourth side, at least the first side What is necessary is just to be arrange | positioned near the vicinity which a 1st edge | side and a 3rd edge | intersection cross rather than the vicinity where an edge | side and a 4th edge | side cross | intersect. For example, in the plurality of electrode units and the plurality of input / output buffers of the first camera interface unit, the distance from the center point of the majority of the electrode units to the vertex where the first side and the third side intersect is the first side. May be arranged in the electrode region and the input / output buffer region so as to be shorter than the distance to the vertex where the fourth side intersects. Preferably, the plurality of electrode units and the plurality of input / output buffers of the first camera interface unit are in a predetermined range of electrode regions and input / output buffers close to a vertex at which the first side and the third side of the semiconductor chip intersect. It should be placed in the area. For example, the plurality of electrode portions are electrode regions that are as close as possible to the vertexes except for an electrode region in the vicinity of the vertex where the first side and the third side cannot be arranged due to difficulty in bonding. It is preferable to arrange them in order. Further, the plurality of input / output buffers are as close as possible to the vertexes except for an input / output buffer region near the vertex where the first side and the third side cannot be arranged for layout reasons. It is preferable to arrange them in order in the input / output buffer region so as to correspond to the electrode portions.

  Similarly, when the second side and the third side of the semiconductor chip are arranged close to each other, when the side facing the third side of the semiconductor chip is the fourth side, at least, It suffices if the second side and the third side are arranged closer to the vicinity where the second side and the fourth side intersect than the vicinity where the second side and the fourth side intersect. For example, in the plurality of electrode units and the plurality of input / output buffers of the second camera interface unit, the distance from the center point of the majority of the electrode units to the vertex where the second side and the third side intersect is the second side. May be arranged in the electrode region and the input / output buffer region so as to be shorter than the distance to the vertex where the fourth side intersects. Preferably, the plurality of electrode units and the plurality of input / output buffers of the second camera interface unit are a predetermined range of electrode regions and input / output buffers close to a vertex at which the second side and the third side of the semiconductor chip intersect. It should be placed in the area. For example, the plurality of electrode portions are electrode regions that are as close as possible to the vertexes except for an electrode region near the vertex where the second side and the third side cannot be arranged due to difficulty in bonding. It is preferable to arrange them in order. Further, the plurality of input / output buffers are as close as possible to the vertexes except for an input / output buffer region in the vicinity of the vertex where the second side and the third side intersect where the input / output buffer cannot be arranged due to layout. It is preferable to arrange them in order in the input / output buffer region so as to correspond to the electrode portions.

  According to this embodiment, the distance between the first camera interface unit and the second camera interface unit and the first memory interface unit can be shortened. Accordingly, the image data captured by the two camera modules and supplied via the first camera interface unit and the second camera interface unit are recorded in the primary storage device via the first memory interface unit. Assuming this, since the length of the wiring connected to the first camera interface unit and the second camera interface unit can be shortened, the wiring efficiency can be increased. Furthermore, since the recording operation to the primary storage device can be speeded up by shortening the wiring length, it is possible to increase the number of image data that can be stored per unit time. If the semiconductor integrated circuit device of the form is used, a data recording device with high reliability and high evidence ability can be provided.

The semiconductor integrated circuit device of the present embodiment is
In the input / output buffer region near the first side and the third side of the semiconductor chip, the power supply line of the first camera interface unit and the power supply line of the first memory interface unit are separated. ,
In the input / output buffer region near the second side and the third side of the semiconductor chip, the power supply line of the second camera interface unit and the power supply line of the first memory interface unit are separated. It is characterized by that.

  According to the present embodiment, even when the operating voltage of the first camera interface unit and the second camera interface unit and the operating voltage of the first memory interface unit are different, near the corner that cannot be used effectively Power supply isolation can be realized using the input / output buffer area.

The semiconductor integrated circuit device of the present embodiment is
Image data recorded in the primary storage device or image data obtained by converting the image data is recorded in a secondary storage device outside the semiconductor chip, including a plurality of electrode units and a plurality of input / output buffers. A second memory interface unit providing an interface for
The electrode unit and the plurality of input / output buffers of the second memory interface unit are
The semiconductor chip is disposed in at least a part of an electrode region and an input / output buffer region provided along a fourth side facing the third side of the semiconductor chip.

  According to the present embodiment, the wiring area for the data line from the first camera interface unit and the second camera interface unit to the first memory interface unit, and the second memory from the first memory interface unit It is possible to effectively reduce the overlapping portion of the wiring area for the data line toward the interface unit.

  When the integrated circuit device according to the present embodiment is used for a data recording device, it is generally necessary to perform the recording operation for the primary storage device at an overwhelmingly higher speed than the recording operation for the secondary storage device. However, by arranging the first camera interface unit and the second camera interface unit in the vicinity of the first memory interface unit, the operation of recording the image data in the primary storage device via the first memory interface unit Can be speeded up.

  Further, on the substrate of the data recording apparatus using the semiconductor integrated circuit device of this embodiment, the first camera module, the second camera module, the primary storage device, and the secondary storage device are respectively connected to the first semiconductor chip. 1st camera module, second camera module, primary storage device, secondary storage device and the present embodiment are arranged opposite to the second side, the second side, the third side, and the fourth side. It is not necessary to cross the wiring formed between the semiconductor integrated circuit devices in the form on the substrate. Therefore, the design of the substrate becomes easy, the number of layers of the substrate can be reduced, and the effect of cost reduction can be obtained.

The semiconductor integrated circuit device of the present embodiment is
The first memory interface unit includes:
Any of the primary storage interface and an interface for recording image data recorded in the primary storage device or image data obtained by converting the image data in a secondary storage device outside the semiconductor chip. It includes at least one electrode portion for outputting a selection signal for selecting and providing the selection to the outside of the semiconductor chip.

  According to the present embodiment, the data line from the first memory interface unit to the second memory interface unit is not necessary, and the wiring area can be reduced, so that the wiring efficiency can be increased.

The semiconductor integrated circuit device of the present embodiment is
A first image processing unit that performs conversion processing on image data supplied to the inside of the semiconductor chip by the first camera interface unit;
A second image processing unit that performs conversion processing on image data supplied to the inside of the semiconductor chip by the second camera interface unit,
The first image processing unit is disposed next to the first camera interface unit,
The second image processing unit is arranged next to the second camera interface unit.

  According to the present embodiment, the length of the data line that runs from the first camera interface unit to the first image processing unit and the length of the data line that runs from the second camera interface unit to the second image processing unit. Therefore, the wiring area can be reduced and the image processing speed can be increased.

The semiconductor integrated circuit device of the present embodiment is
A first AD converter that performs processing for converting analog image data supplied to the inside of the semiconductor chip by the first camera interface unit into digital image data;
A second AD conversion unit that performs processing for converting analog image data supplied to the inside of the semiconductor chip by the second camera interface unit into digital image data;
The first AD conversion unit is disposed next to the first camera interface unit,
The second AD conversion unit is arranged next to the second camera interface unit.

  According to the present embodiment, the length of the data line wiring from the first camera interface unit to the first AD conversion unit and the length of the data line wiring from the second camera interface unit to the second AD conversion unit. Therefore, the wiring area can be reduced.

The semiconductor integrated circuit device of the present embodiment is
A first image processing unit that performs a conversion process on the digital image data converted by the first AD conversion unit;
A second image processing unit that performs a conversion process on the digital image data converted by the second AD conversion unit,
The first image processing unit is disposed next to the first camera interface unit,
The second image processing unit is arranged next to the second camera interface unit.

  According to the present embodiment, even if the first camera interface unit and the second camera interface unit are capable of both analog image data input and digital image data input, the first camera interface unit Wiring from the first camera unit to the first AD conversion unit, wiring from the first camera interface unit to the first image processing unit, and from the second camera interface unit to the second AD conversion unit The lengths of the data lines and the lengths of the data lines from the second camera interface unit to the second image processing unit can be reduced. Accordingly, the wiring area can be reduced, and the wiring efficiency can be increased.

This embodiment is
A data recording apparatus comprising: the semiconductor integrated circuit device according to any one of the above; a first camera module; a second camera module; a primary storage device; and a secondary storage device. is there.

This embodiment is
An electrode region having a square or rectangular shape and for arranging a plurality of electrode portions in the peripheral portion along each side, and an input / output buffer region for arranging a plurality of input / output buffers along the electrode region A semiconductor integrated circuit device layout method including a semiconductor chip having:
The semiconductor integrated circuit device includes:
A first camera interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data captured by a first camera module outside the semiconductor chip to the inside of the semiconductor chip When,
A second camera interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data captured by a second camera module outside the semiconductor chip to the inside of the semiconductor chip When,
Image data that includes a plurality of electrode units and a plurality of input / output buffers and that is supplied to the inside of the semiconductor chip by the first camera interface unit and the second camera interface unit, or an image obtained by performing a conversion process on the image data A first memory interface unit for recording data in a primary storage device external to the semiconductor chip and providing an interface for reading the recorded image data from the primary storage device;
A plurality of electrode portions and a plurality of input / output buffers of the first camera interface portion are disposed in at least a part of the electrode region and the input / output buffer region provided along the first side of the semiconductor chip;
At least a part of the electrode region and the input / output buffer region provided along the second side opposite to the first side of the semiconductor chip, the plurality of electrode units of the second camera interface unit and the plurality of input regions. Arrange the output buffer,
A plurality of electrode portions and a plurality of input / output buffers of the first memory interface portion are disposed in at least a part of an electrode region and an input / output buffer region provided along the third side of the semiconductor chip; A semiconductor integrated circuit device layout method is characterized.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Semiconductor Integrated Circuit Device FIG. 1 is a functional block diagram of the semiconductor integrated circuit device of the present embodiment. The semiconductor integrated circuit device 10 may include a CPU 100, a memory controller 150, and a ROM 180. The CPU 100 reads out a program stored in the ROM 180 via the memory controller 150 and executes each command constituting the program, thereby controlling the operation of the semiconductor integrated circuit device 10.

  The semiconductor integrated circuit device 10 includes a first camera interface unit 110 that functions as a first image data interface unit. The first camera interface unit 110 provides an interface for supplying the image data 22 captured by the first camera module 20 to the inside of the semiconductor integrated circuit device 10. For example, when the image data 22 is digital image data, the first camera interface unit 110 is a level shifter that shifts the voltage level of the image data 22 to match the internal power supply voltage of the semiconductor integrated circuit device 10. Alternatively, when the voltage level of the image data 22 is compatible with the internal power supply voltage of the semiconductor integrated circuit device 10, a simple digital input buffer may be used. Further, when the image data 22 is analog image data, it may be an analog input buffer.

  The semiconductor integrated circuit device 10 includes a first image processing unit 120. The first image processing unit 120 performs conversion processing on the image data 112 output from the first camera interface unit 110. The first image processing unit 120 may be, for example, a JPEG encoder / decoder that compresses or expands still image data, an MPEG encoder / decoder that compresses or expands moving image data, an IP (Interlace to Progressive) converter, and the like. Good. If the image data 22 is analog image data, an AD converter is connected to the output of the first camera interface unit 110 (for example, an analog input buffer), and the analog image data is converted into digital image data. You may make it supply to the 1st image process part 120. FIG.

  The semiconductor integrated circuit device 10 includes a second camera interface unit 130 that functions as a second image data interface unit. The second camera interface unit 130 provides an interface for supplying the image data 32 captured by the second camera module 30 to the inside of the semiconductor integrated circuit device 10. For example, when the image data 32 is digital image data, the second camera interface unit 130 is a level shifter that shifts the voltage level of the image data 32 so as to match the internal power supply voltage of the semiconductor integrated circuit device 10. Alternatively, when the voltage level of the image data 32 is compatible with the internal power supply voltage of the semiconductor integrated circuit device 10, a simple digital input buffer may be used. Further, when the image data 32 is analog image data, it may be an analog input buffer. The first camera interface unit 110 and the second camera interface unit 130 do not need to have the same configuration. For example, when the image data 22 and the image data 32 are digital image data having different bit numbers, In the case where is analog image data and the other is digital image data, a different configuration may be used.

  The semiconductor integrated circuit device 10 includes a second image processing unit 140. The second image processing unit 140 performs conversion processing on the image data 132 output from the second camera interface unit 130. The second image processing unit 140 may be, for example, a JPEG encoder / decoder that compresses or expands still image data, an MPEG encoder / decoder that compresses or expands moving image data, an IP converter, and the like. When the image data 32 is analog image data, an AD converter is connected to the output of the second camera interface unit 130 (for example, an analog input buffer), and the analog image data is converted into digital image data. You may make it supply to the 2nd image process part 140. FIG.

  The semiconductor integrated circuit device 10 includes a first memory interface unit 160. The first memory interface unit 160 includes image data 112 and 132 that are supplied to the inside by the first camera interface unit 110 and the second camera interface unit 130, or image data 122 that is obtained by performing conversion processing on the image data 112 and 132, 142 is recorded in the primary storage device 40, and a primary storage interface for reading the recorded image data from the primary storage device 40 is provided. For example, the first memory interface unit 160 may be a level shifter that shifts the voltage level of the image data 162 or 152 so as to match the internal power supply voltage of the semiconductor integrated circuit device 10 or the power supply voltage of the primary storage device 40. Alternatively, when the internal power supply voltage of the semiconductor integrated circuit device 10 and the power supply voltage of the primary storage device 40 are compatible, a simple digital input / output buffer may be used.

  The semiconductor integrated circuit device 10 includes a second memory interface unit 170. The second memory interface unit 170 provides a secondary storage interface for recording the image data recorded in the primary storage device 40 or the image data obtained by converting the image data in the secondary storage device 50. To do. For example, the second memory interface unit 170 may be a level shifter that shifts the voltage level of the image data 172 or 154 so as to match the internal power supply voltage of the semiconductor integrated circuit device 10 or the power supply voltage of the secondary storage device 50. Alternatively, when the internal power supply voltage of the semiconductor integrated circuit device 10 and the power supply voltage of the secondary storage device 50 are compatible, a simple digital input / output buffer may be used.

The semiconductor integrated circuit device 10 uses the first camera interface unit 110 and the second camera interface unit 130 corresponding to the first camera module and the second camera module as the first image data corresponding to another interface. The interface unit and the second image data interface unit may be replaced. For example, the first image data interface unit and the second image data interface unit may have an interface corresponding to a JPEG encoder IC or an IP conversion IC.
FIG. 2 is a diagram for explaining an example of an operation flow when the semiconductor integrated circuit device of the present embodiment is applied to a data recording device. The operation flow will be described below with reference to FIG.

  The CPU 100 receives the image data 22 received by the first camera interface unit 110 or the image processed by the first image processing unit 120 for the image data 22 captured and supplied by the first camera module 20 at regular time intervals. The data 122 is sequentially and sequentially recorded in a predetermined storage area of the primary storage device 40 via the first memory interface unit 160 (step S10).

  Similarly, in the CPU 100, the image data 132 received by the second camera interface unit 130 or the second image processing unit 140 converts the image data 32 that is captured and supplied by the second camera module 30 at regular time intervals. The applied image data 142 is sequentially and sequentially recorded in a predetermined storage area of the primary storage device 40 via the first memory interface unit 160 (step S12).

  In step S10 and step S12, when the first image processing unit 120 and the second image processing unit 140 have a DMA (Direct Memory Access) transfer function, the first image processing unit 120 and the second image processing are performed. The unit 140 can directly record the image data 122 and 142 in the primary storage device 40 via the first memory interface unit 160. In that case, the load on the CPU 100 can be reduced.

  Until a predetermined event (for example, an event such as the output of an acceleration sensor not shown exceeds a threshold value) occurs, the CPU 100 records image data in the primary storage device 40 at regular time intervals (steps S10 to S14). ). When a predetermined event occurs, the CPU 100 sequentially reads out part of the image data recorded in the primary storage device 40 in step S10 and step S12 (for example, image data after 15 seconds before the event occurs) (step S16). ) And recorded in the secondary storage device 50 through the second memory interface unit 170 (step S18).

  Similarly, the CPU 100 causes the image data 132 received by the second camera interface unit 130 or the second image processing unit 140 to perform conversion processing on the image data 32 that the second camera module 30 periodically captures and supplies. The processed image data 142 is cyclically recorded sequentially in a predetermined storage area of the primary storage device 40 via the first memory interface unit 160 (step S22).

  Until a certain number of image data is recorded in the secondary storage device 50 (for example, image data for 15 seconds before the event occurrence and 5 seconds after the event occurrence), the CPU 100 stores data in the secondary storage device 50 and the primary storage device 40. Image data is sequentially recorded (steps S16 to S24). As a result, necessary image data before and after the occurrence of a predetermined event can be recorded in the secondary storage device 50 and stored for a long time.

  FIG. 3 is a diagram for explaining an arrangement example of the first camera interface unit and the second camera interface unit in the semiconductor integrated circuit device of the present embodiment. A semiconductor chip 200 included in the semiconductor integrated circuit device of the present embodiment has a square or rectangular shape, an electrode region 210 for arranging a plurality of electrode portions 212 in the peripheral portion along each side, and an electrode An input / output buffer area 220 for arranging a plurality of input / output buffers 222 along the area 210 is provided.

  The electrode unit 212 is used for inputting a signal from the outside of the semiconductor chip 200 or outputting a signal to the outside of the semiconductor chip 200. The input / output buffer 222 is connected to the electrode unit 212, and supplies the voltage level of a signal input to the electrode unit 212 in accordance with the internal operating voltage level of the semiconductor chip 200 or the inside of the semiconductor chip 200. It functions as a level shifter for adjusting the operating voltage level to the operating voltage level of the external module and outputting from the electrode unit 212. Therefore, the input / output buffer 222 includes at least a high power supply voltage (HVDD) supply line, a low power supply voltage (LVDD) supply line, and a ground potential (VSS) supply line. For example, when the internal power supply voltage is LVDD and the power supply voltage of the external module is HVDD, the input / output buffer 222 changes the power supply voltage from HVDD (for example, 2.4 V to 3.6 V) to LVDD (for example, 1 .8V) or function as a level shifter that converts from LVDD to HVDD. When the power supply voltage of the external module and the internal power supply voltage are compatible, the input / output buffer 222 can function as a simple buffer by using the high power supply voltage supply line and the low power supply voltage supply line shorted. You can also. Note that the input / output buffer 212 may be a buffer that can only input, a buffer that can only output, or a buffer that can input and output. By arranging a plurality of input / output buffers 222 adjacent to each other, in the input / output buffer region 220, a high power supply voltage (HVDD) supply line 224, a low power supply voltage (LVDD) supply line 226, a ground potential ( VSS) supply line 228 is formed, and each potential of HVDD, LVDD, and VSS is supplied from a predetermined electrode portion 212. Since the input / output buffer 222 cannot be arranged near the four corners of the semiconductor chip 200, only the supply lines are separately provided so that the supply lines are annular.

  Thus, it goes without saying that the signal lines are connected by hand wiring by arranging the first camera interface unit 110 and the second camera interface unit 130 in the peripheral part along the opposing sides. Even when wiring is performed by an automatic wiring tool, an overlapping portion of a wiring area for wiring connected to the first camera interface unit 110 and a wiring area for wiring connected to the second camera interface unit 130 Can be reduced. As a result, the wiring efficiency is increased and the wiring area can be reduced, so that the area cost of the semiconductor chip 200 can be reduced. Further, by reducing the overlapping portion of the wiring area, interference between the two image data supplied from the first camera interface unit 110 and the second camera interface unit 130 to the inside of the semiconductor chip 200 and image data can be prevented. Superposition of noise can be effectively prevented, and an increase in signal propagation delay due to the parasitic capacitance of the wiring can be suppressed, so that high-speed operation can be realized.

  FIG. 4 is a diagram for explaining another arrangement example of the first camera interface unit and the second camera interface unit in the semiconductor integrated circuit device of the present embodiment. The same components as those in FIG. The plurality of electrode units 212 and the plurality of input / output buffers 222 of the first camera interface unit 110 are formed of the electrode region 210 and the input / output buffer region 220 provided along the first side (230) of the semiconductor chip 200. The plurality of electrode units 212 and the plurality of input / output buffers 222 of the second camera interface unit 130 arranged at least in part are provided with the electrode region 210 and the input / output buffer provided along the second side (240). The first camera interface unit 110 is disposed in the region 220 so as to face the plurality of electrode units 212 and the plurality of input / output buffers 222. For example, the plurality of electrode units 212 and the plurality of input / output buffers 222 of the first camera interface unit 110 and the plurality of electrode units 212 and the plurality of input / output buffers 222 of the second camera interface unit 130 are arranged at the center of the semiconductor chip 200. They are arranged at positions that are line-symmetric with respect to the line 202. Further, when the number of electrode portions of the first camera interface unit 110 and the number of electrode portions of the second camera interface unit 130 are different, for example, the electrode unit located at the center of the first camera interface unit 110 The electrode part located at the center of the second camera interface part 130 is arranged so as to be symmetrical with respect to the center line 202 of the semiconductor chip 200.

  As described above, the first camera interface unit 110 and the second camera interface unit 130 are arranged along the opposing sides so as to be opposed to the peripheral part, and thereby the wiring connected to the first camera interface unit 110 and It is easy to make the wiring lengths of the wirings connected to the second camera interface unit 130 substantially equal (that is, to make these wirings symmetrical in FIG. 4), and to the parasitic capacitance of these wirings. The accompanying signal propagation delay can be made approximately equal. As a result, both the image data captured by the first camera module and the second camera module are processed asynchronously or the image data of both are processed in synchronization within the semiconductor chip 200. Conversion processing can be performed without erroneous data correspondence and recorded in the primary storage device. Therefore, if the semiconductor integrated circuit device of this embodiment is used, a data recording device with high reliability and high evidence ability can be provided.

  FIG. 5 is a diagram for explaining an arrangement example of the first camera interface unit, the second camera interface unit, and the first memory interface unit in the semiconductor integrated circuit device of the present embodiment. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted. The semiconductor chip 200 further includes a first memory interface unit 160 in addition to the first camera interface unit 110 and the second camera interface unit 130. The first memory interface unit 160 includes a plurality of electrode units 212 and a plurality of input / output buffers 222, and includes an electrode region 210 and an input / output buffer region provided along the third side (250) of the semiconductor chip 200. 220 is disposed at least in part. The plurality of electrode units 212 and the plurality of input / output buffers 222 of the first camera interface unit 110 are brought close to the vicinity where the first side (230) and the third side (250) of the semiconductor chip 200 intersect with each other. 210 and the input / output buffer area 220. The plurality of electrode units 212 and the plurality of input / output buffers 222 of the second camera interface unit 130 are brought close to the vicinity where the second side (240) and the third side (250) of the semiconductor chip 200 intersect with each other. 210 and the input / output buffer area 220.

  As described with reference to FIG. 2, when the semiconductor integrated circuit device of this embodiment is applied to a data recording device, the first camera interface unit 110 and the second camera interface unit 130 to the first memory interface unit 160. There is a flow of data going. As described above, by arranging the first camera interface unit 110 and the second camera interface unit 130 at positions close to the first memory interface unit 160 along the opposing sides, the first camera interface unit 110 and The distance between the second camera interface unit 130 and the first memory interface unit 160 can be shortened. Accordingly, the image data captured by the two camera modules and supplied via the first camera interface unit 110 and the second camera interface unit 130 are respectively stored in the primary storage device via the first memory interface unit 160. Assuming that recording is performed on the first and second camera interface units 110 and 130, the wiring efficiency can be increased. In addition, by shortening the wiring length, the operation of recording image data in the primary storage device via the first memory interface unit 160 can be speeded up, so that images that can be stored per unit time are stored. It is possible to increase the number of data. By using the semiconductor integrated circuit device of this embodiment, it is possible to provide a data recording device with high reliability and evidence capability.

  In addition, when the operating voltage of the first camera interface unit 110 and the second camera interface unit 130 and the operating voltage of the first memory interface unit 160 are different, the semiconductor chip 200 includes the first camera interface unit 110 and In order to separate the power source of the second camera interface unit 130 and the power source of the first memory interface unit 160, power source separation cells 232 and 242 may be included. The power supply isolation cell is a cell that does not include all or part of the high power supply voltage (HVDD) supply line, the low power supply voltage (LVDD) supply line, and the ground potential (VSS) supply line. The power supply isolation cells 232 and 242 do not include only a high power supply voltage (HVDD) supply line. Therefore, in the input / output buffer region 220 near the first side (230) and the third side (250) of the semiconductor chip 200, the power supply line (high power supply voltage supply line) of the first camera interface unit 110 is used. 224) and the power supply line (high power supply voltage supply line 252) of the first memory interface unit 160 are separated, and the second side (240) and the third side (250) of the semiconductor chip 200 intersect each other. In the input / output buffer area 220, the power supply line (high power supply voltage supply line 224) of the second camera interface unit 130 and the power supply line (high power supply voltage supply line 252) of the first memory interface unit 160 are separated. Yes.

  Here, due to the difficulty of bonding, electrode portions cannot be concentrated in the electrode regions near the four corners of the semiconductor chip 200. As a result, even if many input / output buffers are placed in the input / output buffer areas near the four corners, all of them cannot be used effectively in correspondence with the electrode portions. Therefore, power supply isolation is realized by adding power supply isolation cells in the input / output buffer areas near the four corners or by directly disconnecting the power supply wiring without newly adding an area for power supply isolation. be able to.

  FIG. 6 is a diagram for explaining an arrangement example of the first camera interface unit, the second camera interface unit, the first memory interface unit, and the second memory interface unit in the semiconductor integrated circuit device of this embodiment. It is. The same components as those in FIG. The semiconductor chip 200 further includes a second memory interface unit 170 in addition to the first camera interface unit 110, the second camera interface unit 130, and the first memory interface unit 160. The second memory interface unit 170 includes a plurality of electrode units 212 and a plurality of input / output buffers 222, and is provided along a fourth side (260) facing the third side (250) of the semiconductor chip 200. The electrode region 210 and the input / output buffer region 220 are disposed at least in part.

  As described with reference to FIG. 2, when the semiconductor integrated circuit device of this embodiment is applied to a data recording device, the first camera interface unit 110 and the second camera interface unit 130 to the first memory interface unit 160. There is a data flow that goes to the second memory interface unit 170 from the first memory interface unit 160. As described above, the first memory interface unit 160 and the second memory interface unit 170 are arranged along two sides different from the two sides on which the first camera interface unit 110 and the second camera interface unit 130 are arranged. Accordingly, a wiring area for data lines from the first camera interface unit 110 and the second camera interface unit 130 to the first memory interface unit 160, and the second memory interface from the first memory interface unit 160 to the second memory interface. It is possible to effectively reduce the overlapping portion of the wiring area for the data line toward the unit 170.

  When the integrated circuit device according to the present embodiment is used for a data recording device, it is generally necessary to perform the recording operation for the primary storage device at an overwhelmingly higher speed than the recording operation for the secondary storage device. However, by arranging the first camera interface unit 110 and the second camera interface unit 130 in the vicinity of the first memory interface unit 160, image data is stored in the primary storage device via the first memory interface unit 160. The recording operation can be speeded up.

  FIG. 7 shows the first memory interface in the case where the first memory interface unit in the semiconductor integrated circuit device of the present embodiment selects and provides the primary storage interface and the secondary storage interface with a selection signal. It is a figure for demonstrating the example of arrangement | positioning of a part. The same components as those in FIG. The first memory interface unit 160 converts image data supplied to the inside of the semiconductor chip 200 by the first camera interface unit 110 and the second camera interface unit 130 or image data obtained by converting the image data into the semiconductor chip. The primary storage interface for reading out the recorded image data from the primary storage device, and the image data recorded in the primary storage device or the conversion process into the image data. Electrodes 254 and 256 for outputting a selection signal for selecting and providing one of the secondary storage interfaces for recording the applied image data in the secondary storage device to the outside of the semiconductor chip 200 are included. . For example, when the selection signal (chip select signal) output from the electrode unit 254 is active, the primary storage interface is selected, and when the selection signal (chip select signal) output from the electrode unit 256 is active, the secondary storage is performed. An interface may be selected. Further, either the primary storage interface or the secondary storage interface may be selected according to the polarity of one single selection signal. All of the electrode units other than the electrode units 254 and 256 included in the first memory interface unit 160 may be shared by the primary storage interface and the secondary storage interface, or may be shared by only a part. May be.

  As described with reference to FIG. 2, when the semiconductor integrated circuit device of this embodiment is applied to a data recording device, the first camera interface unit 110 and the second camera interface unit 130 to the first memory interface unit 160. There is a data flow that goes to the second memory interface unit 170 from the first memory interface unit 160. As described above, the first memory interface unit 160 selects and provides the primary storage interface and the secondary storage interface by the selection signal, so that the first memory interface unit 160 to the second memory interface unit are provided. The data line going to 170 becomes unnecessary, and the wiring area can be reduced, so that the wiring efficiency can be increased.

  FIG. 8 is a diagram for explaining an arrangement example of the first AD conversion unit, the first image processing unit, the second AD conversion unit, and the second image processing unit in the semiconductor integrated circuit device of this embodiment. It is. The same components as those in FIG. The semiconductor chip 200 includes a first AD converter 270. The first AD conversion unit 270 performs processing for converting analog image data supplied to the inside of the semiconductor chip 200 by the first camera interface unit 110 into digital image data. The semiconductor chip 200 includes a first image processing unit 120. The first image processing unit 120 performs a conversion process on the digital image data converted by the first AD conversion unit 270. The first AD conversion unit 270 and the first image processing unit 120 are arranged next to the first camera interface unit 110. The semiconductor chip 200 includes a second AD converter 280. The second AD conversion unit 280 performs processing for converting analog image data supplied to the inside of the semiconductor chip 200 by the second camera interface unit 130 into digital image data. The semiconductor chip 200 includes a second image processing unit 140. The second image processing unit 140 performs a conversion process on the digital image data converted by the second AD conversion unit 280. The second AD conversion unit 280 and the second image processing unit 140 are arranged next to the second camera interface unit 130.

  As described above, by arranging the first AD conversion unit 270 and the first image processing unit 120 next to the first camera interface unit 110, the first camera interface unit 110 can input analog image data and digitally. Even in a case where both image data input is possible, a wiring region for wiring between the first camera interface unit 110, the first AD conversion unit 270, and the first image processing unit 120 Can be reduced. Further, even when the output of the first AD conversion unit 270 is supplied to the input of the first image processing unit 120, the wiring area can be reduced.

  Similarly, by arranging the second AD conversion unit 280 and the second image processing unit 140 next to the second camera interface unit 130, the second camera interface unit 130 can input analog image data and digital images. Even when both data input is possible, a wiring area for wiring between the second camera interface unit 130, the second AD conversion unit 280, and the second image processing unit 140 is provided. Can be reduced. Further, even when the output of the second AD conversion unit 280 is supplied to the input of the second image processing unit 140, the wiring area can be reduced.

  The first AD converter 270 and the first image processor 120 do not need to be arranged next to each other. Rather, digital noise generated by the image processor 120 is superimposed on the analog image data input of the AD converter 270. In order to avoid this, it is desirable that the first AD conversion unit 270 and the first image processing unit 120 be arranged with a sufficient distance. Similarly, it is desirable that the second AD conversion unit 280 and the second image processing unit 140 are arranged with a sufficient distance.

  FIG. 9 is a diagram for explaining another arrangement example of the first memory interface unit and the second memory interface unit in the semiconductor integrated circuit device of the present embodiment. The same components as those in FIG.

  The first memory interface unit 160 includes a plurality of electrode units 212 and a plurality of input / output buffers 222, part of which is provided with an electrode region 210 provided along the third side (250) of the semiconductor chip 200 and The remaining portion is disposed in the input / output buffer region 220, and the remaining portion is disposed in the electrode region 210 and the input / output buffer region 220 provided along the first side (230). For example, when the number of the electrode units 212 and the input / output buffers 222 included in the first memory interface unit 160 is large, the electrode regions 210 and the input / output buffer regions provided along the third side (250). In some cases, not all electrode portions 212 and input / output buffers 222 can be arranged in 220. In such a case, a part of the electrode part 212 and the input / output buffer 222 included in the first memory interface part 160 are part of the electrode region 210 and the input / output buffer provided along the first side (230). You may make it arrange | position to the area | region 220. FIG. Similarly, the electrode section 212 and the input / output buffer 222 included in the first memory interface section 160 are provided along the third side (250) and the input / output buffer area 220 and the second side. It may be arranged in the electrode region 210 and the input / output buffer region 220 provided along (240).

  The second memory interface unit 170 includes a plurality of electrode units 212 and a plurality of input / output buffers 222, some of which are electrode regions 210 provided along the fourth side (260) of the semiconductor chip 200 and The remaining portion is disposed in the input / output buffer region 220, and the remaining portion is disposed in the electrode region 210 and the input / output buffer region 220 provided along the second side (240). For example, in the case where the CPU 100 is arranged near the corner where the fourth side (260) and the second side (240) intersect, in order to efficiently wire the CPU 100 and the second memory interface 170, the second A part of the electrode part 212 and the input / output buffer 222 included in the memory interface part 170 are arranged in the electrode area 210 and the input / output buffer area 220 provided along the fourth side (260), and the remaining part. May be arranged in the electrode region 210 and the input / output buffer region 220 provided along the second side (240). Similarly, the electrode unit 212 and the input / output buffer 222 included in the second memory interface unit 170 are provided along the fourth side (260), and the electrode region 210 and the input / output buffer region 220 and the first side. It may be arranged in the electrode region 210 and the input / output buffer region 220 provided along (230).

  FIG. 10 is a diagram for explaining another arrangement example of the first memory interface unit and the second memory interface unit in the semiconductor integrated circuit device of the present embodiment. The same components as those in FIG.

  The first memory interface unit 160 includes a plurality of electrode units 212 and a plurality of input / output buffers 222, part of which is provided with an electrode region 210 provided along the third side (250) of the semiconductor chip 200 and Arranged in the input / output buffer region 220, the remaining part is provided along the electrode region 210 and the input / output buffer region 220 and the second side (240) provided along the first side (230). The electrode region 210 and the input / output buffer region 220 are disposed. For example, when the number of the electrode units 212 and the input / output buffers 222 included in the first memory interface unit 160 is large, the electrode regions 210 and the input / output buffer regions provided along the third side (250). In some cases, not all electrode portions 212 and input / output buffers 222 can be arranged in 220. In such a case, a part of the electrode part 212 and the input / output buffer 222 included in the first memory interface part 160 are part of the electrode region 210 and the input / output buffer provided along the first side (230). It may be arranged in the electrode region 210 and the input / output buffer region 220 provided along the region 220 and the second side (240).

  The second memory interface unit 170 includes a plurality of electrode units 212 and a plurality of input / output buffers 222, some of which are electrode regions 210 provided along the fourth side (260) of the semiconductor chip 200 and Arranged in the input / output buffer region 220, the remaining part is provided along the electrode region 210 and the input / output buffer region 220 and the second side (240) provided along the first side (230). The electrode region 210 and the input / output buffer region 220 are disposed. For example, when the number of the electrode units 212 and the input / output buffers 222 included in the second memory interface unit 170 is large, the electrode regions 210 and the input / output buffer regions provided along the fourth side (260). In some cases, not all electrode portions 212 and input / output buffers 222 can be arranged in 220. In such a case, a part of the electrode unit 212 and the input / output buffer 222 included in the second memory interface unit 170 are partly provided along the first side (230) and the electrode region 210 and the input / output buffer. It may be arranged in the electrode region 210 and the input / output buffer region 220 provided along the region 220 and the second side (240).

  FIG. 11 is another example of a functional block diagram of the semiconductor integrated circuit device of this embodiment. The same components as those in FIG.

  The semiconductor integrated circuit device 12 includes a third memory interface unit 190. The third memory interface unit 190 is an interface for secondary storage for recording image data recorded in the primary storage device 40 or image data obtained by converting the image data in the secondary storage device 60, or The image data 112 and 132 supplied by the first camera interface unit 110 and the second camera interface unit 130 or the image data 122 and 142 obtained by converting the image data 112 and 132 are stored in the primary storage device 60. An interface for primary storage for recording and reading recorded image data from the primary storage device 60 is provided. For example, the third memory interface unit 190 sets the voltage level of the image data 192 or 156 so as to match the internal power supply voltage of the semiconductor integrated circuit device 12 or the power supply voltage of the secondary storage device (or primary storage device) 60. It may be a level shifter to be shifted, or if the internal power supply voltage of the semiconductor integrated circuit device 12 and the power supply voltage of the secondary storage device (or primary storage device) 60 are compatible, it is a mere digital input / output buffer. Also good. The secondary storage device (or primary storage device) 60 may be a USB memory, for example. In that case, a part of the memory controller 150 functions as a USB controller for controlling data transmission and reception compliant with the USB standard between the CPU 100 and the secondary storage device (or primary storage device) 60 (USB memory). You may let them.

  FIG. 12 is a diagram for explaining an arrangement example of the third memory interface unit in the semiconductor integrated circuit device of the present embodiment. The same components as those in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted.

  The third memory interface unit 190 includes a plurality of electrode units 212 and a plurality of input / output buffers 222, some of which are electrode regions 210 provided along the fourth side (260) of the semiconductor chip 200 and The remaining portion is disposed in the input / output buffer region 220, and the remaining portion is disposed in the electrode region 210 and the input / output buffer region 220 provided along the first side (230). For example, when a USB memory is connected as the secondary storage device (or primary storage device) 60 to the semiconductor integrated circuit device 12, wiring for connecting the USB controller and the third memory interface unit 190 to satisfy the USB specifications Should be as short as possible. Therefore, a part of the memory controller 150 functioning as a USB controller is arranged near the corner where the fourth side (260) and the first side (230) intersect, and the electrode unit included in the third memory interface unit 190 212 and a part of the input / output buffer 222 are arranged in the electrode region 210 and the input / output buffer region 220 provided along the fourth side (260), and the remaining part is arranged along the first side (230). The electrode area 210 and the input / output buffer area 220 may be arranged.

2. Data Recording Device FIG. 13 shows an example of a block diagram of the data recording device of the present embodiment. The data recording device 800 includes an integrated circuit device 810, a first camera module 820, a second camera module 830, a primary storage device 840, a secondary storage device 850, a power generation unit 860, and a sensor 870.

  The first camera module 820 and the second camera module 830 take images at regular time intervals. The primary storage device 840 is for temporarily and sequentially storing a set of image data photographed at the same time by the first camera module 820 and the second camera module 830, such as SDRAM (Synchronous DRAM). It may be a volatile memory. The secondary storage device 850 is for storing a set of required image data among the sets of image data recorded in the primary storage device 840 for a long period of time, and may be a non-volatile memory such as a flash memory. For example, a storage medium such as a CF (Compact Flash) memory card or an SD (Secure Digital) memory card may be used. The power generation unit 860 is for generating various power sources used in the data recording apparatus 800. The sensor 870 is for detecting the occurrence of a predetermined event (for example, a sudden increase in acceleration when an accident occurs).

  The integrated circuit device 810 cyclically sequentially sets a set of image data captured at the same time by the first camera module 820 and the second camera module 830 to a predetermined storage area of the primary storage device 840 at regular time intervals. Process to record. When the integrated circuit device 810 determines that a predetermined event has occurred based on the output of the sensor 870, the integrated circuit device 810 continues the process of sequentially recording the set of image data in the primary storage device 840 and an event occurs. A set of image data of a predetermined time before and after an event is generated by performing processing of reading from the primary storage device 840 in order from a set of image data before a predetermined time to be recorded in the secondary storage device 850 in time sequence. If it is recorded in the next storage device, the process is terminated.

  As the data recording device 800, for example, there is a drive recorder that is installed in an automobile and records forward images before and after an accident and images inside the vehicle.

  Note that the data recording apparatus 800 includes devices that perform conversion processing on image data (YUV data and RGB data) captured by the first camera module and the second camera module, respectively, and the semiconductor integrated circuit device 810 includes conversion processing. The image data subjected to the above may be supplied. For example, the data recording apparatus 800 may include a device that performs JPEG encoding or IP conversion on the outputs of the first camera module and the second camera module, respectively.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

  DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit device, 20 1st camera module, 22 Image data, 30 2nd camera module, 32 Image data, 40 Primary storage device, 50 Secondary storage device, 60 Secondary storage device (Primary storage device ), 100 CPU, 110 First camera interface unit (first image data interface unit), 112 Image data, 120 First image processing unit, 122 Image data, 130 Second camera interface unit (Second image) Data interface unit), 132 image data, 140 second image processing unit, 142 image data, 150 memory controller, 152 image data, 154 image data, 156 image data, 160 first memory interface unit, 162 image data, 170 Second memory interface 172 Image data, 180 ROM, 190 Third memory interface unit, 192 Image data, 200 Semiconductor chip, 202 Semiconductor chip center line, 210 electrode area, 212 electrode section, 220 I / O buffer area, 222 I / O Buffer, 224 High power supply voltage (HVDD) supply line, 226 Low power supply voltage (LVDD) supply line, 228 Ground potential (VSS) supply line, 230 First side, 232 Power supply isolation cell, 240 Second side, 242 Power supply Isolation cell, 250 third side, 252 high power supply voltage (HVDD) supply line, 254 primary storage device selection signal output electrode unit, 256 secondary storage device selection signal output electrode unit, 260 fourth side, 270 first AD converter, 280 Second AD converter, 800 data recording device, 810 Semiconductor integrated circuit ASIC), 820 the first camera module 830 a second camera module, 840 the primary storage device, 850 secondary storage device, 860 power generating unit, 870 sensor.

A semiconductor integrated circuit device according to one application example of the present invention has a square or rectangular shape, an electrode region for disposing a plurality of electrode portions in a peripheral portion along each side, and the electrode region A semiconductor integrated circuit device including a semiconductor chip having an input / output buffer region for arranging a plurality of input / output buffers, and including a plurality of electrode portions and a plurality of input / output buffers, An interface for supplying image data to the inside of the semiconductor chip is provided, including a first image data interface unit that provides an interface for supplying the image data to the inside of the semiconductor chip, a plurality of electrode units, and a plurality of input / output buffers. A second image data interface unit; a plurality of electrode units; and a plurality of input / output buffers. Image data supplied to the inside of the semiconductor chip by the second image data interface unit or image data obtained by converting the image data in a primary storage device outside the semiconductor chip, and recorded image data And a first memory interface unit that provides a primary storage interface for reading data from the primary storage device, wherein the first image data interface unit is provided along a first side of the semiconductor chip. And the second image data interface unit is provided along a second side opposite to the first side of the semiconductor chip, and the first memory interface unit is provided on the first side of the semiconductor chip. Entry and exit in the vicinity of the first side and the third side provided along the third side other than the second side and the second side Buffer area, and, in the output buffer area in the vicinity of said second side and said third side intersect, the power supply line is characterized in that it is separated by the power separating cells.
In the semiconductor integrated circuit device according to one application example described above, the power supply isolation cell is a cell that does not include all or part of the wiring of the high power supply voltage supply line, the low power supply voltage supply line, and the ground potential supply line. Is preferred.
In the semiconductor integrated circuit device according to one application example described above, it is preferable that the power source separation cell is disposed in input / output buffer regions at four corners of the semiconductor chip.
In the semiconductor integrated circuit device according to one application example, each of the input / output buffers of the first image data interface unit, the second image data interface unit, and the first memory interface unit includes the semiconductor chip. It is preferable not to be arranged in the input / output buffer areas at the four corners.
A layout method of a semiconductor integrated circuit device according to one application example of the present invention includes a square or rectangular shape, an electrode region for arranging a plurality of electrode portions in a peripheral portion along each side, and the electrode A layout method of a semiconductor integrated circuit device including a semiconductor chip having an input / output buffer region for arranging a plurality of input / output buffers along the region, wherein the semiconductor integrated circuit device includes a plurality of electrode portions and a plurality of electrode portions. A first image data interface unit that includes an input / output buffer and provides an interface for supplying image data to the inside of the semiconductor chip; a plurality of electrode units; and a plurality of input / output buffers. A second image data interface unit providing an interface for supplying the chip inside, a plurality of electrode units, and a plurality of input / outputs Image data supplied to the inside of the semiconductor chip by the first image data interface unit and the second image data interface unit or image data obtained by performing conversion processing on the image data. And a first memory interface unit providing an interface for reading the recorded image data from the primary storage device, and along the first side of the semiconductor chip, the first memory interface unit provides an interface for reading the recorded image data from the primary storage device. One image data interface unit is disposed, and the second image data interface unit is disposed along a second side opposite to the first side of the semiconductor chip, and the first side and the third side An input / output buffer area in the vicinity of the intersection of the second side and the input / output buffer in the vicinity of the intersection of the second side and the third side Characterized by arranging the power separation cell region.
In the layout method of a semiconductor integrated circuit device according to the above one application example, the power source separation cell does not include all or a part of wiring of a high power supply voltage supply line, a low power supply voltage supply line, and a ground potential supply line. It is preferable that
In the semiconductor integrated circuit device layout method according to one application example described above, it is preferable that the power supply isolation cells are arranged in input / output buffer regions at four corners of the semiconductor chip.
In the layout method of the semiconductor integrated circuit device according to the above one application example, the input / output buffers of the first image data interface unit, the second image data interface unit, and the first memory interface unit are provided. It is preferable not to arrange in the input / output buffer areas at the four corners of the semiconductor chip.
(1) The present invention
An electrode region having a square or rectangular shape and for arranging a plurality of electrode portions in the peripheral portion along each side, and an input / output buffer region for arranging a plurality of input / output buffers along the electrode region A semiconductor integrated circuit device including a semiconductor chip having:
A first image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
A second image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
The plurality of electrode units and the plurality of input / output buffers of the first image data interface unit are
Disposed in at least a part of the electrode region and the input / output buffer region provided along the first side of the semiconductor chip;
The plurality of electrode units and the plurality of input / output buffers of the second image data interface unit are
The semiconductor chip is arranged in at least a part of an electrode region and an input / output buffer region provided along a second side facing the first side of the semiconductor chip.

Claims (8)

An electrode region having a square or rectangular shape and for arranging a plurality of electrode portions in the peripheral portion along each side, and an input / output buffer region for arranging a plurality of input / output buffers along the electrode region A semiconductor integrated circuit device including a semiconductor chip having:
A first image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
A second image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
A plurality of electrode units and a plurality of input / output buffers are provided, and the first image data interface unit and the second image data interface unit perform conversion processing on the image data supplied to the semiconductor chip or the image data. A first memory interface unit for recording the recorded image data in a primary storage device outside the semiconductor chip and providing a primary storage interface for reading the recorded image data from the primary storage device;
The plurality of electrode units and the plurality of input / output buffers of the first image data interface unit are
Disposed in at least a part of the electrode region and the input / output buffer region provided along the first side of the semiconductor chip;
The plurality of electrode units and the plurality of input / output buffers of the second image data interface unit are
Disposed in at least a part of an electrode region and an input / output buffer region provided along a second side opposite to the first side of the semiconductor chip;
At least some of the plurality of electrode portions and at least some of the plurality of input / output buffers of the first memory interface portion are:
A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is disposed in an electrode region and an input / output buffer region provided along a third side of the semiconductor chip. In claim 1,
The plurality of electrode units and the plurality of input / output buffers of the first image data interface unit are arranged in the electrode region and the input / output buffer region near the first side and the third side of the semiconductor chip. And
The plurality of electrode units and the plurality of input / output buffers of the second image data interface unit are arranged in the electrode region and the input / output buffer region near the intersection of the second side and the third side of the semiconductor chip. A semiconductor integrated circuit device. In claim 2,
In the input / output buffer region near the first side and the third side of the semiconductor chip, the power supply line of the first image data interface unit and the power supply line of the first memory interface unit are separated. And
In the input / output buffer region near the second side and the third side of the semiconductor chip, the power supply line of the second image data interface unit and the power supply line of the first memory interface unit are separated. A semiconductor integrated circuit device. In any one of Claims 1 thru | or 3,
The first memory interface unit includes:
Secondary storage for recording the primary storage interface and image data recorded in the primary storage device or image data obtained by converting the image data in a secondary storage device outside the semiconductor chip A semiconductor integrated circuit device comprising: at least one electrode portion for outputting a selection signal for selecting and providing any one of the interfaces for use to the outside of the semiconductor chip. In any one of Claims 1 thru | or 3,
Image data recorded in the primary storage device or image data obtained by converting the image data is recorded in a secondary storage device outside the semiconductor chip, including a plurality of electrode units and a plurality of input / output buffers. A second memory interface unit providing a secondary storage interface for
At least part of the electrode part of the second memory interface part and at least part of the plurality of input / output buffers are
A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is disposed in an electrode region and an input / output buffer region provided along a fourth side facing the third side of the semiconductor chip. In claim 5,
A third memory interface unit including a plurality of electrode units and a plurality of input / output buffers, and providing the secondary storage interface or the primary storage interface;
At least part of the electrode part of the third memory interface part and at least part of the plurality of input / output buffers are
A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is disposed in an electrode region and an input / output buffer region provided along the fourth side. In claim 6,
A part of the electrode part of the third memory interface part and a part of the plurality of input / output buffers are arranged in an electrode area and an input / output buffer area provided along the first side. A semiconductor integrated circuit device. An electrode region having a square or rectangular shape and for arranging a plurality of electrode portions in the peripheral portion along each side, and an input / output buffer region for arranging a plurality of input / output buffers along the electrode region A semiconductor integrated circuit device layout method including a semiconductor chip having:
The semiconductor integrated circuit device includes:
A first image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
A second image data interface unit that includes a plurality of electrode units and a plurality of input / output buffers, and provides an interface for supplying image data to the inside of the semiconductor chip;
A plurality of electrode units and a plurality of input / output buffers are provided, and the first image data interface unit and the second image data interface unit perform conversion processing on the image data supplied to the semiconductor chip or the image data. A first memory interface unit for recording the recorded image data in a primary storage device outside the semiconductor chip and providing an interface for reading the recorded image data from the primary storage device;
A plurality of electrode portions and a plurality of input / output buffers of the first image data interface portion are disposed in at least a part of the electrode region and the input / output buffer region provided along the first side of the semiconductor chip;
A plurality of electrode portions and a plurality of electrode portions of the second image data interface portion are provided in at least a part of the electrode region and the input / output buffer region provided along the second side facing the first side of the semiconductor chip. I / O buffer is arranged,
A plurality of electrode portions and a plurality of input / output buffers of the first memory interface portion are disposed in at least a part of an electrode region and an input / output buffer region provided along the third side of the semiconductor chip; A layout method of a semiconductor integrated circuit device.

Images