JP2013166361A - Printing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform communication between an image processing part and a plurality of head control parts without applying a load to a main control part in a printing apparatus that includes a plurality of head control parts.SOLUTION: A printing apparatus includes: a plurality of head control parts that control each of a plurality of print heads; an image processing part that communicates with a plurality of head control parts through general-purpose buses; a main control part that controls the head control part through the image processing part and the general purpose buses; and a switching means that periodically switches a first mode in which a main control part controls the head control part through the image processing part and the general-purpose bus, and a second mode in which the image processing part controls communication of messages through the general-purpose buses between the image processing part and a plurality of head control parts.

Description

  The present invention relates to a printing apparatus including a plurality of print heads.

  Large format printers tend to increase the number of models equipped with multiple print heads. In many cases, a head controller is assigned to each of a plurality of print heads, and each head controller controls a corresponding print head. Japanese Patent Application Laid-Open No. 2004-228561 describes that the load on the CPU is reduced by transferring print data to a print head without using a CPU bus.

JP 2004-314423 A

A configuration in which when the image data to be printed is acquired from the outside, the main control unit causes the image processing unit to generate print data based on the image data, and the image processing unit transfers the generated print data to each of the plurality of head control units Consider a printing device equipped with In order to synchronize the ejection timing with multiple print heads, information such as whether the head control unit has completed receiving print data from the image processing unit, or reception could not be completed due to an error, information such as the head control unit and image It is necessary to communicate between the processing units.
In order for the head control unit to notify the other head control unit and the image processing unit of the information as described above, for example, the main control unit is notified by an interrupt signal, and the main control unit uses the image processing unit and the image processing unit as the interrupt service. A method in which the above information is notified to another head control unit can be considered. However, every time the above-described interrupt occurs, the main control unit must divide the CPU processing time in order to perform processing corresponding to the interrupt, and cannot perform other processing during that time. As a result, the throughput of the entire printing apparatus is reduced. Also, depending on the system response time for the interrupt signal of the main control unit, the priority order of interrupts, etc., there is a possibility that the time from when the head control unit outputs the interrupt signal until the processing for that interrupt is executed may be delayed. . If a CPU with a high processing speed is adopted, these problems can be solved, but adopting a CPU with a high processing speed leads to an increase in cost.

As another method for notifying the above-described information without using the main control unit, for example, a method in which the head control unit itself operates as a bus master and directly communicates with another head control unit is conceivable. However, in this case, each head control unit needs to comply with a bus right acquisition protocol in accordance with a specification such as a PCI bus. For this reason, the number of signal terminals and the package size increase, leading to an increase in cost. In addition, a high-speed clock is required to minimize the arbitration period when acquiring the bus right, and in that case, the number of board layers and the wiring area increase in order to ensure signal quality. This leads to an increase in cost. Alternatively, as another method of notifying the above information without using the main control unit, a method of providing a dedicated signal line for communication between the head control units can be considered. However, an increase in the number of signal terminals leads to an increase in the cost of the head controller. Also, the increase in wiring area increases the board size, leading to an increase in overall cost.
SUMMARY An advantage of some aspects of the invention is that, in a printing apparatus including a plurality of head control units, communication is performed between an image processing unit and a plurality of head control units without imposing a load on a main control unit.

  A printing apparatus for achieving the above object includes a plurality of head control units, an image processing unit, a main control unit, and switching means. The plurality of head control units have a function of controlling each of the plurality of print heads. The image processing unit has a function of communicating with a plurality of head control units via a general-purpose bus. The main control unit has a function of controlling the head control unit via the image processing unit and the general-purpose bus. The switching means includes a first mode in which the main control unit controls the head control unit via the image processing unit and the general-purpose bus, and an image processing unit via a general-purpose bus between the image processing unit and the plurality of head control units. A function of periodically switching between the second mode for controlling the communication of the received message.

  By having such a configuration, in the second mode, the main control unit is not required for communication between the image processing unit and the head control unit. Can be used for processing. Therefore, by adopting the configuration of the present invention, it is possible to contribute to the improvement of the throughput of the main control unit. In addition, a separate bus is not provided in order to communicate messages between the image processing unit and the plurality of head control units, but the usage method of the same bus is switched over time. Can be suppressed. Note that message communication between the image processing unit and the plurality of head control units is performed by one device of the image processing unit and the plurality of head control units, and at least one of the other devices. It means sending a message as a destination.

  Further, in the printing apparatus for achieving the above object, in the second mode, at least one of the plurality of data signal lines and the plurality of address signal lines of the general-purpose bus in the first mode. Each functions as a signal line that plays the following role. That is, at least one message signal line from which a signal indicating a message is output, a clock signal line from which a clock signal for synchronizing the transfer of a signal indicating a message is output, and a message transmission request from the head control unit A transmission request signal line to which a signal is output, the transmission request signal line corresponding to each of the plurality of head control units, and a transmission permission signal line to which a signal indicating transmission permission for the transmission request is output, the plurality Each of the head control units functions as a transmission permission signal line corresponding to each of the head control units.

  By switching the function of the signal line between the first mode and the second mode in this manner, message communication is performed between the image processing unit and each head control unit in the second mode as described later. Can be done without.

  Furthermore, in the printing apparatus for achieving the above object, in the second mode, when transmitting a message, the head controller first outputs a signal indicating a transmission request to the transmission request signal line corresponding to the head controller. When a signal indicating transmission permission is output to the transmission permission signal line corresponding to the head controller, a signal indicating a message is output to the message signal line. In the second mode, the image processing unit permits transmission corresponding to one head control unit at the same time among the one or more head control units that output a signal indicating a transmission request to the transmission request signal line. A signal indicating transmission permission is output to the signal line.

  As described above, the image processing unit arbitrates the general-purpose bus in the second mode, so that a message can be transmitted from each head control unit using the general-purpose bus without the intervention of the main control unit.

Furthermore, in the printing apparatus for achieving the above object, in the second mode, when the image processing unit transmits a message to the head control unit, it does not output a signal indicating transmission permission to any transmission permission signal line. A signal indicating a message is output to the message signal line.
In this case, the image processing unit can transmit the message without competing with other messages.

Further, in the printing apparatus for achieving the above object, the message may include a destination part and a message body part. In this case, a value indicating at least one of the image processing unit and the plurality of head control units as the destination may be set in the destination unit. Further, a value indicating the status of transfer of print data from the image processing unit to the head control unit may be set in the message body.
By notifying the message having such a configuration between the image processing unit and the plurality of head control units, the transfer status of the print data from the image processing unit to the head control unit is notified to another head control unit or image processing unit. Can be shared with.

  Note that the function of each unit recited in the claims is realized by hardware resources whose functions are specified by the configuration itself, hardware resources whose functions are specified by a program, or a combination thereof. The functions of these means and units are not limited to those realized by hardware resources that are physically independent of each other. Furthermore, the present invention is established as an invention of a program for controlling the printing apparatus as described above and an invention of a recording medium for recording the program. Of course, the recording medium for recording the program may be a magnetic recording medium, a magneto-optical recording medium, or any recording medium developed in the future.

FIG. 3 is a block diagram illustrating a configuration of a main controller, an image processing ASIC, and a plurality of head controllers included in the printer according to the embodiment of the invention. 4 is a timing chart showing switching between a first mode and a second mode. (3A) to (3C) are timing charts showing communication of messages concerning print data transfer. (4A) is a timing chart when a message is transmitted from the image processing ASIC, and (4B) is a timing chart when a message is transmitted from the head controller. (5A) is a diagram showing the data structure of the message, (5B) is a diagram showing the correspondence between the value set in the message destination part and the meaning, and (5C) is the correspondence between the value set in the message body part and the meaning The figure which shows a relationship. Timing chart when transmission requests from the head controller compete.

Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings. In addition, the same code | symbol is attached | subjected to the corresponding component in each figure, and the overlapping description is abbreviate | omitted.
1. 1. First embodiment 1-1. Configuration FIG. 1 is a block diagram showing the configuration of the main part of the invention of a printer (printing apparatus) according to an embodiment of the present invention. The printer according to the present embodiment is a large format printer including a plurality of print heads H0 to H3. Each of the print heads H0 to H3 is controlled by a head controller (functioning as a head controller) HC0 to HC3 corresponding to 1: 1. In the following description, the head controller HC is used when referring to any head controller among the head controllers HC0 to HC3 or when referring to all head controllers. The main controller (functioning as a main control unit) 10 includes a CPU, RAM, ROM (not shown), various circuits such as a communication interface circuit, and the like. The entire printer is controlled in cooperation with the circuit so that the printer functions as a printing device. For example, when image data to be printed is acquired from the outside, the main controller 10 causes the image processing ASIC (which functions as an image processing unit) 11 to generate print data based on the image data. The main controller 10 and the image processing ASIC 11 communicate with each other via the bus B1.

  The image processing ASIC 11 includes various circuits such as a CPU, a RAM, a ROM, an image processing circuit, and a communication interface circuit (not shown). The program stored in the ROM is executed by the CPU using the RAM, and the image processing circuit and the communication interface. Various processes relating mainly to image processing can be performed in cooperation with the circuit. For example, the image processing ASIC 11 performs resolution conversion processing, color conversion processing, halftone processing, and the like on the image data to be printed while using the image buffer 12 to generate print data in a format to be transferred to each head controller HC. To do. The generated print data is stored in the image buffer 12. The image processing ASIC 11 and the image buffer 12 communicate with each other via the bus B2.

  The image processing ASIC 11 generates print data in band units, and sequentially transfers the print data of the portion of the generated print data, in which the print head is responsible for dot formation, from the image buffer 12 to the head controller corresponding to the print head. . The image processing ASIC 11 and each head controller HC can communicate via two types of buses B3 and B4. The print data is transferred to each head controller HC via the print data transfer bus B4. The bus B4 is a bus capable of transferring data at a higher speed than the bus B3, and is responsible for transferring a large amount of print data. The image processing ASIC 11 can transfer print data without the main controller 10 when transferring the print data from the image processing ASIC 11 to the head controller HC via the bus B4.

  Each head controller HC includes a CPU, a RAM, a ROM, an image processing circuit, a communication interface circuit, and the like (not shown). The program stored in the ROM is executed by the CPU using the RAM and cooperates with the image processing circuit and the communication interface circuit. To control the corresponding head. Specifically, each head controller HC performs processing such as rearrangement processing on the print data transferred from the image processing ASIC 11, and causes the corresponding print head to eject ink based on the processed data. The drive signal is output to the print head in synchronization with a predetermined synchronization signal.

  Each of the print heads H0 to H3 ejects ink droplets from the nozzles in accordance with a drive signal output from the corresponding head controller HC, thereby forming an image on the print medium. The ejection timing needs to be synchronized in a plurality of print heads, and in order to do so, the timing of outputting the drive signal from each head controller HC to the corresponding print head needs to be synchronized. For this purpose, it is necessary that each head controller HC can output a drive signal at the timing. In order to be able to output a drive signal, it is necessary to complete transfer of print data from the image processing ASIC 11 to each head controller HC. Therefore, it is desirable that the status such as whether or not the transfer of print data from the image processing ASIC 11 to each head controller HC is completed can be shared between the image processing ASIC 11 and each head controller HC.

  In this embodiment, the bus B3 as a “general-purpose bus”, which is another bus existing between the image processing ASIC 11 and each head controller HC, is used in two types of modes, the first mode and the second mode. Is done. In the first mode, the main controller 10 is used for transmitting various commands for controlling each head controller HC via the image processing ASIC 11. In the second mode, it is used for message communication between the image processing ASIC 11 and the head controller HC. The message means data for notifying the transfer status of print data as described above.

  The bus B3 is configured by a signal line conforming to the asynchronous SRAM interface specification. Specifically, the bus B3 includes eight address signal lines (A [7: 0]), eight data signal lines (D [7: 0]), and four chip select signal lines (CS0 #). , CS1 #, CS2 #, CS3 #), a write enable signal line (WE #), and an output enable signal line (OE #). The eight address signal lines (A [7: 0]) and the eight data signal lines (D [7: 0]) are illustrated as one line, but each of them is composed of eight signal lines. Composed. The image processing ASIC 11 includes eight address signal lines (A [7: 0]), eight data signal lines (D [7: 0]), and four chip select signal lines (CS0 #, CS1 #). , CS2 #, CS3 #), a write enable signal line (WE #), and an output enable signal line (OE #).

  The head controller HC0 includes eight address signal lines (A [7: 0]), eight data signal lines (D [7: 0]), a chip select signal line (CS0 #), and a write enable signal. The line (WE #) is connected to the output enable signal line (OE #). The head controller HC1 includes eight address signal lines (A [7: 0]), eight data signal lines (D [7: 0]), a chip select signal line (CS1 #), and a write enable signal. The line (WE #) is connected to the output enable signal line (OE #). The head controller HC2 includes eight address signal lines (A [7: 0]), eight data signal lines (D [7: 0]), a chip select signal line (CS2 #), and a write enable signal. The line (WE #) is connected to the output enable signal line (OE #). The head controller HC3 includes eight address signal lines (A [7: 0]), eight data signal lines (D [7: 0]), a chip select signal line (CS3 #), and a write enable signal. The line (WE #) is connected to the output enable signal line (OE #).

  For the printer immediately after the printer is turned on, only the first mode is enabled. When the main controller 10 instructs the image processing ASIC 11 to transition to a state in which the first mode and the second mode are switched, the image processing ASIC performs communication processing corresponding to each of the first mode and the second mode. Can be executed. When the main controller 10 transmits a command for enabling the second mode to each head controller via the image processing ASIC 11 and the bus B3, each head controller HC detects the switching between the first mode and the second mode and switches to the mode. Transition to a state in which the corresponding communication process is performed.

  FIG. 2 is a timing chart in the bus B3 indicating that the first mode and the second mode are periodically switched. During the first mode, the bus B3 performs communication according to the communication specification of the asynchronous SRAM interface. For example, in FIG. 2, the image processing ASIC 11 outputs a signal indicating an address to the address signal line (A [7: 0]) in response to an instruction from the main controller 10 during the first mode, and the chip select signal line (CS0 #). ) And the write enable signal line (WE #) are asserted, and a signal indicating the command C1 is transmitted to the data signal line (D [7: 0]). FIG. 2 also shows an example in which the command C2 is similarly sent. The head controller HC0 can receive the command C1 transferred in this way in the first mode and execute processing according to the command C1. Further, the head controller HC0 can receive the command C2 transferred in the first mode and execute processing according to the command C2.

  The length t1 of the period during which the first mode is continued is determined in advance. In the first mode, as described above, the main controller 10 transmits a command to the head controller HC via the image processing ASIC 11. The period t1 corresponds to the time required for transmitting a command once, for example. In the first mode, as described above, the image processing ASIC 11 executes communication processing in the image processing ASIC 11 corresponding to the first mode in which a command is transmitted to the head controller HC in response to an instruction from the main controller 10. In the first mode, as described above, when the head controller HC transmits a command, the head controller corresponding to the first mode receives the transmitted command and executes the process according to the command. Executed. When the time t1 elapses from the start of the first mode period, the main controller 10 and the image processing ASIC 11 determine that it is the switching timing from the first mode to the second mode, and the image processing ASIC 11 The signal line (WE #) and the output enable signal line (OE #) are once asserted and then negated (see the dotted line 102 in FIG. 2). Each head controller HC detects that WE # and OE # have changed from L to H as indicated by the dotted line 102 in FIG. 2, and the chip select signal line (CSn #) corresponding to itself is negated. If it is confirmed that the second mode has been switched, communication processing in the head controller HC corresponding to the second mode (communication between the image processing ASIC 11 and the head controller HC without interposing the main controller 11 is performed. Execute). In the second mode, the main controller 10 performs another process without communicating with the head controller HC. In the second mode, the image processing ASIC 11 executes communication processing (communication between the image processing ASIC 11 and the head controller HC without the main controller 10) in the image processing ASIC 11 corresponding to the second mode.

  By the way, in the second mode period, the address signal line of bus B3 (A [7: 0] in a period surrounded by a dotted line 100 in FIG. 2) and a data signal line (D in a period surrounded by a dotted line 101 in FIG. 2). [7: 0]) is assigned a function different from the function of the signal line in the first mode. Specifically, as shown in FIG. 4, D [0] of the eight data signal lines (D [7: 0]) functions as a transmission request signal line (REQ0 #) corresponding to the head controller HC0. Further, D [1] functions as a transmission request signal line (REQ1 #) corresponding to the head controller HC1. Further, D [2] functions as a transmission request signal line (REQ2 #) corresponding to the head controller HC2. Further, D [3] functions as a transmission request signal line (REQ3 #) corresponding to the head controller HC3. Of the eight address signal lines (A [7: 0]), A [0] functions as a transmission permission signal line (GNT0 #) corresponding to the head controller HC0. A [1] functions as a transmission permission signal line (GNT1 #) corresponding to the head controller HC1. A [2] functions as a transmission permission signal line (GNT2 #) corresponding to the head controller HC2. A [3] functions as a transmission permission signal line (GNT3 #) corresponding to the head controller HC3. In addition, A [7] of the eight address signal lines A [7: 0] functions as a clock signal line (SCLK), and D [7 of the eight data signal lines D [7: 0]. ] Functions as a message signal line (SDATA) for transmitting a message.

  The timing at which each head controller switches back to the first mode when REQn # of all head controllers HC is H after a lapse of a certain period (for example, 16 SCLK) after determining that the mode has switched to the second mode. Judge. If it is determined that it is time to switch from the second mode to the first mode, each head controller HC executes communication processing in the head controller HC corresponding to the first mode. A signal indicating a transmission request on the transmission request signal line (REQn #) before a certain period of time (for example, 16 SCLK) has elapsed since the head controller HC that desires to transmit a message detects that the mode has switched from the first mode to the second mode. Is preliminarily programmed as a communication process in the head controller corresponding to the second mode. In addition, when it is desired to transmit a message also in the image processing ASIC 11, communication in the image processing ASIC 11 corresponding to the second mode is performed so that the message is transmitted before a predetermined period (for example, 16 SCLK) elapses after switching to the second mode. It is programmed in advance as a process. Further, since the image processing ASIC 11 has switched to the second mode, when the transmission of the messages of all the head controllers HC and the image processing ASIC 11 itself is completed and the REQn # of all the head controllers HC becomes H (note that In the second mode, there may be cases where no message is transmitted), and it is determined that the second mode has ended (it is the switching timing from the second mode to the first mode), and corresponds to the first mode. Switch to communication processing. In this way, the second mode is not a fixed period, and when the number of messages to be transmitted is small, the period of the second mode can be shortened, and as a result, the first mode can be shifted quickly. Further, the maximum period t2 of the second mode is determined in advance so that the transition to the first mode is not too late. Each head controller HC negates REQn # from L to H after the elapse of t2 even during transmission request. Then, the head controller HC requests transmission again in the next second mode.

  The main controller 10 is also synchronized with the mode switching determination of the image processing ASIC 11, and is programmed in advance to communicate during the first mode when communicating with the head controller HC. In principle, the main controller 10 does not communicate with the head controller HC only in the first mode. However, in an exceptional case, when trying to communicate with the head controller HC during the second mode period, the main controller 10 sends the image processing ASIC 11 with the information. Can wait for communication. The image processing ASIC 11 performs the communication after the mode is switched to the first mode again when the main controller 10 is kept waiting during the second mode period. In this way, the main controller 10, the image processing ASIC 11, and each head controller HC determine the mode switching, and during the period of each mode, communication processing corresponding to the mode is executed. Therefore, the main controller 10, the image processing ASIC 11, and each head controller HC also function as “switching means”.

  In the first mode, the eight terminals of the image processing ASIC 11 connected to the address signal lines (A [7: 0]) are used as terminals for outputting signals from the image processing ASIC 11 to each head controller HC. A terminal connected to the address signal line (A [7: 0]) in the head controller is used as a terminal for inputting a signal. Therefore, even in the second mode, the transmission enable signal lines (GNT0 # to GNT3 #) are used so that the address signal lines (A [7: 0]) can be used as output terminals in the image processing ASIC 11 and input terminals in the head controller. ) And the clock signal line (SCLK) are assigned to any one of the address signal lines (A [7: 0]). Note that the image processing ASIC 11 generates and outputs the clock signal output to the clock signal line (SCLK) in the second mode.

  In the first mode, the eight terminals of the image processing ASIC 11 connected to the data signal lines (D [7: 0]) are used as input / output terminals, and the head controller uses the data signal lines (D [7: 0]). ) Is also used as an input / output terminal. For this reason, in the second mode, the data signal lines (D [7: 0]) are sent to the transmission request signal lines (REQ0 # to REQ3 #) to which the image processing ASIC 11 inputs the signal output from the head controller side, or the image processing. A message signal line (SDATA) through which signals are input / output by the ASIC 11 and the head controller HC is assigned.

  The terminal of the image processing ASIC 11 connected to the address signal line (A [7: 0]) and the terminal of the head controller HC connected to the address signal line (A [7: 0]) are set as input / output terminals. In the second mode, which of the address signal lines (A [7: 0]) and the data signal lines (D [7: 0]) is a transmission request signal line, a transmission permission signal line, or a clock signal It may be assigned to a line or a message signal line.

1-2. Transfer of Print Data from Image Processing ASIC to Each Head Controller FIG. 3 is a timing chart showing an example of a message transmitted at the time of transfer of print data from the image processing ASIC 11 to each head controller HC. First, the flow of print data transfer will be described with reference to FIG. 3A. First, when the image processing ASIC 11 completes preparation of print data to be transferred to the head controller, the image processing ASIC 11 transfers the message M1 in the second mode period. In the present embodiment, the message is composed of an 8-bit value as shown in FIG. 5A. More specifically, the message is composed of a 4-bit destination part and a 4-bit message body part. The association between the value set in the destination portion and the meaning indicated by the value is shared in advance between the image processing ASIC 11 and each head controller HC as shown in FIG. 5B, for example. A value indicating unicast with each head controller HC and image processing ASIC 11 as an individual destination, and a value indicating broadcast with each head controller HC and image processing ASIC as destinations are determined in advance. Further, as shown in FIG. 5C, the common correspondence between the image processing ASIC 11 and each head controller HC is also determined in advance for the value and meaning of the message body.

  Returning to the description of FIG. The message M1 in which the value “1111” meaning “broadcast” is set in the destination part and the value “1000” meaning “the image processing ASIC 11 has completed the preparation of print data” is set in the message body part is the bus B3. D [7], i.e., the message signal line SDATA in the second mode, each head controller HC receives the message M1 and transitions to a state of waiting for transfer of print data. More specifically, each head controller HC receives the message M1 and specifies that itself is included in the destination because the destination part is broadcast, and by specifying the meaning indicated by the value of the message body part, Transition to a state of waiting for transfer of print data. When the image processing ASIC 11 transmits a message, as shown in FIG. 4A, even if the transmission request signal line (REQn #) of any head controller HC is asserted, which transmission permission is not given. While the signal lines (GNT0 # to GNT3 #) are also negated, a message is sent to the message signal line (SDATA) in synchronization with the clock signal generated and output to the clock signal line (SCLK).

  When the image processing ASIC 11 finishes transferring the print data PD1 to the head controller HC0 via the bus B4, the head controller HC0 sets a value indicating “broadcast” in the destination part in the second mode period, A message M2 set with a value “0000” indicating that “HC0 has received the print data” is sent to SDATA. Since it is broadcast, the image processing ASIC 11 and other head controllers HC1, HC2, and HC3 can also recognize that the head controller HC0 has completed receiving print data.

  FIG. 4B shows a timing chart when the head controller HC0 transmits the message M2. First, the head controller HC0 asserts a transmission request signal line (REQ0 #) corresponding to itself to indicate a transmission request. During the second mode period, the image processing ASIC 11 has asserted one or more transmission request signal lines among the transmission request signal lines (REQ0 #, REQ1 #, REQ2 #, REQ3 #) (a signal indicating a transmission request). When the transmission request signal line is detected, the transmission permission signal line corresponding to one head controller is asserted at the same time among the one or more head controllers asserting the transmission request signal line, and the transmission of the message is permitted. Yes (gives the right to send messages) In FIG. 4B, since only the transmission request signal line (REQ0 #) corresponding to the head controller HC0 is asserted at the same time, the image processing ASIC 11 sets the transmission permission signal line (GNT0 #) corresponding to the head controller HC0. Assert (output a signal indicating transmission permission). When the transmission permission signal line corresponding to the head controller HC that has issued the transmission request is asserted, the head controller HC transmits an 8-bit message to the message signal line (SDATA) in synchronization with the clock signal. That is, in the case of FIG. 4B, the head controller HC0 sends the message M2 to SDATA in synchronization with SCLK.

  If the head controller HC0 and the head controller HC2 assert the transmission request signal line at the same time in the second mode as shown in FIG. 6, as described above, the image processing ASIC 11 does not Give permission to send. In the case of FIG. 6, it is shown that transmission permission is given to the head controller HC0. As a result, the message M20 from the head controller HC0 is sent to the message signal line SDATA first. A predetermined period after asserting the transmission permission signal line of the head controller HC0 (after the image processing ASIC 11 determines that the time required for message transmission has elapsed since the message size is determined to be 8 bits in this embodiment) In addition, the image processing ASIC 11 asserts the transmission permission signal line (GNT2 #) corresponding to the head controller HC2 that has issued the transmission request, and permits the transmission of the message. In this way, the image processing ASIC 11 performs arbitration in the second mode.

  Returning to the description of FIG. When the image processing ASIC 11 recognizes from the message M2 that the transfer of the print data PD1 to the head controller HC0 has been completed, the image processing ASIC 11 also transfers the print data to other head controllers. For example, when the next generated print data is print data PD2 for transfer to the head controller HC2 corresponding to the head H2, the image processing ASIC 11 transmits the print data PD2 to the head controller HC2 via the bus B4. When the head controller HC2 completes the reception of the print data PD2, in the second mode period, a value indicating “broadcast” is set in the destination part, and a value indicating “the head controller HC2 has received the print data” in the message body part A message M3 in which “0010” is set is transmitted.

  When the image processing ASIC 11 recognizes that the transfer of the print data PD2 to the head controller HC2 is completed by the message M3, the image processing ASIC 11 also transfers the print data to the remaining head controllers. For example, when the print data generated by the image processing ASIC 11 next is print data PD3 for transfer to the head controller HC1 corresponding to the head H1, the image processing ASIC 11 sends the print data PD3 to the head controller HC1 via the bus B4. Send. When the head controller HC1 completes the reception of the print data PD3, the value indicating “broadcast” is set in the destination part in the second mode, and the value “indicating that the head controller HC1 has received the print data” is set in the message body part. The message M4 in which “0001” is set is transmitted.

  When the image processing ASIC 11 recognizes from the message M4 that the transfer of the print data PD2 to the head controller HC1 is completed, the image processing ASIC 11 also transfers the print data to the remaining head controllers. The image processing ASIC 11 transmits the print data PD4 to the remaining head controller HC3 via the bus B4. When the head controller HC3 completes the reception of the print data PD4, a value indicating “broadcast” is set in the destination portion, and a value “0011” indicating that “the head controller HC3 has received the print data” is set in the message body portion. The transmitted message M5 is transmitted in the second mode period. As described above, the image processing ASIC 11 and each head controller HC transmit the messages M1 to M5 in the second mode, thereby confirming that each head controller HC has received the print data without intervention of the main controller 10. be able to.

  FIG. 3B shows a timing chart when an error occurs when print data is transferred from the image processing ASIC 11 to each head controller HC. In FIG. 3B, messages M6, M7, M8, and M9 are the same as messages M1, M2, M3, and M4 in FIG. When an error occurs while the image processing ASIC 11 is transferring the print data PD8 and the head controller HC3 cannot complete the reception of the print data PD8, the head controller HC3 sets a value indicating “broadcast” in the destination part and the message body A message M10 in which a value “0111” indicating that “the head controller HC3 has not received the print data” has been set is transmitted to the part. If it is determined that reception of the print data PD8 could not be completed during the first mode period, the head controller HC3 transmits a message M10 after switching to the second mode period. As a result, the image processing ASIC 11 and each head controller HC can share the fact that the head controller HC3 has not received the print data.

  If the head controller cannot receive the print data, a drive signal cannot be output to the corresponding print head, so a retry of print data transfer is necessary. Therefore, the configuration of the present embodiment that can share the situation regarding the transfer of print data between the image processing ASIC 11 and each head controller HC is effective. Furthermore, according to the present embodiment, during the second mode period, since message communication can be performed between the image processing ASIC 11 and the head controller HC without the intervention of the main controller 10, it is not necessary to apply a load to the main controller 10. As a result, a decrease in the throughput of the main controller 10 can be prevented. Further, since there is no need to intervene the main controller 10 in the communication between the image processing ASIC 11 and each head controller HC, message communication is promptly performed without being affected by the interrupt response time or interrupt priority in the main controller 10. It can be performed. Although not shown in FIG. 3, when the main controller 10 needs to communicate with the head controller HC, communication is performed in the first mode period. Since the function of the signal line of the bus B3 is switched between the first mode and the second mode, each head controller HC can accept access from the main controller 10 in the first mode.

  Note that the transfer time of the print data PDn is shown in FIG. 3 by the length of one period of the second mode and one period of the first mode, but this is only an example. . 2 and 3, the period of the first mode and the period of the second mode are illustrated to the same extent, but this is only an example, and the bus transfer speed, the processing of the image processing ASIC 11 and the head controller HC This is an item that is appropriately designed according to the speed, the control frequency of the head controller HC by the main controller 10, the time required for the control, and the like.

  In the example of FIGS. 3A and 3B described above, the destination of each message is broadcast. However, the print data may be transmitted to each head controller HC by transmitting a unicast message. This will be specifically described with reference to FIG. 3C. When the preparation of the print data to be transferred to each head controller HC is completed, the image processing ASIC 11 first sets a value “0000” indicating “head controller HC0” in the destination portion, and “image processing ASIC 11 prints the print data in the message body”. A message M11 set with a value “1000” indicating that “preparation is completed” is transmitted in the second mode period. The head controller HC0 that has received the message M11 prepares to receive print data via the bus B4.

  Subsequently, the image processing ASIC 11 transmits the print data PD9 to the head controller HC0. When the head controller HC0 completes the reception of the print data PD9, the value “0001” indicating “head controller HC1” is set in the destination portion, and the message body portion. A message M12 in which a value “1001” indicating “print data transfer start” is set is transmitted during the second mode period. In response to the message M12, the head controller HC1 prepares to receive print data via the bus B4. The image processing ASIC 11 transmits the print data PD10 to the head controller HC1 after a predetermined time has elapsed since the transmission of the print data PD9 to the head controller HC0 via the bus B4.

  When the head controller HC1 completes reception of the print data PD10, a value “0010” indicating “head controller HC2” is set in the destination portion, and a value “1001” indicating “print data transfer start” is set in the message body portion. Message M13 is transmitted during the second mode period. The head controller HC2 receives the message M13 and prepares to receive print data via the bus B4. The image processing ASIC 11 transmits the print data PD11 to the head controller HC2 after a predetermined time has elapsed since the transmission of the print data PD10 to the head controller HC1 via the bus B4.

  When the head controller HC2 completes reception of the print data PD10, the value “0011” indicating “head controller HC3” is set in the destination portion, and the value “1001” indicating “print data transfer start” is set in the message body portion. Message M14 is transmitted during the second mode period. The head controller HC3 receives the message M14 and prepares to receive print data via the bus B4. The image processing ASIC 11 transmits the print data PD12 to the head controller HC3 after a predetermined time has elapsed after the transmission of the print data PD11 to the head controller HC2 via the bus B4.

  When the head controller HC3 completes reception of the print data PD12, a value “1000” indicating “image processing ASIC11” is set in the destination portion, and a value indicating that “head controller HC3 has received the print data” in the message body portion. A message M15 in which “0011” is set is transmitted during the second mode period. Heretofore, an example has been described in which a message indicating the start of print data transfer is sequentially notified by unicast.

2. Other Embodiments The technical scope of the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the present invention. For example, in the above-described embodiment, an example in which a value indicating unicast or broadcast is determined in advance as a value set in the message destination part has been described. It may be included. For example, in the message M12 of FIG. 3C, a value indicating that the image processing ASIC 11 and the head controller HC1 are the destination may be set in the destination portion.

In the above embodiment, an example in which the message is transmitted serially in the second mode has been described. However, in the second mode, two or more signal lines may be assigned to the message signal line, and in that case the message is transmitted. May be transmitted in parallel using the two or more signal lines.
In the above embodiment, the printer is described as an example of the printing apparatus. However, the present invention can be applied to an apparatus having an image reading function, a facsimile function, and the like in addition to the printing function.

  The configuration for switching between the first mode and the second mode described in the above embodiment is merely an example, and the present invention is not limited to this. For example, in the above embodiment, the configuration in which WE # and OE # are once asserted and negated immediately after switching from the first mode to the second mode has been described, but the present invention is not limited to this. For example, when switching from the first mode to the second mode, WE # and OE # need not be asserted and negated immediately after that. In this case, WE #, OE #, and CSn # are asserted only when the main controller 10 communicates with the head controller HC via the image processing ASIC 11 in the first mode. Therefore, each head controller HC always monitors WE #, OE #, and CSn #, and when it detects that WE #, OE #, and CSn # are H, it judges that it has switched from the first mode to the second mode. May be.

  10: main controller, 11: image processing ASIC, 12: image buffer, B1: bus, B2: bus, B3: bus, B4: bus, H0 to H3: print head, HC0 to HC3 (HC): head controller

Claims (5)

A plurality of head controllers for controlling each of the plurality of print heads;
An image processing unit communicating with the plurality of head control units via a general-purpose bus;
A main control unit for controlling the head control unit via the image processing unit and the general-purpose bus;
A first mode in which the main control unit controls the head control unit via the image processing unit and the general-purpose bus; and the general-purpose unit between the image processing unit and the plurality of head control units. Switching means for periodically switching between the second mode for controlling communication of messages via the bus,
A printing apparatus comprising: In the second mode, at least one of a plurality of data signal lines and a plurality of address signal lines of the general-purpose bus in the first mode,
At least one message signal line from which a signal indicating the message is output;
A clock signal line for outputting a clock signal for synchronizing the transfer of the signal indicating the message;
A transmission request signal line from which a signal indicating a transmission request of the message from the head control unit is output and corresponding to each of the plurality of head control units, and
A transmission permission signal line to which a signal indicating transmission permission for the transmission request is output, the transmission permission signal line corresponding to each of the plurality of head controllers,
Function as one of the
The printing apparatus according to claim 1. In the second mode, when transmitting the message, the head controller first outputs a signal indicating the transmission request to the transmission request signal line corresponding to the head controller, and corresponds to the head controller. When a signal indicating transmission permission is output to the transmission permission signal line, a signal indicating the message is output to the message signal line,
In the second mode, the image processing unit outputs a signal indicating the transmission request to the transmission request signal line at one of the one or more head control units at the same time. Outputting a signal indicating the transmission permission to the corresponding transmission permission signal line;
The printing apparatus according to claim 2. In the second mode, when the image processing unit transmits the message to the head control unit, the message processing line does not output a signal indicating the transmission permission to any of the transmission permission signal lines. Output a signal indicating
The printing apparatus according to claim 2 or 3. The message includes a destination part and a message body part,
A value indicating at least one of the image processing unit and the plurality of head control units as a destination is set in the destination unit.
A value indicating the status of transfer of print data from the image processing unit to the head control unit is set in the message body.
The printing apparatus in any one of Claims 1-4.

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