JP2013161311A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the maximum peak power while suppressing the increase of a semiconductor integrated circuit.SOLUTION: In a semiconductor integrated circuit in which a plurality of real time function blocks whose processing should be completed within a predetermined time and a plurality of non-real time function blocks whose processing time is not specified are connected via an internal bus to each other, a non-real time function block 150 includes: a clock parameter generation part 152 for monitoring the operating state of the real time function block, and for generating a clock thinning-out parameter for performing the thinning-out processing of a system clock in accordance with the operating state; and a clock control part 153 for thinning out the system clock by a predetermined ratio in accordance with the value of the clock parameter generated by the clock parameter generation part.

Description

  The present invention relates to a system LSI technology that integrates a plurality of functional blocks that execute predetermined processing on a single semiconductor.

In general, in a system LSI in which a plurality of functional blocks are integrated on a single semiconductor, a plurality of real-time function blocks that require processing to be completed within a predetermined time period and a plurality of non-real-time functions that do not have a specified processing time The blocks are connected to each other by an internal bus, and a plurality of types of data processing are performed using these functional blocks.
In recent years, with the improvement of miniaturization technology of semiconductor integrated circuits, it has become possible to integrate a large number of functional blocks, and advanced functions of the semiconductor integrated circuits have progressed.
On the other hand, higher performance of semiconductor integrated circuits has caused a significant increase in maximum peak power and average power consumption. Further, in an embedded device driven by a battery, it is required to reduce power consumption in order to avoid a temperature rise problem of a semiconductor integrated circuit and to differentiate a product.
In order to solve such a problem, an operation mode change request is issued to each of a plurality of functional blocks, and each functional block is configured so that the total power consumption of the plurality of functional blocks does not exceed the limit power consumption of the semiconductor integrated circuit. There has been proposed a technique for reducing the power consumption of a semiconductor integrated circuit by controlling the clock frequency and bus occupancy time used in the above in response to an operation mode change request (see, for example, Patent Document 1).

Republished Japanese Patent Publication No. WO01 / 001228

  However, in the prior art, all functional blocks have a circuit for controlling power consumption, and there is a problem that the number of semiconductor integrated circuits increases.

  In order to solve the above-described conventional problems, an object of the present invention is to provide a technique for reducing the maximum peak power while suppressing an increase in the number of semiconductor integrated circuits.

  The present invention relates to a semiconductor integrated circuit in which a plurality of real-time functional blocks that need to complete processing within a predetermined time and a plurality of non-real-time functional blocks that do not have a processing time are interconnected by an internal bus. The non-real-time functional block monitors an operating state of the real-time functional block, and further generates a clock decimation parameter for performing a system clock decimation process according to the operating state; and the clock And a clock controller that thins out the system clock at a predetermined rate in accordance with the value of the clock parameter generated by the parameter generator.

According to the semiconductor integrated circuit of the present invention, the circuit for controlling the power consumption is provided only in the non-real-time function block for which the processing time is not specified, and the increase in the circuit for reducing the power consumption can be suppressed. . Further, since the clock control is not performed for the real-time function block, the maximum peak power in the semiconductor integrated circuit can be reduced without hindering the real-time property of the circuit. Furthermore, by reducing the maximum peak power, the temperature rise of the semiconductor can be suppressed, and an increase in the leakage current of the semiconductor that increases drastically with the temperature rise is also suppressed.
Thereby, for example, the LSI cost can be reduced by selecting a package having a lower heat tolerance, and if the LSI is a pad neck, the power supply terminals can be reduced, and the LSI cost can be reduced by reducing the die size.

It is a block diagram of one Example of a semiconductor integrated circuit. FIG. 2 is a block diagram of a real-time function block (R1 block) in the semiconductor integrated circuit of FIG. 2 is a block diagram of a functional block (N1 block) having a high priority in the non-real-time functional block in the semiconductor integrated circuit of FIG. 2 is a block diagram of a functional block (N2 block) having the lowest priority in the non-real-time functional block in the semiconductor integrated circuit of FIG. FIG. 5 is a block diagram of a clock parameter generation unit in the non-real-time function block (N2 block) having the lowest priority in FIG. 6 is a timing chart illustrating an operation example of the clock parameter generation unit in FIG. 5. 6 is a generation example of a clock decimation parameter in the clock parameter generation unit of FIG. FIG. 5 is a block diagram of a clock control unit in the non-real time functional block (N2 block) having the lowest priority in FIG. FIG. 9 is a timing chart illustrating an operation example of the clock control unit in FIG. 8. FIG. It shows the maximum peak power when the N1 block and N2 block, which are non-real-time functional blocks, are operating at the same frequency as the system clock CLK. It is a conceptual diagram of the maximum peak electric power reduction | restoration at the time of operating the N1 block and N2 block which are non-real-time functional blocks by carrying out frequency reduction.

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.
In FIG. 1, 10 is a semiconductor integrated circuit, 20 is an external power supply that supplies power to the semiconductor integrated circuit 10, and 30 is an oscillation circuit that supplies a clock to the semiconductor integrated circuit 10. Here, in the semiconductor integrated circuit 10, a plurality of functional blocks 110 to 150, a CPU 160, and a memory 170 are connected to each other via the internal bus 100, and each of the functional blocks 110 to 150, the CPU 160, and the memory 170 are connected from the power supply control circuit 180. A predetermined power is supplied, and a system clock CLK (T0) (not shown) is supplied from the clock generation circuit 190 to each of the functional blocks 110 to 150, the CPU 160, and the memory 170.

  The plurality of functional blocks 110 to 150 are an R1 block 110, an R2 block 120, and an R3 block 130 that are real-time functional blocks that need to complete processing within a predetermined time period, and an N1 block that is a non-real-time functional block with no processing time defined. 140 and N2 block 150. Further, the non-real-time functional block has processing priority. In this embodiment, the N1 block 140 has a higher priority than the N2 block 150, and the N2 block 150 is a functional block having the lowest priority among the non-real-time functional blocks. It is.

  As an example of the real-time function block, for example, in the case of a semiconductor integrated circuit of a digital camera, a sensor interface, H.264 or the like. H.264 codec and other functional blocks that must be synchronized with the input / output timing of the external circuit, and non-real-time functional blocks include functional blocks that may have different processing times, such as AE detection and white balance detection. .

Hereinafter, an embodiment of the present invention will be specifically described with reference to FIGS.
FIG. 2 is a block diagram of the R1 block 110, which is a real-time functional block. The R1 block 110 includes a logic circuit 111 that realizes a predetermined function.

  The logic circuit 111 receives input data processed by the logic circuit and a system clock CLK (T0) for driving the logic circuit from the clock generation circuit 190. The logic circuit 111 executes predetermined processing. Output the output data. In addition, an operation state signal R1 Act (T1) indicating whether or not the logic circuit 111 is processing is output. In this embodiment, R1 Act (T1) is a signal of 1 when the logic circuit 111 is operating and 0 when the logic circuit 111 is stopped. This operation state signal R1 Act (T1) is output to the N1 block 140 and the N2 block 150, which are non-real time functional blocks.

  The other real-time functional blocks, R2 block 120 and R3 block 130, have the same block configuration as R1 block 110.

  FIG. 3 is a block diagram of the N1 block 140, which is a functional block having a high priority in the non-real-time functional block. The N1 block 140 monitors the operation state of the logic circuit 141 that realizes a predetermined function and the R1 block 110, the R2 block 120, and the R3 block 130 that are real-time function blocks, and thins the system clock according to the operation state. A clock parameter generation unit 142 that generates a clock decimation parameter P1 (T12) for processing, and a system clock at a predetermined ratio according to the value of the clock decimation parameter P1 (T12) generated by the clock parameter generation unit 142 The thinning clock control unit 143 is configured.

  The logic circuit 141 receives input data processed by the logic circuit and an internal clock N1 CLK (T6) for driving the logic circuit. The logic circuit 141 outputs output data that has been subjected to predetermined processing. Output. Further, an operation state signal N1 Act (T4) indicating whether or not the logic circuit 141 is performing processing is output. In this embodiment, N1 Act (T4) is a signal of 1 when the logic circuit 141 is operating and 0 when the logic circuit 141 is stopped. The operation state signal N1 Act (T4) is output to the clock control unit 143 in the N1 block 140 and also to a non-real-time functional block having a lower priority than the N1 block 140. In this embodiment, the data is output to the N2 block 150.

  The clock parameter control unit 142 includes an operation state signal R1 Act (T1) of the R1 block 110, an operation state signal R2 Act (T2) of the R2 block 120, and an operation state signal R3 Act (R3 block 130) which are real-time functional blocks. T3) is input, and a clock decimation parameter P1 (T12) corresponding to each operation state signal is output to the clock controller 143.

  The clock control unit 143 includes a system clock CLK (T0) from the clock generation circuit 190, a clock thinning parameter P1 (T12) generated by the clock parameter generation unit 142, and an operation state signal N1 indicating the operation state of the logic circuit 141. Act (T4) is input, and the system clock CLK (T0) is thinned out at a predetermined rate or the system clock CLK (T0) according to the signal of the clock thinning parameter P1 (T12) and the operation state signal N1 Act (T4). ) Is supplied to the logic circuit 141 with the internal clock N1 CLK (T6) having the same frequency as that in FIG.

  FIG. 4 is a block diagram of the N2 block 150, which is the functional block having the lowest priority in the non-real-time functional block. The N2 block 150 monitors the operation state of the logic circuit 151 that realizes a predetermined function, the R1 block 110, the R2 block 120, the R3 block 130 that are real-time functional blocks, and the N1 block 140 that is a non-real-time functional block. Then, the clock parameter generation unit 152 that generates the clock decimation parameter P2 (T13) for performing the system clock decimation process according to the operating state, and the clock decimation parameter P2 (T13) generated by the clock parameter generation unit 152 And a clock control unit 153 that thins out the system clock at a predetermined rate according to the value of.

  The logic circuit 151 receives input data processed by the logic circuit and an internal clock N2 CLK (T7) for driving the logic circuit, and the logic circuit 151 outputs output data that has been subjected to predetermined processing. Output. In addition, an operation state signal N2 Act (T5) indicating whether or not the logic circuit 151 is performing processing is output. In this embodiment, N2 Act (T5) is 1 when the logic circuit 151 is in operation and 0 when it is stopped. The operation state signal N2 Act (T5) is output to the clock control unit 153 in the N2 block 150.

  The clock parameter control unit 152 includes an operation state signal R1 Act (T1) of the real time function block R1 block 110, an operation state signal R2 Act (T2) of the R2 block 120, an operation state signal R3 Act (T3) of the R3 block 130, and The operation state signal N1 Act (T4) of the non-real-time function block N1 block 140 is input, and the clock decimation parameter P2 (T13) corresponding to each operation state signal is output to the clock control unit 153.

  The clock control unit 153 includes a system clock CLK (T0) from the clock generation circuit 190, a clock thinning parameter P2 (T13) generated by the clock parameter generation unit 152, and an operation state signal N2 indicating the operation state of the logic circuit 151. Act (T5) is input, and the system clock CLK (T0) is thinned out at a predetermined rate or the system clock CLK (T0) according to the clock thinning parameter P2 (T13) and the operation state signal N2 Act (T5). ) Is supplied to the logic circuit 151 with the internal clock N2 CLK (T7) having the same frequency as that in FIG.

  FIG. 5 is a block diagram of the clock parameter generation unit 152 constituting the N2 block 150, which is a non-real time functional block. The clock parameter generation unit 152 includes multipliers 152A to 152D, adders 152E to 152G, and a lookup table 152H.

The multiplier 152A receives the operation state signal R1 Act (T1) of the R1 block 110 and the weighting coefficient C1 (T8) of the R1 block 110, which are real-time functional blocks, and the result of multiplying them is added to the adder 152E. Output.
The multiplier 152B receives the operation state signal R2 Act (T2) of the R2 block 120 and the weighting coefficient C2 (T9) of the R2 block 120, which are real-time functional blocks, and outputs the result of multiplying them to the adder 152E. To do.
The multiplier 152C receives the operation state signal R3 Act (T3) of the R3 block 130 and the weighting coefficient C3 (T10) of the R3 block 130, which are real-time functional blocks, and outputs the result of multiplying them to the adder 152F. To do.
The multiplier 152D receives the operation state signal N1 Act (T4) of the N1 block 140 and the weighting coefficient C4 (T11) of the N1 block 140, which are non-real-time function blocks, and multiplies the results to the adder 152G. Output.

The adder 152E receives the multiplication results of the multiplier 152A and the multiplier 152B, and outputs the addition result to the adder 152F.
The adder 152F receives the division result of the multiplier 152C and the addition result of the adder 152E, and outputs the addition result to the adder 152G.
The adder 152G receives the division result of the multiplier 152D and the addition result of the adder 152F, and outputs the addition result to the lookup table 152H.

  The look-up table 152H outputs the clock decimation parameter P2 (T13) to the clock control unit 153 according to the input value of the adder 152F.

  Although weighting coefficients C1 (T8) to C4 (T11) are not shown, CPU 160 sets predetermined values.

Next, an operation example and a generation example of the clock thinning parameter P2 (T13) in the clock parameter generation unit 152 will be described with reference to FIGS.
FIG. 6 is a timing chart showing an operation example of the clock parameter generation unit 152. Now, the weighting coefficients are set to C1 (T8) = 8, C2 (T9) = 4, C3 (T10) = 2, and C4 (T11) = 2, and the operation state signal R1 Act (T1) at the timing shown in FIG. , R2 Act (T2), R3 Act (T3), and N1 Act (T4) change, the value of the clock decimation parameter P2 (T13) becomes 1 → 16 → 8 → 4 → 2 → 1 at the timing shown in FIG. And change.

  In FIG. 7, as described above, the weighting coefficients are set to C1 (T8) = 8, C2 (T9) = 4, C3 (T10) = 2, C4 (T11) = 2, and the operation state signal R1 Act (T1). , R2 Act (T2), R3 Act (T3), and N1 Act (T4) are examples of generating the clock decimation parameter P2 (T13) generated by the lookup table 152H.

FIG. 8 is a block diagram of the clock control unit 153 constituting the N2 block 150, which is a non-real time functional block. The clock control unit 153 includes a logic circuit 153A such as a down counter, a comparator, an AND gate, and a flip-flop (FF). The clock control unit 153 includes the value of the clock thinning parameter P2 (T13) and the operation state signal N2 Act ( Depending on the state of T5), the system clock CLK (T0) is thinned out at a predetermined rate to generate the internal clock N2 CLK (T7).
Note that the configuration of the logic circuit 153A illustrated in the above embodiment is merely an example, and is not limited thereto.

  FIG. 9 is a timing chart showing an operation example of the clock control unit 153. As shown in FIG. 9, the system clock CLK (T0) is thinned out according to the value of the clock thinning parameter P2 (T13) and the state of the operation state signal N2 Act (T5) of the N2 block 150, and at each timing. It can be seen that the internal clock N2 CLK (T7) in which the system clock CLK (T0) is divided by ÷ 1, ÷ 16, ÷ 8, ÷ 4, ÷ 2, and ÷ 1 is generated.

  FIG. 10 is a diagram showing the maximum peak current when the N1 block 140 and the N2 block 150, which are non-real-time functional blocks, are operating at the same frequency as the system clock CLK.

FIG. 11 is a conceptual diagram of maximum peak power reduction when the N1 block 140 and the N2 block 150, which are non-real-time functional blocks, are operated with the system clock CLK being thinned out.
As shown in FIG. 11, although the processing time of the N1 block and the N2 block is long, it can be seen that the maximum peak power is reduced.

As described in the above embodiment, in the present invention, a plurality of real-time function blocks that need to complete processing within a predetermined time and a plurality of non-real-time function blocks that do not have a processing time are defined by an internal bus. In a semiconductor integrated circuit connected to each other, a clock parameter for monitoring the operating state of a real-time functional block only for a non-real-time functional block and generating a clock thinning parameter for performing a system clock thinning process according to the operating state By including a generation unit and a clock control unit that thins out the system clock at a predetermined rate according to the value of the clock parameter generated by the clock parameter generation unit, while suppressing an increase in circuit for power consumption reduction, Maximum peak power can be reduced.
In addition, since clock control is not performed for the real-time functional block, a semiconductor integrated circuit that reduces the maximum peak power in the semiconductor integrated circuit can be realized without hindering the real-time performance of the circuit.

The invention described in the claims of the present application will be added below.
[Claims]
[Claim 1]
In a semiconductor integrated circuit in which a plurality of real-time functional blocks that need to complete processing within a predetermined time and a plurality of non-real-time functional blocks that do not have a processing time are interconnected by an internal bus,
The non-real-time functional block monitors the operating state of the real-time functional block;
A clock parameter generation unit for generating a clock decimation parameter for performing a decimation process of the system clock according to the operation state;
A semiconductor integrated circuit comprising: a clock control unit that thins out a system clock at a predetermined rate in accordance with a value of a clock thinning parameter generated by the clock parameter generation unit.
[Claim 2]
The clock parameter generation unit monitors an operation state of the real-time function block and an operation state of a function block having a higher processing priority than itself among the non-real-time function blocks,
2. The semiconductor integrated circuit according to claim 1, further comprising: a clock thinning parameter for performing a thinning process of a system clock according to the operation state.
[Claim 3]
2. The semiconductor integrated circuit according to claim 1, wherein the clock parameter generation unit can set a weighting coefficient according to a processing priority of the real-time functional block and the non-real-time functional block.

10 Semiconductor Integrated Circuit 20 External Power Supply 30 Oscillation Circuit 100 Internal Bus 110 R1 Block (Real Time Function Block)
111 logic circuit 120 R2 block (real-time function block)
130 R3 block (real-time function block)
140 N1 blocks (non-real-time functional blocks with high priority)
141 Logic circuit 142 Clock parameter generation unit 143 Clock control unit 150 N2 block (non-real-time functional block with the lowest priority)
151 Logic Circuit 152 Clock Parameter Generation Unit 152A Multiplier 152B Multiplier 152C Multiplier 152D Multiplier 152E Adder 152F Adder 152G Adder 152H Lookup Table 153 Clock Control Unit 153A Logic Circuit 160 CPU
170 Memory 180 Power supply control circuit 190 Clock generation circuit T0 System clock CLK
T1 operation state signal R1 Act
T2 operation state signal R2 Act
T3 operation state signal R3 Act
T4 operation state signal N1 Act
T5 operation state signal N2 Act
T6 Internal clock N1 CLK
T7 Internal clock N2 CLK
T8 Weighting factor C1
T9 Weighting factor C2
T10 Weighting coefficient C3
T11 Weighting coefficient C4
T12 Clock decimation parameter P1
T13 Clock thinning parameter P2
T14 Down counter T15 Count value = 0
T16 Function block internal ENCLK

Claims (3)

In a semiconductor integrated circuit in which a plurality of real-time functional blocks that need to complete processing within a predetermined time and a plurality of non-real-time functional blocks that do not have a processing time are interconnected by an internal bus,
The non-real-time functional block monitors the operating state of the real-time functional block;
A clock parameter generation unit for generating a clock decimation parameter for performing a decimation process of the system clock according to the operation state;
A semiconductor integrated circuit comprising: a clock control unit that thins out a system clock at a predetermined rate in accordance with a value of a clock thinning parameter generated by the clock parameter generation unit. The clock parameter generation unit monitors an operation state of the real-time function block and an operation state of a function block having a higher processing priority than itself among the non-real-time function blocks,
2. The semiconductor integrated circuit according to claim 1, further comprising: a clock thinning parameter for performing a thinning process of a system clock according to the operation state.   2. The semiconductor integrated circuit according to claim 1, wherein the clock parameter generation unit can set a weighting coefficient according to a processing priority of the real-time functional block and the non-real-time functional block.

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