JP2013158210A - Power source and power failure detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a power failure state at an early stage and reduce power consumption of a device in a stand-by state.SOLUTION: A power source includes: rectification means which performs full-wave rectification of an input AC voltage; a first converter which converts the rectified voltage; a second converter connected to the first converter in parallel; zero cross detection means which detects zero cross of the AC voltage; voltage detection means which detects the AC voltage; a first capacity element connected between a line and ground after the full-wave rectification; a first discharge resistor which discharges an electrical charge charged in the first capacity element; first switch means which blocks a current flowing in the first discharge resistor; and stop means which causes the voltage detection means to detect the AC voltage using the current flowing in the first discharge resistor and stops an operation of the second converter when the detected voltage is smaller than a threshold. The power source also includes a first state in which the first switch means is in a block state and a second state in which the first switch means is in an energization state.

Description

  The present invention relates to a power source and a power failure detection device mounted in an image forming apparatus such as a copying machine, a printer, and a facsimile machine.

  When the AC voltage from the commercial AC power supply is not supplied to the device (also referred to as a power failure), when the AC voltage supply from the commercial AC power supply is cut off due to a power failure or the like, the supplied AC voltage is There is a case where the power cable is pulled out while the apparatus is operating by the user when the voltage is greatly reduced outside the specification range. It is desirable to stop the power supply circuit after detecting the power failure state and making a transition to a state where the apparatus can be stopped normally. In Patent Document 1, as a configuration for detecting this power failure state, a first converter (insulated DC / DC converter) and a second converter (insulated DC / DC converter) are connected in parallel to a full-wave rectifier circuit of a power supply. Then, a method has been proposed in which a power failure state is detected and the second converter is stopped, whereby voltage supply by the first converter is continued for a certain period of time and the apparatus is transitioned to a state where it can be stopped normally.

  By the way, as a fixing device that is mounted on a copying machine, a printer, a facsimile, or the like as an image forming apparatus and fixes an image on a recording material, an endless belt and a ceramic heater that contacts an inner surface of the endless belt (hereinafter referred to as a ceramic heater). ) And a pressure roller that forms a nip portion with a ceramic heater via an endless belt is known. As a means for controlling the power supplied to the fixing device, a method is used in which the power supplied from a commercial AC power source is phase-controlled using a switching element such as a triac. In the phase control of the supplied AC voltage waveform, it is necessary to accurately detect a timing at which the AC voltage becomes 0 V, that is, a so-called zero-cross timing (hereinafter referred to as zero-cross) as a reference timing for phase control. Patent Document 2 discloses a circuit for detecting zero-cross timing.

Patent No. 4080764 JP 2003-199343 A

  Among the above power outage states, when the power supply cable of the device is pulled out by the user, when detecting the power outage state by detecting the AC voltage, the charge charged in the X capacitor, which is provided as a noise countermeasure for the power source As a result, the drop in the voltage of the power supply circuit is delayed, and it may take time to detect the power failure. This delay can be improved by reducing the resistance value of the resistor that discharges the X capacitor. However, on the other hand, there is an increasing demand for reducing the power in the standby state where the apparatus is not operating, and it is also necessary to reduce or suppress the power consumption of the circuit that detects the power failure state. That is, it is required to detect a power outage state early and to reduce power consumption during standby of the apparatus.

  In order to achieve the above goal, the power supply of the present invention includes a rectifier that full-wave rectifies an input AC voltage, a first converter that converts the voltage rectified by the rectifier, and a parallel to the first converter. Connected between the connected second converter, zero-cross detection means for detecting the zero-cross of the AC voltage, voltage detection means for detecting the AC voltage, and the potential after full-wave rectification by the rectification means and the ground The first capacitor element, the first discharge resistor for discharging the charge charged in the first capacitor element, the first switch means for cutting off the current flowing through the discharge resistor, and the voltage detecting means, Detecting the AC voltage using a current flowing through the first discharge resistor, and stopping the operation of the second converter when the detected voltage is smaller than a threshold value. And having a first state in which said first switch means to the cut-off state, a second state in which said first switch means to the conductive state, a.

  The power failure detection device of the present invention includes a first converter that converts a voltage after full-wave rectification of an input AC voltage, a second converter connected in parallel to the first converter, and the AC voltage A zero cross detecting means for detecting a zero cross; and a voltage detecting means for detecting the value of the AC voltage. When the voltage detected by the voltage detecting means is lower than a threshold value, the operation of the second converter is stopped. When the stop means and the zero cross detection means fail to detect the zero cross for a predetermined time or more, the first power failure detection means for judging a power failure state, and the voltage detected by the voltage detection means is more than a threshold value. It has the 2nd power failure detection means which judges that it is a power failure state, when low.

  According to the present invention, a power failure state can be detected at an early stage, and power consumption in a standby state of the apparatus can be reduced.

1 is a schematic diagram of an image forming apparatus. FIG. 3 is a power supply circuit diagram according to the first embodiment. FIG. 3 is a diagram illustrating a zero-cross detection unit according to the first embodiment. Explanatory drawing of the power failure detection operation | movement of Example 1. FIG. Explanatory drawing of the power failure detection operation | movement of Example 1. FIG. Explanatory drawing of the power failure detection operation | movement of Example 1. FIG. Explanatory drawing of the power failure detection operation | movement of Example 1. FIG. 5 is a follow chart showing a control sequence of the power supply circuit according to the first embodiment. FIG. 6 is an explanatory diagram of a power supply circuit according to the second embodiment.

  Next, specific configurations of the present invention for solving the above-described problems will be described based on examples. In addition, the Example shown below is an example, Comprising: It is not the meaning which limits the technical scope of this invention only to them.

(Description of apparatus configuration example to which the present invention is applied)
FIG. 1 is a cross-sectional view of an electrophotographic image forming apparatus as an example of an apparatus to which the present invention is applied. Recording sheets as recording media loaded on the paper feed cassette 11 are sent one by one from the paper feed cassette 11 by the pickup roller 12 and conveyed toward the registration roller 14 by the paper feed roller 13. The recording paper is conveyed to the image forming unit by the registration roller 14 at a predetermined timing. A process cartridge 15 as an image forming unit integrally includes a charging roller 16 as a charging unit, a developing roller 17 as a developing unit, a cleaner 18 as a cleaning unit, and a photosensitive drum 19 on which a toner image is formed. It can be attached to and detached from the image forming apparatus. In the electrophotographic image forming operation, first, the surface of the photosensitive drum 19 is uniformly charged by the charging roller 16, and then the photosensitive drum 19 is exposed based on the image signal by the scanner unit 21 as an exposure unit. . Laser light emitted from the laser diode 22 in the scanner unit 21 is scanned in the main scanning direction through the rotating polygon mirror 23 and the reflecting mirror 24, and in the sub-scanning direction by the rotation of the photosensitive drum 19. A latent image is formed on top. The latent image on the photosensitive drum 19 is visualized as a toner image on the photosensitive drum 19 by supplying toner by the developing roller 17. The toner image on the photosensitive drum 19 is transferred onto the recording paper conveyed from the registration roller 14 by the transfer roller 20. Subsequently, when the recording paper on which the toner image has been transferred is conveyed to the heating device 100, the recording paper is heated and pressurized, and the toner image transferred onto the recording paper is fixed on the recording paper. The recording paper is further discharged out of the image forming apparatus by the intermediate paper discharge roller 26 and the paper discharge roller 27, and a series of image forming operations is completed. Although the operation of the fixing unit 100 will be described later, based on the zero-cross timing of the AC voltage from the commercial AC power supply, the power to be input is controlled by phase control or a control method over a plurality of cycles including a phase control waveform. Control is taking place. Reference numeral 200 denotes a power supply circuit used in the image forming apparatus. The AC voltage supplied from the external power supply unit 40 as a commercial power supply is supplied to the power supply circuit 200 via the power cable 50.

  FIG. 2 shows a power supply circuit 200 according to the first embodiment. The external power supply unit 40 includes a ground point GND to the ground potential and an AC power supply 201. The AC power supply 201 outputs an AC voltage between the LIVE line and the NEWTRAL line. In this embodiment, in the external power supply unit 40, the NEUTRAL line is grounded to GND. However, the effect of this embodiment is effective even when the LIVE line side is grounded to GND. Even in a state where the frame ground (hereinafter referred to as FG) of the image forming apparatus is not connected to GND (ground), the zero-cross detection accuracy described later can be satisfied. In the present embodiment, the external power supply unit 40 and the power supply circuit 200 are connected by three lines: a LIVE line, a NEWTRAL line, and a GND line. The FG of the image forming apparatus is connected to the GND line. The AC voltage supplied from the AC power supply 201 is full-wave rectified by the bridge diode circuit BD1, and smoothed by the primary smoothing capacitor C2. The low side potential of the primary smoothing capacitor C2 is DCL, and the high side potential is DCH. A first converter (converter 1) and a second converter (converter 2) are connected in parallel at the subsequent stage of the bridge diode circuit BD1 and the primary smoothing capacitor C2. The converter 1 is an insulation type DC / DC converter, which converts an input primary side DC voltage and outputs DC 5V (V5) to the output side secondary side. The converter 2 is an insulation type DC / DC converter, which converts an input primary-side DC voltage and outputs DC 24V (V24) to the output-side secondary side.

  In general, some power supply circuits have a capacitive element (hereinafter referred to as an X capacitor) provided between lines to which an AC voltage is supplied from a commercial AC power supply as a noise countermeasure. In FIG. 2, C1 is an X capacitor. In a power supply circuit using an X capacitor, when a user disconnects a power supply cable that supplies power to the power supply circuit, the X capacitor may be charged with an AC power supply. Since the user may touch the outlet terminal of the power cable when the power cable is pulled out, a discharge resistor (hereinafter referred to as the X capacitor discharge resistor) is required to discharge the charge charged in the X capacitor. become. The resistors R1 and R2 are X capacitor discharge resistors used for discharging the X capacitor C1. When the user pulls out the power cable 50 from the external power supply unit 40, the external power supply unit 40 and the three lines of LIVE, NEWTRAL, and GND of the power supply circuit are cut off. When the state of charge of the X capacitor C1 is positive (the potential on the LIVE side is higher than that of NEWTRAL), the charge is discharged via the X capacitor discharge resistor R1 and the bridge diode circuit BD1. On the other hand, when the charged state of the X capacitor C1 is negative (the potential on the LIVE side is lower than that of NEWTRAL), the charge is discharged through the X capacitor discharge resistor R2 and the diode bridge circuit BD1.

  Patent Document 1 discloses a zero cross detection circuit and a power supply circuit having a capacitance component between a potential (line) after full-wave rectification of an AC voltage and an FG (frame ground), such as terminal noise. As a countermeasure against noise, a capacitor called a Y capacitor is provided as a capacitive element between the potential after full-wave rectification and FG. In order to accurately detect the zero-cross timing, a resistor for discharging the Y capacitor (hereinafter referred to as a Y capacitor discharge resistor) is required. In FIG. 2, capacitors C3 and C4 are Y capacitors for noise countermeasures. Even when there is no Y capacitor C3 (when only the Y capacitor C4 is provided), as described below, the effect of the Y capacitor discharge resistance described in the present embodiment can be obtained. Similarly, even when there is no Y capacitor C4 (when only the Y capacitor C3 is provided), the effect of the Y capacitor discharge resistance described in this embodiment can be obtained. The resistors R3 and R4 are Y capacitor discharge resistors for discharging the Y capacitors C3 and C4. D1 and D2 are backflow prevention diodes. The effect of the Y capacitor discharge resistance will be described later with reference to FIG. As described above, in this embodiment, the Y capacitor as the first capacitor element, R3 and R4 as the first discharge resistor for discharging the Y capacitor, the X capacitor as the second capacitor element, and the X capacitor are discharged. This is a configuration in which R1 and R2 are provided as the second discharge resistance.

  Q1 is a high voltage transistor as a first switch element used to cut off the current flowing through the Y capacitor discharge resistor. In this embodiment, a high-breakdown-voltage bipolar transistor is used for Q1, but other switching elements such as FETs (field effect transistors) can also be used. The resistor R9 is a pull-up resistor for driving the transistor Q1, and the resistor R8 is a resistor for protecting the transistor Q1. Here, the X capacitor discharge resistors R1 and R2 are resistance elements that discharge the electric charge charged in the X capacitor when the user pulls out the power cable 50. The resistors R3 and R4 do not function as resistors for discharging the X capacitor when the transistor Q1 is OFF.

Incidentally, the X capacitor discharge resistors R1 and R2 also have a function of discharging the charges charged in the Y capacitors C3 and C4. However, since the resistance value is not sufficiently small with respect to the capacitances of the Y capacitors C3 and C4, the detection accuracy of the zero cross timing due to the time constant delay (described later in FIG. 3) is lowered. The Y capacitor discharge resistors R3 and R4 are characterized in that the resistance values of the X capacitor discharge resistors R1 and R2 are set to be smaller than at least the X capacitor discharge resistor R2 that supplies current to the zero cross detection circuit 202. . In the configuration of the first embodiment, the X capacitor discharge resistor R2 also functions as a zero cross detection resistor for detecting the zero cross timing, and also functions as a discharge function of the X capacitor. The condition of the resistance value is as follows.
-Resistance value of X capacitor discharge resistance (zero cross detection resistor) R2> Resistance value of Y capacitor discharge resistor R3-Resistance value of X capacitor discharge resistance (zero cross detection resistor) R2> Resistance value of Y capacitor discharge resistor R4 CPU 203 is a power supply device 200 and a control unit that controls the image forming apparatus of FIG. Details of the control by the CPU 203 will be described later with reference to the flowchart of FIG.

  In FIG. 2, Vcc is a voltage supplied from the auxiliary winding of the converter 1. The auxiliary winding voltage Vcc is supplied via the primary side transistor of the photocoupler PC2. In addition, when the supply capability of the primary side transistor of the photocoupler PC2 is insufficient, the auxiliary winding voltage Vcc may be output separately using a transistor or the like for output amplification. When a standby signal output from the CPU 203 (hereinafter referred to as “Standby signal”) is in a high state, Vcc is supplied, and Vcc is in a high state (a state in which an auxiliary winding voltage is output). When the Standby signal output from the CPU 203 is in the Low state, Vcc is not supplied and Vcc is in the Low state (the same potential as the reference potential DCL). The auxiliary winding voltage Vcc supplies power for driving a zero-cross detection unit 202, a converter 2, a transistor Q1 (first switch element), and a voltage detection unit 205, which will be described later.

  Next, the zero cross detection unit 202 will be described. When the potential of the NEUTRAL line supplied from the AC power supply 201 is higher than the potential of the LIVE line, a current flows through the zero-cross detection unit 202 via the X capacitor discharge resistor R2. When the current supplied from the X capacitor discharge resistor R2 flows to the base terminal of the transistor Q2 of the zero cross detector 202, the transistor Q2 is turned on. The resistor R5 and the capacitor C5 are circuits for adjusting the operation timing of the transistor Q2. When the transistor Q2 is turned on, the voltage applied to the primary side diode of the photocoupler PC1 is lowered, and the secondary side transistor of the photocoupler PC1 is turned off. When the secondary side transistor of the photocoupler PC1 is turned off, the voltage of the zero cross signal (hereinafter referred to as Zerox signal) rises through the pull-up resistor R7 by the output voltage V5 of the converter 1, and the CPU 203 detects the Zerox signal. The High state of the is detected. When the potential of the NEUTRAL line is lower than the potential of the LIVE line, a current flows through the X capacitor discharge resistor R1, and no current flows through the X capacitor discharge resistor R2, so that the transistor Q2 is turned off. When the transistor Q2 is turned off, a current flows from the auxiliary winding voltage Vcc through the pull-up resistor R6 to the primary side diode of the photocoupler PC1, so that the secondary transistor of the photocoupler PC1 is turned on. When the secondary transistor of the photocoupler PC1 is turned on, the voltage of the Zerox signal decreases, and the CPU 203 detects the Low state of the Zerox signal. The zero cross waveform will be described later with reference to FIG.

  Next, the voltage detection unit 205 will be described. The current flowing through the Y capacitor discharge resistors R3 and R4 is charged in the capacitor C6. R10 is a discharge resistance of the capacitor C6. The voltage Vin smoothed by the resistor R11 and the capacitor C7 is input to the voltage detection unit 205. When the voltage of the AC power supply 201 decreases, the charging current to the capacitor C6 decreases, and the detection voltage Vin of the voltage detection unit 205 decreases. When the voltage Vin becomes equal to or lower than a predetermined threshold voltage Vth (1.16 V in the present embodiment), the voltage detection unit 205 sets Vout to a low state and stops the output of the converter 2. When the output of the converter 2 stops and the voltage of V24 decreases, the voltage of the signal (V24sense signal) obtained by dividing the voltage of V24 by the resistors R12 and R13 decreases. The CPU 203 determines that the converter 2 has been stopped based on the V24 sense signal. The details of the power failure detection method will be described later with reference to FIGS.

  Next, the operation of the circuit of FIG. 2 in the energy saving state where the apparatus is not operating will be described. Since the Standby signal is in the low state in the energy saving state, the auxiliary winding voltage Vcc is in the low state. Since Vcc is in the Low state, no current flows through the resistor R6 of the zero-crossing detection unit 202, the primary side diode of the photocoupler PC1, and the collector terminal of the transistor Q2, thereby reducing power consumption. Further, power supply to the converter 2 is stopped, and power consumption can be suppressed by stopping the switching operation of the converter 2. Further, since the auxiliary winding voltage Vcc is in the low state, the high breakdown voltage transistor Q1 is in the OFF state. Therefore, the current flowing from the LIVE line via the Y capacitor discharge resistor R3 and the current flowing from the NEWTRAL line via the Y capacitor discharge resistor R4 can be cut off to reduce power consumption. In such a state where the power consumption is suppressed, the secondary transistor of the photocoupler PC1 is always in the OFF state, so that the Zerox signal is always in the High state (that is, the state in which the zero cross timing cannot be detected). Further, the input voltage Vin of the voltage detection unit 205 is always in a low state (that is, a state in which the voltage from the AC power source cannot be detected).

  Next, the operation of the circuit of FIG. 2 in an operation state such as when the apparatus is on standby or during image formation will be described. In such an operating state, the zero cross timing of the AC power supply 201 and the input voltage can be detected. In the state in which the zero cross timing and the voltage can be detected, the standby signal is in the high state, and thus the auxiliary winding voltage Vcc is in the high state. Since Vcc is in the high state, the transistor Q1, the zero cross detection unit 202, the voltage detection unit 205, and the power for driving the converter 2 are supplied. A current flows through the resistor R6, the primary diode of the photocoupler PC1, and the collector terminal of the transistor Q2, and the power consumption of the zero-cross detection unit 202 increases. Moreover, since the converter 2 starts, the power consumption of the converter 2 increases. When the auxiliary winding voltage Vcc is in a high state, the high breakdown voltage transistor Q1 is in an ON state, and the voltage detection unit 205 is in a state in which the voltage of the AC power supply 201 can be detected. Power consumption increases due to the current flowing from the LIVE line via the Y capacitor discharge resistor R3 and the current flowing from the NEW line via the Y capacitor discharge resistor R4. In a state where the zero-cross timing and voltage can be detected, the power consumed by the power supply circuit 200 increases.

  As described above, the power supply circuit 200 according to the present embodiment cuts off the current to the Y capacitor discharge resistors R3 and R4 by turning off the transistor Q1 (first switch element), and the voltage detection unit 205 has the voltage. The current used for detection is also cut off, and the power consumption can be reduced.

  Next, the effects of the Y capacitor discharge resistors R3 and R4 will be described with reference to FIG. FIG. 3 is a diagram (simulation diagram) for explaining the influence of the Y capacitor discharge resistors R3 and R4 of the present embodiment on the detection accuracy of the zero-cross timing. The waveforms in FIG. 3 are simulation results under the conditions of X capacitor C1 = 0.56 μF, Y capacitor C3 = C4 = 2200 pF, X capacitor discharge resistance R1 = R2 = 1000 kΩ, and Y capacitor discharge resistance R3 = R4 = 150 kΩ.

  A waveform 301 shows an AC voltage waveform (220 Vrms, 50 Hz) from the AC power supply 201. Zerox1, Zerox2, Zerox3 and Zerox4 are indicated by arrows on the AC voltage waveform as zero cross points. A waveform 302 indicates a zero-cross waveform in a state where the Y capacitor discharge resistors R3 and R4 are energized. In the waveform 302, the falling timing of the Zerox signal coincides with the zero cross, Zerox1, and Zerox3 of the AC power supply 201. The timings of Zerox2 and Zerox4 are detected inside the CPU 203. Specifically, first, the CPU 203 calculates a period (one cycle of the AC power supply 201) from Zerox1 to Zerox3 (20 msec in this example). The CPU 203 predicts, for example, a timing after a half cycle (10 msec in this example) from Zerox1 (3), which is the falling timing of the Zerox signal, as the timing of Zerox2 (4). Thus, if one of the falling timing or the rising timing of the zero cross is known, both the rising and falling zero crosses can be detected and predicted.

  A waveform 303 shows a zero-cross waveform (waveform in the third state described in the third embodiment) in a state where the Y capacitor discharge resistance is cut off. In the waveform 303, the rising and falling timings do not coincide with the zero crossing of the AC power supply in the waveform 301. This error is caused by the time (CR delay) required until the charges charged in the Y capacitors C3 and C4 are discharged. In the state of the waveform 303, there is an error in the detection of the zero cross timing due to the CR delay caused by the X capacitor discharge resistors R1 and R2 and the Y capacitors C3 and C4. In the waveform 302, since the resistance values of the Y capacitor discharge resistors R3 and R4 are small, the CR delay as in the waveform 303 is reduced, and the detection error of the zero cross timing can be improved. The error of the zero cross detection in the state of the waveform 303 varies depending on the AC voltage from the AC power supply 201 and the grounding state of the external power supply unit 40 to GND. For this reason, it is difficult to accurately detect the zero cross timing from the Zerox signal of the waveform 303. Note that in the waveform 303, it is possible to detect the cycle (frequency) of the AC voltage from the AC power supply 201 shown in the waveform 301 based on the timing and number of times of rising or falling.

  FIG. 4 is a simulation diagram for explaining the operation of power failure detection according to the present embodiment. In this simulation, the voltage of the AC power supply 201 is 220 Vrms (effective voltage value), the output of the converter 1 is 5 V, 6 A (30 W constant power load), the output of the converter 2 is 24 V, 6 A (144 W constant power load), the converter 1 and the conversion efficiency of the converter 2 were 90%, and the simulation was performed with the primary smoothing capacitor C2 being 270 μF.

  A waveform 400 shows an input voltage waveform (voltage between the LIVE terminal and the NEWTRAL terminal) from the AC power supply 201. In the present embodiment, it is assumed that the power supply cable 50 is pulled out at the ACOFF timing (one and a half cycles of the AC voltage waveform: 30 msec). In the waveform 400, it can be seen that the electric charge charged in the X capacitor C1 is discharged from the timing when the power cable 50 is pulled out, and the voltage becomes 0V after the discharge. A waveform 411 indicates the voltage charged in the primary smoothing capacitor C2. A waveform 421 represents the Zerox signal. Here, an example of the first power failure detection means using the zero cross detection unit 202 will be described. In this embodiment, the output of V24 and V5 can be continued without detecting the power outage state at the moment of instantaneous interruption of 1 full wave (20 msec) (instantaneous power outage state), and the power outage state is established as soon as possible. A detection method will be described. When the AC power supply 201 is in a power failure state, zero crossing cannot be detected, so that the power failure state of the AC power supply can be determined. In the present embodiment, the rise and fall of the zero cross with an AC frequency of 50 Hz can be detected only at every AC cycle (20 msec), so that a maximum detection error of 20 msec occurs. When 5 msec is considered as an error factor such as frequency fluctuation, the state where the zero cross rise and rise cannot be detected from the timing when the zero cross rise is detected lastly, that is, when 45 msec or more has passed. What is necessary is just to detect a power failure state.

  Also, it can be seen from the Zerox signal 421 that the falling edge of the zero cross has been detected for a while after the power failure. This is because the base current is continuously supplied to the transistor Q2 by the charge of the X capacitor C1 when the power cable 50 is pulled out in a state where the X capacitor C1 is charged with a negative charge. Therefore, the Zerox signal is kept in the High state, and after the X capacitor C1 is discharged, the Zerox signal is in the Low state, and the falling of the zero cross is detected. Since the timing at which the trailing edge of Zerox can be detected last depends on the electric charge charged in the X capacitor C1, the variation becomes large. Therefore, the first power failure detection means of the present embodiment, after detecting the rising edge of the zero cross lastly, the time until the next rising edge detection, and finally detecting the falling edge of the zero crossing, A power failure state is detected when either one of the times until the falling edge is detected is 45 msec or more. When a power failure state is detected using the zero cross, as shown in the waveform 421, the timing at which the supply of voltage from the AC power supply is cut off (power failure) immediately after the zero cross is detected (ACOFF timing) is zero cross. This is the condition that takes the longest time to detect a power outage using. In the example shown in FIG. 4, the first power failure detection means can detect about 45 msec after the power failure occurs at the ACOFF timing.

  The 2nd power failure detection means by the voltage detection part 205 is demonstrated. A waveform 431 represents the input voltage Vin of the voltage detection unit 205. The operation of the converter 2 is stopped at a timing (60 msec) when the input voltage Vin decreases from the ACOFF timing and becomes equal to or lower than the threshold voltage value Vth. As described above, the voltage detection unit 205 is set to stop the converter 2 30 msec after the power failure so that the power failure state is not detected at the momentary interruption of one full wave (20 msec).

  A waveform 441 indicates the voltage value of the output voltage V24 of the converter 2. When the operation of the converter 2 is stopped, the output voltage rapidly decreases. When the voltage of V24 decreases, the value of V24sense, which is the voltage dividing resistance value of V24, decreases, and the Low state is set. Based on the V24sense signal, the CPU 203 can detect a power failure state. A waveform 451 indicates the voltage value of the output voltage V5 of the converter 1. When the voltage (411) charged in the primary smoothing capacitor C2 falls below a limit voltage value that can hold the output voltage of the converter 1, the converter 1 cannot hold the output voltage V5. The limit voltage of the converter 1 of this embodiment is 120V. The timing V5 OFF (173 msec) at which the output voltage V5 cannot be held is illustrated.

  As shown in FIG. 4, the second power failure detection means can detect about 30 msec after the power failure occurs at the ACOFF timing. It was possible to obtain a grace period of about 113 msec from when the power failure state was detected until the converter 1 stopped. By using the above-described grace time, the image forming apparatus and the power supply circuit may be changed to a state in which they can be normally stopped. In the example described with reference to FIG. 4, it can be seen that the second power failure detection means can detect the power failure state earlier than the first power failure detection means.

  FIG. 5 is a simulation diagram for explaining the power failure detection means of the first embodiment. Description of points that are the same as the simulation described in FIG. 4 is omitted. In this simulation, a power failure state in which the input voltage from the AC power supply 201 is reduced from 220 Vrms to 100 Vrms is described. A waveform 500 indicates an input voltage waveform (voltage between the LIVE terminal and the NEWTRAL terminal) from the AC power supply 201. In this embodiment, it is assumed that the power supply voltage drops from 220 Vrms to 100 Vrms at 0 msec. A waveform 511 represents a voltage charged in the primary smoothing capacitor C2.

  The first power failure detection means by the zero cross detection unit 202 will be described. A waveform 521 represents the Zerox signal. Even if the voltage of the AC power supply 201 decreases, the zero crossing does not stop, so the first power failure detection means cannot detect the state where the voltage has decreased.

  The 2nd power failure detection means by the voltage detection part 205 is demonstrated. A waveform 531 indicates the input voltage Vin of the voltage detection unit 205. The operation of the converter 2 is stopped at a timing (95 msec) at which the input voltage Vin decreases from the timing when the voltage of the AC power supply 201 decreases and becomes equal to or lower than the threshold voltage value Vth. A waveform 541 represents the voltage value of the output voltage V24 of the converter 2. A waveform 551 indicates the voltage value of the output voltage V5 of the converter 1.

  As described above, when the voltage (511) charged in the primary smoothing capacitor C2 of the converter 1 falls below the limit voltage value 120V that can hold the output voltage of the converter 1, the converter 1 holds the voltage of the output voltage V5. become unable. As shown in FIG. 5, the power failure state can be detected by the second power failure detection means before the voltage of the primary smoothing capacitor drops to 120 V or less, and before the converter 1 stops, the image forming apparatus and The power supply circuit can transition to a state where it can be stopped normally.

  FIG. 6 is a simulation diagram for explaining the power failure detection means of the first embodiment. Description of points that are the same as the simulation described in FIG. 4 is omitted. A waveform 600 indicates an input voltage waveform (voltage between the LIVE terminal and the NEWTRAL terminal) from the AC power supply 201. In this embodiment, it is assumed that the power cable 50 is pulled out at the ACOFF timing (25 msec). In the waveform 600, it can be seen that the charge charged in the X capacitor C1 is discharged from the timing when the power cable 50 is pulled out, and the voltage becomes 0V after the discharge. A waveform 611 indicates the voltage charged in the primary smoothing capacitor C2. A waveform 621 represents the Zerox signal. Here, the 1st power failure detection means using the zero cross detection part 202 is demonstrated. As described with reference to FIG. 4, the power failure state can be detected when 45 msec has elapsed from the timing at which the rising edge of the zero cross is detected lastly. The first power failure detection means can detect the power failure state at a timing of 55 msec, 30 msec after the power failure at ACOFF (25 msec).

  The 2nd power failure detection means by the voltage detection part 205 is demonstrated. A waveform 631 indicates the input voltage Vin of the voltage detection unit 205. Here, when compared with the waveform described in FIG. 4, it can be seen that the input voltage Vin starts to decrease after a while from ACOFF. As shown in the waveform 600, when the power cable 50 is pulled out at the timing when the voltage of the AC power supply 201 reaches the peak value, the peak voltage of the AC power supply 201 is charged in the X capacitor C1. For this reason, the voltage of the input voltage Vin indicated by the waveform 631 drops below the threshold voltage value Vth by the amount of time that the voltage of the X capacitor C1 drops, and the time required until the power failure state can be detected becomes long. In the case of FIG. 6, the time required for the first power failure detection means to detect the power failure state is 51 msec, and a delay time of about 21 msec occurs compared to the case of FIG.

  The cause of this delay time is a CR delay determined by the X capacitor C1, the capacitance value, the X capacitor discharge resistors R1, R2, and the Y capacitor discharge resistors R3, R4. Since the Y capacitor discharge resistors R3 and R4 having lower resistance values than the X capacitor discharge resistors R1 and R2 are used in the first embodiment, the above-described delay time is compared with the case where the Y capacitor discharge resistors are not used. Can be reduced. When detecting the power failure state using the voltage detection unit 205, as shown in FIG. 6, when the power cable 50 is pulled out at the timing when the voltage of the AC power source 201 reaches the peak value, the power failure state is detected. Is the most time-consuming condition.

  A waveform 641 indicates the voltage value of the output voltage V24 of the converter 2. A waveform 651 represents the voltage value of the output voltage V5 of the converter 1. The timing V5OFF (197 msec) at which the voltage (611) charged in the primary smoothing capacitor C2 decreases and the converter 1 cannot hold the output voltage V5 is illustrated.

  As shown in FIG. 6, the first power failure detection means can detect about 30 msec after a power failure occurs due to ACOFF. It was possible to obtain a grace period of about 142 msec from when the power failure state was detected until the converter 1 stopped. By using the above-described grace time, the image forming apparatus and the power supply circuit may be changed to a state in which they can be normally stopped. In the example described with reference to FIG. 6, it can be seen that the first power failure detection means can detect the power failure state earlier. However, FIG. 6 describes a power failure state due to the power cable 50 being pulled out. For example, when the output of the AC power supply 201 drops to 0 V, the charge of the X capacitor C1 is immediately discharged. Therefore, the delay time described above is reduced, and the power failure state can be detected quickly even by the second power failure detection means.

  FIG. 7 is a simulation diagram for explaining the power failure detection means of the first embodiment. Description of points that are the same as the simulation described in FIG. 4 is omitted. In this simulation, the output of the converter 1 is 5V, 6A (30W constant power load), the output of the converter 2 is 24V, 0A (0W constant power load), and the power of the output voltage V5 of the converter 1 is large. The case where the power of the output voltage V24 of 2 is very low will be described.

  A waveform 700 shows an input voltage waveform (voltage between the LIVE terminal and the NEWTRAL terminal) from the AC power supply 201. In the present embodiment, it is assumed that the power cable 50 is pulled out at ACOFF (25 msec). A waveform 711 shows the voltage charged in the primary smoothing capacitor C2.

  A waveform 721 represents the Zerox signal. Here, the 1st power failure detection means using the zero cross detection part 202 is demonstrated. As described with reference to FIG. 4, the power failure state can be detected when 45 msec has elapsed from the timing at which the rising edge of the zero cross is detected lastly. The first power failure detection means can detect the power failure state at a timing of 55 msec, 30 msec after the power failure at ACOFF (25 msec).

  The 2nd power failure detection means by the voltage detection part 205 is demonstrated. A waveform 731 indicates the input voltage Vin of the voltage detection unit 205. When the power of the output voltage V24 of the converter 2 is very low, the output voltage V24 of the converter 2 is held by a capacitor (not shown) even when the converter 2 is stopped using the second power failure detection means. . Therefore, when the power of the output voltage V24 of the converter 2 is very low, V24sense remains in the high state, and the power failure state may not be detected by the CPU 203 before the output of the converter 1 stops. However, if the photocoupler PC3 is added and the power failure state is directly detected as in the power supply circuit 900 of Example 2 described later, the power failure state can be detected by the second power failure detection means.

A waveform 741 indicates the voltage value of the output voltage V24 of the converter 2.
A waveform 751 indicates the voltage value of the output voltage V5 of the converter 1. The timing V5OFF (352 msec) at which the voltage (711) charged in the primary smoothing capacitor C2 decreases and the converter 1 cannot hold the output voltage V5 is illustrated.

  As shown in FIG. 7, the first power failure detection means can detect the power failure state about 30 msec after the power failure state occurs due to ACOFF. It was possible to obtain a grace period of about 297 msec from when the power failure state was detected until the converter 1 stopped.

  FIG. 8 is a flowchart for explaining a control sequence of the power supply circuit 200 by the CPU 203 of the first embodiment. When the control starts in S800, the process proceeds to S801. In S801, the Standby signal is set to the High state, power is supplied to the converter 2, the zero cross detection unit 202, and the voltage detection unit 205, and the Y capacitor discharge resistors R3 and R4 are energized (this state is the second state). State, zero-crossing and voltage detection possible).

  In S802, it is determined whether the input voltage Vin of the voltage detection unit 205 is a voltage smaller than the threshold voltage Vth. When the input voltage Vin is low, the process proceeds to S803 and the converter 2 is stopped. If the input voltage Vin is high, the converter 2 is started in S804. If the converter 2 has already been activated, the activated state is continued.

  In S805, the power failure state is determined based on the V24sense signal. When V24sense is in the Low state, a power failure state is detected, and the process proceeds to S809. In S806, the zero cross of the AC power supply 201 is detected based on the falling timing of the Zerox signal.

  In S807, if the rise of the Zerox signal cannot be detected for 45 msec or more, or if the fall of the Zerox signal cannot be detected for 45 msec or more, the process proceeds to S809 to detect a power failure state. In this embodiment, the case where both falling and rising of Zerox are detected has been described, but it is also effective in the case where a power failure state is detected by only one of falling and rising of Zerox. .

  When a power failure state is detected in S805 and S807, in S809, the Standby signal is set to the Low state, the power supply to the converter 2, the zero cross detection unit 202, and the voltage detection unit 205 is cut off, and the Y capacitor discharge resistor R3 and R4 is turned off (first state, energy saving state). This first state is a state in which the power supply can be normally stopped even when the AC power supply fails. For example, when the image forming apparatus according to the present exemplary embodiment includes a hard disk (not illustrated), a process for avoiding a data crash or the like is performed. The above process is repeated until the end of the standby state is determined in S808, and after the process of S809 described above is terminated, the control is terminated in S810.

  Here, the effect of providing the first power failure detection means using the zero cross detection unit 202 and the second power failure detection means using the voltage detection unit 205 will be described. As described with reference to FIG. 4, when the power cable 50 is pulled out immediately after detecting the zero crossing, the first power failure detection means requires the most time to detect the power failure, and the second power failure detection. The means can quickly detect a power outage. As explained in FIG. 6, when the power cable 50 is pulled out at the timing when the voltage of the AC power supply 201 reaches the peak value, it takes the longest time for the second power failure detection means to detect the power failure state. Thus, the first power failure detection means can quickly detect the power failure state. By using the first power failure detection means and the second power failure detection means, even when the timing at which the power cable 50 is pulled out changes, the power failure state can be detected quickly. Further, as described with reference to FIG. 5, when the voltage of the AC power supply 201 greatly decreases, the power failure state can be detected by the second power failure detection means. Further, as described in FIG. 7, when the power of the output voltage V5 of the converter 1 is large and the power of the output voltage V24 of the converter 2 is very low, the power failure state can be detected by the first power failure detection means.

  Thus, by using the first power failure detection means using the zero cross detection unit 202 and the second power failure detection means using the voltage detection unit 205, it is possible to detect the power failure state with a simple configuration with high accuracy. it can. Further, in the power supply circuit 200 of the present embodiment, the first switch means Q1 is used as means for cutting off the current flowing through the discharge resistances R3 and R4 of the Y capacitor, and the current necessary for voltage detection of the voltage detection unit 205 is used. By using as a means for shutting off, it is possible to switch between a state where zero cross detection and power failure voltage detection can be performed and a state where power consumption can be reduced with only one high withstand voltage switch means Q1.

  As described above, according to the present embodiment, a power failure state can be detected early with a simple configuration, and power consumption in a standby state of the apparatus can be reduced.

  Next, a power supply circuit 900 including the voltage detection unit 905 according to the second embodiment will be described with reference to FIG. The description of the same configuration as in the first embodiment is omitted.

  The configuration of the second embodiment requires a photocoupler PC3 as compared with the configuration of the first embodiment. However, as shown in FIG. 7, the power of the output voltage V5 of the converter 1 is large, and the output voltage V24 of the converter 2 Even when the power is low, the power failure state can be detected using the voltage detection unit 905.

  The operation of the voltage detection unit 905 of this embodiment will be described. The voltage detection unit 905 sets Vout to the low state when the input voltage Vin is equal to or lower than the predetermined threshold voltage Vth (in this embodiment, 1.16 V), and no current flows through the primary diode of the photocoupler PC3. To. R901 and R902 are pull-up resistors. When the current does not flow through the primary diode of the photocoupler PC3, the secondary transistor of the photocoupler PC3 is turned off, so that the VACsense signal is in a high state, and the CPU 903 can detect a power failure state.

  As described above, according to the present embodiment, a power failure state can be detected early with a simple configuration, and power consumption in a standby state of the apparatus can be reduced.

DESCRIPTION OF SYMBOLS 100 Image heating apparatus 200 Power supply circuit 202 Zero cross detection part 205 Voltage detection part C1 X capacitor C2 Smoothing capacitor C3, C4 Y capacitor R1 X capacitor discharge resistance R2 Zero cross detection resistance (X capacitor discharge resistance)
R3, R4 Y capacitor discharge resistance Q1 First switch means BD1 Bridge diode

Claims (7)

Rectifying means for full-wave rectifying the input AC voltage;
A first converter for converting the voltage rectified by the rectifying means;
A second converter connected in parallel to the first converter;
Zero-cross detection means for detecting zero-cross of the AC voltage;
Voltage detecting means for detecting the AC voltage;
A first capacitive element connected between the potential after full-wave rectification by the rectifying means and the ground;
A first discharge resistor for discharging the charge charged in the first capacitive element;
First switch means for interrupting a current flowing through the discharge resistor;
The AC voltage is detected by the voltage detection means using the current flowing through the first discharge resistor, and when the detected voltage is smaller than a threshold value, stop means for stopping the operation of the second converter is provided. And
A power supply comprising: a first state in which the first switch means is turned off; and a second state in which the first switch means is turned on. Furthermore, a second capacitive element is connected between the two lines to which the AC voltage is supplied,
A second discharge resistor for discharging the charge charged in the second capacitor element,
The zero cross detection means detects a zero cross of the AC voltage using a current flowing through a second discharge resistor, and the resistance value of the first discharge resistor is smaller than the resistance value of the second discharge resistor. The power supply according to claim 1.   3. The first power failure detection means for determining that the zero cross detection means is in a power failure state when the zero cross of the AC voltage cannot be detected for a predetermined time or longer. Power supply described in.   3. The power supply according to claim 1, further comprising: a second power failure detection unit that determines that a power failure state occurs when the voltage detection unit detects a voltage lower than the threshold value. 4. A power source according to claims 1 to 4;
A heating device that heats the recording medium while conveying it,
An image forming apparatus, wherein power to the heating device is controlled according to a result of detecting a zero cross of the AC voltage by the zero cross detecting means. A first converter that converts the voltage after full-wave rectification of the input AC voltage;
A second converter connected in parallel to the first converter;
Zero-cross detection means for detecting zero-cross of the AC voltage;
Voltage detecting means for detecting the value of the AC voltage,
A stopping means for stopping the operation of the second converter when the voltage detected by the voltage detecting means is lower than a threshold;
A first power failure detection means for determining a power failure state when the zero cross detection means fails to detect the zero cross for a predetermined time or more;
A power failure detection device comprising second power failure detection means for determining that a power failure has occurred when the voltage detected by the voltage detection means is lower than a threshold value. A first capacitive element connected between a potential after full-wave rectification of the AC voltage and a ground;
A first discharge resistor for discharging the charge charged in the first capacitive element;
A second capacitive element connected between two lines to which the AC voltage is supplied;
First switch means for cutting off a current flowing through the discharge resistor,
The power failure detection device according to claim 6, wherein the second capacitive element is discharged using the first discharge resistor when the switch means is energized.