JP2013157803A - Voice reproduction device, and voice reproduction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the generation of unnecessary voice data generated by stopping a CPU clock when silence data are reproduced.SOLUTION: A voice reproduction device 100 to which a clock and voice data are supplied, and which reproduces an analog voice signal analog-converted from the voice data by using the clock, includes: a data comparison apparatus 104 for generating a clock stop signal when the voice data are equal to a threshold value or close to a zero value rather than the threshold value; an output data generator 114 for generating fadeout data which gradually decreases the voice data in a zero value direction, according to the clock stop signal; an output switching control portion 115 for outputting a switch signal which switches the voice data to the fadeout data, according to the clock stop signal; and a CG portion 107 for stopping the clock according to the clock stop signal.

Description

  The present invention relates to an audio reproduction device and an audio reproduction method, and, for example, relates to an audio reproduction device and an audio reproduction method for determining a silent data input and stopping a CPU (Central Processing Unit) clock when the audio input is at a low level.

  Along with recent improvements in digital technology, compressed audio signals such as MP3 (MPEG Audio Layer-3) and WMA (Windows Media (registered trademark) Audio) and analog audio signals are played back by signal processing using an audio DSP (Digital Signal Processor). An audio reproducing apparatus that has been put into practical use has been put into practical use. Since many audio playback devices are portable products, there is an increasing demand for reducing the power consumption of the entire system, reducing the power consumption of the entire system, and extending the usage time.

  As a technique for reducing power consumption, a technique is known in which when the voice input is at a low level, it is determined that silence data has been input, and the CPU clock is stopped. Patent Document 1 discloses that a mute control signal is generated by detecting a supply stop of a clock by integrating a clock for audio reproduction in order to prevent power supply noise and clock noise from being emitted from a speaker during silence. A technique for stopping the output of an analog audio signal is disclosed.

  In the digital audio output circuit described in Patent Document 1, PCM (Pulse-code modulation) audio data is supplied from the output-side PCM interface to the input-side PCM interface together with a synchronization signal and a clock.

  The input-side PCM interface synchronizes with the sampling synchronization signal, converts the PCM audio data into digital / analog using a clock by a built-in D / A converter, and outputs an analog audio signal.

  The analog audio signal output from the input-side PCM interface is amplified by a speaker driver, supplied to the speaker, and is sounded. The mute control signal is generated by comparing an integrated signal obtained by integrating the clock with a comparator. The speaker driver performs mute according to the mute control signal.

JP 2005-79877 A

  In Patent Document 1, the mute control signal is generated as a result of integrating a clock. For this reason, it takes time until the speaker driver is muted after the clock supply is stopped.

  During this time, if a potential difference occurs in the output of the D / A converter built in the input-side PCM interface due to power supply noise or clock noise, there is a problem that unnecessary sound (hereinafter referred to as a “bottom sound”) is generated from the speaker after the clock is stopped. is there.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a clock stop signal is generated when the audio data is equal to a predetermined threshold value or closer to a zero value than the threshold value, and the audio data is stepped in a zero value direction according to the clock stop signal. The fade-out data to be made smaller is generated, the audio data is switched to the fade-out data, and the clock is stopped.

  According to the embodiment, even when silence data is input, even when the CPU clock is stopped, it is possible to suppress the output of the clapping sound.

It is a figure which shows the structure of the audio | voice reproduction apparatus which concerns on embodiment. It is a figure which shows the structure of the output data generator of the audio | voice reproduction apparatus which concerns on embodiment. It is a timing chart which shows the clock stop operation | movement in the audio | voice reproduction apparatus which concerns on embodiment. It is a timing chart which shows operation | movement of the output data generator of the audio | voice reproduction apparatus which concerns on embodiment. It is a timing chart which shows the other example of the clock stop operation | movement in the audio | voice reproduction apparatus which concerns on embodiment. It is a timing chart which shows the clock resumption operation | movement in the audio | voice reproduction apparatus which concerns on embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description will be omitted.

Embodiment.
An audio playback apparatus according to an embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration of an audio reproduction device 100 according to an embodiment. In FIG. 1, the audio playback device 100 is described as an example of an apparatus configured by SIP (System In Package) in which two chips, an AD / DA chip 101 and a CPU chip 102, are housed in one package.

  The audio reproduction device according to the embodiment is an audio reproduction device that reproduces a compressed audio signal or an analog audio signal, and has a function of stopping the CPU clock by determining that there is no sound when the audio input is at a low level.

  The AD / DA chip 101 includes an A / D unit 103, a data comparator 104, an AD / DA chip input side PCM unit 105, an AD / DA chip output side PCM unit 113, an output data generator 114, an output switching control unit 115, A selector unit 116, a D / A unit 117, and a frequency divider 118 are included.

The CPU chip 102 includes a CPU chip input side PCM unit 106, a CG (Clock Generator) unit 107, an SPI (Serial parallel interface) unit 108, a CPU (Central
A processing unit (109) unit, a read-only memory (ROM) unit 110, a random access memory (RAM) unit 111, and a PCM unit 112 on the CPU chip output side are included.

  The A / D unit 103 receives an audio analog signal from an AUX (Auxiliary) signal input 130 and converts A / D data 131, which is digital data obtained by converting the audio analog signal, into an AD / DA chip input side PCM unit 105 and a data comparator 104. Output to. The audio analog signal input from the AUX signal input 130 is an audio signal output from an external device, for example, a music signal output from a portable digital audio playback device.

  The frequency divider 118 receives a clock 324 that is a system clock. The frequency divider 118 generates a frequency-divided clock 328 of 44.1 kHz, which is a music data sampling period, using the clock 324, and outputs it to the data comparator 104 and the output data generator 114.

  The data comparator 104 receives A / D data 131 output from the A / D unit 103, a divided clock 328 output from the dividing period 118, and a serial communication signal 134 output from the SPI 108. The data comparator 104 compares the A / D data 131 with a predetermined threshold set by the serial communication signal 134 according to the divided clock 328, and the CPU clock stop control signal 133 generated according to the comparison result. Are output to the output data generator 114, the output switching control unit 115, and the CG unit 107. The predetermined threshold will be described later.

  The AD / DA chip input side PCM unit 105 is a serial interface for transferring audio data. The AD / DA chip input PCM unit 105 receives the A / D data 131 of the A / D unit 103 and outputs an input serial data signal 132 to the CPU chip input PCM unit 106.

  The AD / DA chip output-side PCM unit 113 receives the output-side serial data signal 137 output from the CPU chip output-side PCM unit 112 and outputs PCM output data 138 to the selector unit 116 and the output data generator 114.

  The output data generator 114 receives the PCM output data 138 and the CPU clock stop control signal 133, outputs the output data 139 as fade-out data and fade-in data to the selector unit 116, and outputs a switching timing signal to the switching control unit 115. 144 is output.

  The output switching control unit 115 receives the clock 324, the switching timing signal 144 output from the output data unit 114, and the CPU clock stop control signal 133 output from the data comparison unit 104. The output switching control unit 115 generates an input logical product in accordance with the clock 324 and outputs the logical product to the selector unit 116 as the switching signal 140.

  The selector unit 116 receives PCM output data 138 input from the AD / DA chip output side PCM unit 113 and output data input from the output data generator 114 in response to the switching signal 140 input from the output switching control unit 115. 139 is selected and output to the D / A unit 117 as audio data 141.

  The D / A unit 117 converts the audio data 141 output from the selector unit 116 into analog data, and outputs the analog data to the speaker as an L-ch analog signal 142 and an R-ch analog signal 143.

  The SPI unit 108 is an interface that performs serial communication, and outputs a serial communication signal 134 in order to set a predetermined threshold value in the data comparator 104. This threshold value is a voltage level and is a threshold value for determining whether the A / D data 131 is silent data.

  The CPU unit 109 performs signal processing of audio data using a ROM unit 110 that stores programs and a RAM unit 111 that stores data, and an SPI unit 108 and a CPU chip input side PCM unit 106 connected to the internal bus 135. The CPU chip output side PCM unit 112 is controlled.

  The CPU chip input PCM unit 106 receives the input serial data signal 132 and stores audio data in the RAM unit 111. A CPU unit 109 constituting an audio DSP (Digital Signal Processor) performs signal processing of data stored in the RAM unit 111 and stores the data in the RAM unit 111 again. The CPU chip output side PCM unit 112 outputs the audio data after the signal processing to the AD / DA chip output side PCM unit 113 as an output side serial data signal 137.

  Here, the configuration of the output data generator 114 used in the audio reproduction device according to the embodiment will be described. FIG. 2 is a diagram illustrating the configuration of the output data generator 114. The output data generator 114 includes an edge detection unit 301, a flip-flop (F / F) input selector 302, a flip-flop (F / F) 303, a multiplier 304, a sequencer 305, and a comparator 306.

  The edge detection unit 301 receives a CPU clock stop control signal 133 and a clock 324. The edge detection unit 301 detects an edge of the CPU clock stop control signal 133 according to the clock 324 and outputs the edge detection signal 322 to the F / F input selector 302 and the sequencer 305. Note that the clock 324 is a system clock, is supplied from outside the AD / DA chip 101, and is input to the sequencer 305 and the edge detection unit 301, respectively.

  The sequencer 305 receives the edge detection signal 322, the clock 324, the divided clock 328, and the comparator output signal 325 output from the comparator 306. Using these signals, the sequencer 305 outputs a multiplication clock 323 as a clock of the F / F 303 and outputs a switching timing signal 144 that is an output of the output data generator 114 to the output switching control unit 115.

  The output signal of the multiplier 304, the PCM output data 138, and the edge detection signal 322 are input to the F / F input selector 302. The F / F input selector 302 selects either the PCM output data 138 of the AD / DA chip output side PCM unit 113 or the output signal of the multiplier 304 based on the edge detection signal 322, and outputs the selector output 321 to the F / F 303. To do.

  The F / F 303 receives a selector output 321 from the F / F input selector 302 and a multiplication clock 323 from the sequencer unit 305. The F / F 303 outputs the selector output 321 as output data 139 to the multiplier 304, the comparator 306, and the selector unit 116 according to the multiplication clock 323, respectively.

  The multiplier 304 receives the output data 139 output from the F / F 303 and the multiplication constant 326. The multiplier 304 outputs the data obtained by multiplying the output data 139 by the multiplication constant 326 to the F / F input selector 302. The multiplication constant 326 is a value set in the register in advance, and the output data 139 is multiplied by the multiplication constant 326 to make the output data 139 approach a zero value.

  Output data 139 and comparison data 327 output from the F / F 303 are input to the comparator 306. The comparator 306 compares the output data 139 and the comparison data 327 and outputs a comparator output signal 325 to the sequencer 305. The comparison data 327 is a value set in advance in a register, and is a constant for determining that the output data 139 is a zero value.

  In the embodiment, the two chips AD / DA chip 101 and CPU chip 102 are configured by SIP, but the AD / DA chip 101 and CPU chip 102 may be configured by one chip. Good.

  Here, with reference to FIG. 3, the clock stop operation in the audio reproduction device 100 according to the embodiment will be described. FIG. 3 is a timing chart showing a clock stop operation in the audio reproduction device 100 according to the embodiment.

  FIG. 3A is a graph showing the waveform of the A / D data 131. The vertical axis indicates the level of the A / D data 131 that is audio data, and the horizontal axis indicates time. Here, the A / D data 131 has an amplitude with a maximum value of 7FFFH (hexadecimal number) and a minimum value of 8000H (hexadecimal number) centered on 0000H (hexadecimal number).

  3A, the solid line is the A / D data 131, the dotted line along the peak of the waveform of the A / D data 131 is the peak hold value 131 (P), and the bottom of the waveform of the A / D data 131. The dotted line indicates the bottom hold value 131 (B). FIG. 3A shows an example in which threshold values are set up and down around 0000H.

  The upper threshold value and the lower threshold value are used when determining whether or not the A / D data 131 is silence data. The upper threshold value is compared with the peak hold value 131 (P), and the lower threshold value is compared with the bottom hold value 131 (B). In the embodiment, the peak hold value 131 (P) is equal to the upper threshold value or closer to the zero value than the threshold value, and the bottom hold value 131 (B) is equal to or lower than the lower threshold value. Is also determined to be silence data when the value is close to zero. As described above, by setting the threshold values up and down around 0000H, it is possible to more accurately determine that the A / D data 131 is silence data.

  Note that only one threshold value is set, and one of the peak hold value 131 (P) of the A / D data and the bottom hold value 131 (B) of the A / D data is compared with the threshold value, and the A / D data It is also possible to determine whether 131 is silent data.

  FIG. 3B shows the comparison timing, the CPU clock stop control signal 133, and the audio data 141 input to the D / A unit 117. The comparison timing is a timing for comparing the threshold value with the peak hold value 131 (P) and the bottom hold value 131 (B) in the period of 44.1 kHz of the frequency-divided clock 328. In the audio data 141, XXXH (hexadecimal number) indicates that the audio output level is an arbitrary value, and 0000H (hexadecimal number) indicates that the audio output level is zero and indicates a mute state.

  FIG. 3C shows a waveform of the audio data 141 input to the D / A unit 117. The vertical axis indicates the level of the audio data 141, and the horizontal axis indicates time. The audio data 141 has an amplitude with a maximum value of 7FFFH (hexadecimal number) and a minimum value of 8000H (hexadecimal number) centered on 0000H (hexadecimal number).

  In FIG. 3C, a period A is a fade-out period, and is a period until the audio data 141 is muted from an XXXH value (hexadecimal number), which is an arbitrary value, to a 0000H value (hexadecimal number). A period B indicates a mute state period and continues until the PCM output data 138 is output again.

  FIG. 3D shows the CPU clock 136. A period C indicates a period in which the clock is stopped after the audio data 141 is changed to the mute state of 0000H (hexadecimal number).

  The audio analog signal input from the AUX signal input 130 is digitally converted by the A / D unit 103 and output as A / D data 131. The data comparator 104 samples the peak hold value 131 (P) and the bottom hold value 131 (B) of the A / D data 131 at a regular interval of 44.1 kHz. The frequency of 44.1 kHz is the audio sampling period of the compact disc (hereinafter referred to as 44.1 kHz).

  The peak hold value 131 (P) of the A / D data is a value obtained by holding the peak value of the A / D data 131, and leaks in the 0000H (hexadecimal number) direction. The bottom hold value 131 (B) of the A / D data is a value obtained by holding the bottom value of the A / D data 131 and leaks in the 0000H (hexadecimal number) direction.

  A predetermined threshold set in advance by the SPI unit 108 is compared with the sampled peak hold value 131 (P) and the bottom hold value 131 (B). The threshold is a threshold for determining whether the A / D data 131 is silence data.

  As shown in FIG. 3A, the CPU clock of the data comparator 104 is stopped because the A / D data 131 is continuously closer to the zero value than the threshold in the predetermined period from T1 to T2 in FIG. The control signal 133 changes from the low level to the high level. In the embodiment, the period from T1 to T2 is set to 5 seconds longer than the silent data period between songs in the compact disc format. This makes it possible to identify the silence data between songs and the A / D data 131 being silence data. The period for determining the silence data of the A / D data 131 is not limited to this.

  The output data generator 114 latches the PCM output data 138 by the output data generator 114 at the timing when the rising edge of the CPU clock stop control signal 133 is detected. Based on the latched PCM output data 138, the output data generator 114 outputs, as output data 139, fade-out data whose value is decreased stepwise so as to become zero values every 44.1 kHz period to the selector unit 116. .

  As a method of decreasing the output data 139 stepwise, a method of multiplying the latched data value by a multiplication constant 326 smaller than 1 stepwise every 44.1 kHz period is exemplified.

  The selector 116 in the preceding stage of the D / A unit 117 selects the output data 139 that is fade-out data from the PCM output data 138 and the output data 139 according to the CPU clock stop control signal 133, and the D / A unit It outputs to 117.

  For example, after the PCM output data 138 is latched by the output data generator 114 in the periods indicated by the period A and the period B, the selector unit 116 moves from the AD / DA chip output side PCM unit 113 to the output data generator 114 side. Switch. Generation of the switching timing of the selector unit 116 is performed by the output switching control unit 115. The output switching control unit 115 switches the selector unit 116 based on the timing at which the rising edge of the CPU clock stop control signal 133 is detected.

  The CG unit 107 detects a rising edge of the CPU clock stop control signal 133 in the period A, and the output data 139 input to the D / A unit 117 has a sufficient time (for example, a mute state at a 0000H value (hexadecimal number)). After 10 milliseconds), the clock of the CPU unit 109 is stopped.

  As described above, in this embodiment, before the clock of the CPU unit 109 is stopped, the fade-out data that is gradually reduced from the sound generation state to the zero value direction in the output data generator 114 in the period indicated by the period A. Is output to the D / A unit 117 as output data 139. As a result, it is possible to prevent the occurrence of a clicking sound from the speaker without causing a sudden potential difference between the L-ch analog signal 142 and the R-ch analog signal 143 output. In this example, since the clock of the CPU unit 109 is stopped after a sufficient time has elapsed for the output data 139 to be in a mute state, it is possible to more effectively prevent the generation of a humming sound.

  Here, the operation of the output data generator 114 in the period A of FIG. 3 will be described in detail with reference to FIG. FIG. 4 is a timing chart showing the operation of the output data generator 114.

  In FIG. 4, a period F is a period during which an edge of the CPU clock stop control signal 133 is detected. When the CPU clock stop control signal 133 changes to the high level at T5, the edge detection unit 301 detects the rising edge of the CPU clock stop control signal 133, and sets the high level of the edge detection signal 322 to the sequencer 305 and the F at T6. Output to the / F input selector 302.

  In response to the high level of the edge detection signal 322, the sequencer 305 outputs the multiplication clock 323 to the F / F 303 at T7. The F / F input selector 302 outputs PCM output data 138 to the F / F 303 in accordance with the high level of the edge detection signal 322 of T6.

  The F / F 303 latches the PCM output data 138 as data A (0) according to the multiplication clock 323 of T7. The sequencer 305 outputs the multiplication clock 323 to the F / F 303 at T7, and then outputs the high level of the switching timing signal 144 to the output switching control unit 115 at T8.

  The period G to the period I are periods for generating fade-out data. The multiplier 304 multiplies the multiplication constant by the F / F output data 139 at a predetermined period, and outputs the result to the F / F input selector 302. The F / F input selector 302 selects the output data of the multiplier 304 and outputs it to the F / F 303.

In the F / F 303, the multiplication result is latched repeatedly at T9, T10, and T11, respectively. Generation of the output data 139 of the F / F 303 is repeated n times until the output data 139 of the F / F becomes ALL zero using the equation (1).
A (n) = A (n−1) × S (1)
(N: number of operations executed (1 to n), A (n): output data obtained by performing n operations, S: multiplication constant)

  For example, output data 139 when the calculation is executed once is A (1) = data A (0) × multiplication constant, and output data 139 when the calculation is executed twice is A (2) = A ( 1) x multiplication constant.

  A clock 323 with a 44.1 kHz cycle is output from the sequencer 305 to the F / F 303. The calculation from the period G to the period I is executed, for example, at a cycle of 44.1 kHz, which is a basic cycle of audio output. The multiplication constant is a value smaller than 1 that attenuates data A (0) in the zero direction.

  The comparator 306 compares the output data 139 with the comparison data 327 from T9 to T11, and if the comparison result matches, outputs the high level of the comparator output signal 325 to the sequencer 305 at T12. The comparison data 327 is a zero value.

  In the period J, the sequencer 305 stops the output of the multiplication clock 323 at T13 in response to the high level of the comparator output signal 325 at T12. After T13, the F / F output data 139 is ALL zero and the mute state is entered.

  In the above example, the clock of the CPU unit 109 is stopped after a sufficient time has elapsed for the output data 139 input to the D / A unit 117 to be in a mute state, but the present invention is not limited to this. For example, as shown in FIG. 5, in response to the rising edge of the CPU clock stop control signal 133, the clock of the CPU unit 109 is stopped before the output data 139 input to the D / A unit 117 is muted. It is also possible.

  Also in this example, since the fade-out signal is output in the period A after the CPU unit 109 clock is stopped, there is no sudden potential difference between the L-ch analog signal 142 and the R-ch analog signal 143. Thus, it is possible to prevent the generation of a clicking sound from the speaker. In this example, since the clock of the CPU unit 109 is stopped before the output data 139 is muted, the power consumption can be further reduced.

  Next, with reference to FIG. 6, the clock resuming operation in the audio reproducing device 100 will be described. FIG. 6 is a timing chart showing the clock restart operation in the audio reproduction device 100. 6A to 6D are the same as those in FIGS. 3A to 3D.

  A period from T3 to T4 in the comparison timing in FIG. 6B is a period in which the A / D data 131 is compared with a threshold value to determine whether the data is silence data. When the A / D data 131 is farther from the zero value than the threshold for a predetermined period from T3 to T4, it is determined that the data is not silence data. As in FIG. 3A, FIG. 6A shows an example in which threshold values are set up and down around 0000H.

  Therefore, in the present embodiment, when the peak hold value 131 (P) is farther from the zero value than the upper threshold value and the bottom hold value 131 (B) is farther from the zero value than the lower threshold value, there is no sound. It is determined that it is not data. In the audio data 141, 0000H (hexadecimal number) indicates a mute state when the audio output level is zero, and XXXH (hexadecimal number) indicates that the audio output level is an arbitrary value.

  FIG. 6C shows a waveform of the audio data 141 output from the D / A unit 117. A period B indicates a mute state period, and a period D is a fade-in period. The audio data 141 in the period D is a period that gradually increases from the mute state of the 0000H value (hexadecimal number) to the arbitrary value XXXXH value (hexadecimal number). FIG. 6D shows the CPU clock 136. Period C is a period in which the clock is stopped, and period E is a period in which the clock is restarted.

  The data comparator 104 samples the peak hold value 131 (P) and the bottom hold value 131 (B) of the A / D data 131 at regular intervals during the period B in FIG. Then, the data comparator 104 compares the predetermined threshold set in advance by the SPI unit 108 with the peak hold value 131 (P) of the sampled A / D data and the bottom hold value 131 (B) of the A / D data. .

  In this embodiment, both the peak hold value 131 (P) and the bottom hold value 131 (B) are zero values from the threshold value continuously for 10 milliseconds in the period shown from T3 to T4 in FIG. If the level is far from the CPU, the CPU clock stop control signal 133 of the data comparator 104 is shifted from the high level to the low level.

  In the period E, the CG unit 107 detects the falling edge of the CPU clock stop control signal 133 and restarts the clock supply of the CPU unit 109. In the period indicated by period D, the output side serial data signal 137 processed by the CPU chip 102 is transferred to the AD / DA chip output side PCM unit 113, and then the PCM output data 138 is sequentially output to the output data generator 114. To do.

  The output data generator 114 raises the level of the PCM output data 138 step by step from the 0000H value (hexadecimal number). In this embodiment, fade-in data is generated by multiplying the PCM output data 138 by a multiplication constant 326 larger than 1 step by step for every 44.1 kHz period, and the D / A section 117 is output as output data 139. Is output to the selector 116 in the previous stage.

  When the multiplication result (output data 139) exceeds the PCM output data 138, the low level of the switching timing signal 144 is output to the output switching control unit 115. The selector unit 116 switches from the output data generator 114 side to the PCM output side in response to a switching signal 140 signal from the output switching control unit 115.

  A period indicated by a period C is the same as the period C in FIG. 3, and the clock of the CPU unit 109 is stopped. A period indicated by a period E indicates a period in which the falling edge of the CPU clock stop control signal 133 is detected and the clock supply of the CPU unit 109 is resumed.

  As described above, according to the present embodiment, it is possible to suppress the reproduction of unnecessary audio data that occurs when the CPU clock is stopped during reproduction of silence data. This is because the output data generator 114, the output switching control unit 115, and the selector unit 116 are provided in the preceding stage of the D / A unit 117, and the CPU clock stop control signal 133 that is output when silence data is detected is used. This is because the audio data 141 is faded out.

  Since the L-ch analog signal 142 and the R-ch analog signal 143 itself, which are output data of the D / A unit 117, are gradually reduced and faded out, the output of the D / A unit 117 generated immediately after the CPU clock is stopped. There is no potential difference, and no loud noise is generated from the speaker.

  In addition, by adopting the configuration of the embodiment, there is an effect of reducing the mute circuit realized by adding an external transistor to the output stage of the D / A unit 117. In addition, since silence data is detected when the source of the audio analog signal is switched, the time until the CPU clock stops can be shortened, and the current consumption can be reduced. Here, the source switching is, for example, switching of an audio analog signal input source from a compact disc playback device to a portable digital audio playback device.

  Normally, in the fade-out process, 2048-byte audio data is stored in the RAM, and signal processing is performed on the stored audio data. However, in the present embodiment, the calculation for creating the fade-out data and the fade-out data is performed at a cycle of 44.1 kHz in units of 32 bits, so (2048 (Byte) / 4) × (1 / 44.1 kHz) = 11.6 msec. There is also an effect of shortening the time.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 100 Audio | voice reproduction apparatus 101 AD / DA chip 102 CPU chip 103 A / D part 104 Data comparator 105 AD / DA chip input side PCM part 106 CPU chip input side PCM part 107 CG part 108 SPI part 109 CPU part 110 ROM part 111 RAM unit 112 CPU chip output side PCM unit 113 AD / DA chip output side PCM unit 114 Output data generator 115 Output switching control unit 116 Selector unit 117 D / A unit 118 Frequency divider 130 AUX signal input 131 A / D data 131 (P) Peak hold value 131 (B) Bottom hold value 132 Input side serial data signal 133 CPU clock stop control signal 134 Serial communication signal 135 Internal bus 136 CPU clock 137 Output side serial data signal 13 8 PCM output data 139 Output data 140 Switching signal 141 Audio data 142 L-ch analog signal 143 R-ch analog signal 144 Switching timing signal 301 Edge detector 302 F / F input selector 303 F / F
304 Multiplier 305 Sequencer 306 Comparator 321 Selector Output 322 Edge Detection Signal 323 Multiplication Clock 324 Clock 325 Comparator Output Signal 326 Multiplication Constant 327 Comparison Data 328 Divided Clock

Claims (14)

An audio reproduction device that is supplied with a clock and audio data and reproduces an analog audio signal obtained by analogizing the audio data using the clock,
A data comparator that generates a clock stop signal when the audio data is equal to a predetermined threshold or closer to a zero value than the threshold;
In response to the clock stop signal, an output data generation unit that generates fade-out data that gradually decreases the audio data in a zero value direction;
In response to the clock stop signal, an output switching control unit that switches from the audio data to the fade-out data;
A clock controller for stopping the clock in response to the clock stop signal;
An audio playback device comprising:   The audio reproduction device according to claim 1, wherein the clock control unit stops the clock after the fade-out data reaches a zero value.   The said data comparator produces | generates the said clock stop signal, when both the peak hold value and the bottom hold value of the said audio | voice data are equal to a predetermined threshold value, or it is closer to zero value than a threshold value. Audio playback device.   The data comparator samples the peak hold value and the bottom hold value at a predetermined interval, and the peak hold value and the bottom hold value are equal to or equal to the threshold value continuously for a predetermined period. 4. The audio reproduction device according to claim 3, wherein the clock stop signal is generated when the two are close. The data comparator, when the peak hold value and the bottom hold value of the audio data has transitioned from a zero value to a value farther from a zero value than a predetermined threshold, the level of the clock stop signal is transitioned,
The output data generation unit generates fade-in data that gradually increases the audio data according to the transition of the clock stop signal,
The output switching control unit switches to the fade-in data according to the transition of the clock stop signal,
The audio reproduction device according to claim 1, wherein the clock control unit resumes the supply of the clock in response to transition of the clock stop signal. The output data generation unit
A latch circuit that latches the audio data in response to the clock stop signal;
An arithmetic circuit for generating the fade-out data by multiplying the audio data latched in response to the clock stop signal by a value smaller than 1 at regular intervals;
The sound reproducing device according to claim 1, comprising: The latch circuit latches the audio data according to the transition of the clock stop signal,
6. The audio reproduction device according to claim 5, wherein the arithmetic circuit generates the fade-in data by multiplying the audio data latched in response to the transition of the clock stop signal by a value greater than 1 every predetermined period. . Generating a clock stop signal when the audio data is equal to a predetermined threshold or closer to zero than the threshold;
In response to the clock stop signal, fade-out data that gradually decreases the audio data in a zero value direction is generated, the audio data is switched from the audio data to the fade-out data, and the fade-out data is converted to analog and reproduced. Audio playback method to stop   The audio reproduction method according to claim 8, wherein the clock is stopped after the fade-out data reaches a zero value.   9. The audio reproduction method according to claim 8, wherein the clock stop signal is generated when both the peak hold value and the bottom hold value of the audio data are equal to a predetermined threshold value or closer to a zero value than the threshold value.   When the peak hold value and the bottom hold value are sampled at a predetermined interval, and the peak hold value and the bottom hold value are continuously equal to the threshold value or closer to the zero value than the threshold value for a predetermined period, the clock The audio reproduction method according to claim 10, wherein a stop signal is generated. When the peak hold value and the bottom hold value of the audio data transition from a zero value to a value farther from a zero value than a predetermined threshold, the level of the clock stop signal is transitioned,
9. The fade-in data that increases the audio data stepwise in response to the transition of the clock stop signal is generated, the fade-in data is analogized and reproduced, and the supply of the clock is resumed. Audio playback method.   9. The fade-out data is generated by latching the audio data in accordance with the clock stop signal and multiplying the audio data latched in accordance with the clock stop signal by a value smaller than 1 at a constant period. The audio playback method described in 1.   The audio data is latched in response to the transition of the clock stop signal, and the audio data latched in response to the transition of the clock stop signal is multiplied by a value greater than 1 at regular intervals, thereby the fade-in data is The sound reproducing device according to claim 12, which is generated.

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