JP2013153384A - Signal transmitting device and signal transmitting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmitting device capable of transmitting signals at high speed while reducing noise generated in a power supply.SOLUTION: A signal transmitting device according to the present invention includes: a plurality of flip-flops FF1-FFn that respectively store and output pieces of data DATA1-DATAn in accordance with clocks CLK1-CLKn supplied thereto; delay circuits 11_1-11_n that are provided so as to respectively correspond to the flip-flops and delay the clocks CLK1-CLKn to be supplied to the corresponding flip-flops; a comparator COMP that compares a voltage VDD of a power supply line with a reference voltage Vref; and a counter CNT_A that changes its count value if the voltage VDD of the power supply line exceeds the reference voltage Vref. The delay circuits 11_1-11_n delay the clocks to be supplied to the corresponding flip-flops FF1-FFn, in accordance with the count value of the counter CNT_A.

Description

  The present invention relates to a signal transmission device and a signal transmission method, and more particularly, to a signal transmission device and a signal transmission method that can reduce noise caused by signal transmission.

  Recent products such as computers and portable devices can dramatically process a large amount of data, and their performance has been dramatically improved. In order to process a large amount of data at high speed, it is necessary to transmit signals between LSIs at high speed. For this purpose, it is necessary to increase the amount of data transmitted at one time by increasing the number of bits of signal transmission between LSIs (increasing the number of channels).

  Patent Document 1 discloses a circuit design method for a semiconductor device that can suppress noise generated in a branch power supply line in a short time. Patent Document 2 discloses a technique related to a power supply noise measurement circuit that can evaluate a frequency component of power supply noise that affects the performance in the circuit by using a cross-correlation function.

JP 2000-285146 A JP 2008-224255 A

  However, if signal transmission between LSIs is made multi-bit in order to speed up signal transmission between LSIs, and these signals are transmitted simultaneously, there is a problem that noise generated in the power source increases.

  In view of the above problems, an object of the present invention is to provide a signal transmission device and a signal transmission method capable of transmitting a signal at high speed while reducing noise generated in a power supply.

  A signal transmission device according to the present invention is adapted to correspond to each of a plurality of flip-flops that are supplied with power from a power line and store and output data according to a supplied clock. A delay circuit that delays a clock supplied to each of the flip-flops, a comparator that compares the voltage of the power supply line with a reference voltage, and the voltage of the power supply line exceeds the reference voltage Each of the delay circuits delays the clock supplied to each of the flip-flops according to the count value of the counter.

  A signal transmission method according to the present invention is a signal transmission method using a plurality of flip-flops that are supplied with power from a power supply line and store and output data according to a supplied clock. The voltage is compared with the reference voltage, and the voltage is counted when the voltage of the power supply line exceeds the reference voltage, and the clock supplied to each flip-flop is delayed according to the count value.

  According to the present invention, it is possible to provide a signal transmission device and a signal transmission method capable of transmitting a signal at high speed while reducing noise generated in a power supply.

1 is a block diagram showing a signal transmission device according to a first exemplary embodiment; FIG. 3 is a diagram for explaining an operation of the signal transmission device according to the first exemplary embodiment; FIG. 3 is a diagram for explaining an operation of the signal transmission device according to the first exemplary embodiment; 3 is a flowchart for explaining an operation of the signal transmission apparatus according to the first exemplary embodiment; 3 is a timing chart illustrating an operation before clock adjustment of the signal transmission device according to the first exemplary embodiment; 3 is a timing chart illustrating an operation after clock adjustment of the signal transmission device according to the first exemplary embodiment; It is a block diagram which shows the comparative example of a signal transmission apparatus. 6 is a timing chart for explaining the operation of the signal transmission apparatus shown in FIG. 5 (at the time of 1-bit operation). 6 is a timing chart for explaining the operation of the signal transmission apparatus shown in FIG. 5 (during multi-bit operation). It is a figure which shows the received waveform in the signal transmission apparatus shown in FIG. 5 (when noise is small). It is a figure which shows the received waveform in the signal transmission apparatus shown in FIG. 5 (when noise is large). FIG. 3 is a block diagram showing a signal transmission device according to a second exemplary embodiment. FIG. 10 is a diagram for explaining an operation of the signal transmission device according to the second exemplary embodiment; FIG. 10 is a diagram for explaining an operation of the signal transmission device according to the second exemplary embodiment; 6 is a timing chart illustrating an operation before clock adjustment of the signal transmission device according to the second exemplary embodiment; 6 is a timing chart illustrating an operation after clock adjustment of the signal transmission device according to the second exemplary embodiment;

<Embodiment 1>
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of the signal transmission apparatus according to the first embodiment. As shown in FIG. 1, the signal transmission apparatus according to the present embodiment includes a comparator COMP, a counter CNT_A, flip-flops FF1 to FFn, and delay circuits 11_1 to 11_n. Here, n is an integer of 2 or more.

  The flip-flops FF1 to FFn are supplied with power from the power supply line VDD, and store and output data DATA1 to DATAn according to the supplied clocks CLK1 to CLKn. For example, each of the flip-flops FF1 to FFn can store the data DATA1 to DATAn at the timing when each of the clocks CLK1 to CLKn rises, and then output the data DATA1 to DATAn at the timing when the clocks CLK1 to CLKn rise.

  The signal transmission apparatus according to this embodiment can be used on both the transmission side and the reception side. When the signal transmission device is used on the transmission side, for example, a buffer may be provided at the subsequent stage of the flip-flops FF1 to FFn. When the signal transmission device is used on the receiving side, a buffer may be provided in front of the flip-flops FF1 to FFn (see FIG. 5).

  In the signal transmission device according to this embodiment, a signal having the number of bits corresponding to the number of flip-flops FF1 to FFn can be transmitted and received. For example, when n = 8, since the number of flip-flops FF1 to FF8 is 8, the signal transmission device can transmit and receive an 8-bit signal.

  The delay circuits 11_1 to 11_n are provided so as to correspond to the flip-flops FF1 to FFn. The delay circuits 11_1 to 11_n generate the clocks CLK1 to CLKn supplied to the flip-flops FF1 to FFn, respectively, by delaying the supplied input clock CLK. Each delay circuit 11_1 to 11_n includes delay elements D1 to Dn and selectors SEL1 to SELn. Each delay element D1 to Dn delays the supplied input clock CLK, and outputs the delayed clock to the selectors SEL1 to SELn, respectively. Each of the selectors SEL1 to SELn inputs the input clock CLK to one input, the clock delayed by the delay elements D1 to Dn to the other input, and inputs the input clock CLK or the delayed clock according to the signals A1 to An. Select and output to the flip-flops FF1 to FFn as clocks CLK1 to CLKn.

  The comparator COMP compares the voltage VDD of the power supply line with the reference voltage Vref. When the voltage VDD of the power supply line exceeds the reference voltage Vref, a signal (for example, a high level signal) is output to the counter CNT_A. When the power supply VDD includes large noise, LSIs connected to the same power supply line may malfunction, or noise may be radiated into the space as electromagnetic waves and affect other electronic devices. In the signal transmission apparatus according to the present embodiment, it is possible to detect whether the power supply VDD contains noise of a predetermined level or more by comparing the preset reference voltage Vref with the voltage VDD of the power supply line. it can. Here, the reference voltage Vref set in advance can be set to a value lower than a voltage at which noise included in the power supply may adversely affect the LSI or the like.

  The counter CNT_A counts when the voltage VDD of the power supply line exceeds the reference voltage Vref. For example, the comparator COMP outputs a high level signal to the counter CNT_A when the voltage VDD of the power supply line exceeds the reference voltage Vref. The counter CNT_A counts up when a high level signal is output from the comparator COMP. The counter CNT_A outputs signals A1 to An to the delay circuits 11_1 to 11_n according to the count value of the counter CNT_A. Accordingly, each of the delay circuits 11_1 to 11_n can delay the clock supplied to each of the flip-flops FF1 to FFn according to the count value of the counter CNT_A.

  Here, the number of bits of the counter CNT_A is the same as the number of flip-flops FF1 to FFn, and each bit of the counter CNT_A has a one-to-one correspondence with each flip-flop FF1 to FFn. The delay circuits 11_1 to 11_n delay the clocks supplied to the flip-flops FF1 to FFn corresponding to the bits in the “1” state among the bits of the counter CNT_A. At this time, the signals A1 to An are output from the counter CNT_A to the delay circuits 11_1 to 11_n corresponding to the bits in the “1” state.

  Specifically, for example, when n = 8, the number of bits of the counter CNT_A is 8. At this time, for example, the least significant bit of the counter CNT_A corresponds to the signal A1 output to the delay circuit 11_1, the second least significant bit corresponds to the signal A2 output to the delay circuit 11_2, and the counters are sequentially counted thereafter. It is assumed that the bit of CNT_A corresponds to the signal output to the delay circuit, and the most significant bit corresponds to the signal A8 output to the delay circuit 11_8. For example, when the value of the counter CNT_A is “00000001” (that is, when the least significant bit is “1”), the counter CNT_A outputs a high-level signal A1 to the delay circuit 11_1. Since the high-level signal is supplied as the signal A1, the selector SEL1 of the delay circuit 11_1 selects a clock obtained by delaying the input clock CLK by the delay element D1, and outputs the selected clock to the flip-flop FF1. Therefore, the delayed clock CLK1 is supplied to the flip-flop FF1.

  For example, when the value of the counter CNT_A is “00010001”, the counter CNT_A outputs the high-level signals A1 and A5 to the delay circuits 11_1 and 11_5, respectively. Since the high-level signal is supplied as the signal A1, the selector SEL1 of the delay circuit 11_1 selects a clock obtained by delaying the input clock CLK by the delay element D1, and outputs the selected clock to the flip-flop FF1. Similarly, since the high-level signal is supplied as the signal A5, the selector SEL5 of the delay circuit 11_5 selects a clock obtained by delaying the input clock CLK by the delay element D5 and outputs the selected clock to the flip-flop FF5. Therefore, the delayed clocks CLK1 and CLK5 are supplied to the flip-flops FF1 and F5, respectively.

  In the signal transmission device according to the present embodiment, the correspondence between each bit of the counter CNT_A and each of the flip-flops FF1 to FFn may be different from the above case. That is, each bit of the counter CNT_A and each flip-flop FF1 to FFn only need to correspond one-to-one, and the combination can be arbitrarily determined.

  Next, the operation of the signal transmission apparatus according to this embodiment will be described. First, the basic operation of the signal transmission apparatus according to this embodiment will be described. 2A and 2B are diagrams for explaining the operation of the signal transmission apparatus according to the present embodiment. The comparator COMP compares the voltage VDD of the power supply line with the reference voltage Vref, and when the voltage VDD of the power supply line exceeds the reference voltage Vref as shown by a broken line in FIG. 2A, a high level signal is output to the counter CNT_A. Is output. The counter CNT_A counts up the count value when a high level signal is output from the comparator COMP. When the count value of the counter CNT_A is counted up, a high level signal An is output to the delay circuit 11_n corresponding to the bit in the “1” state. Thereby, the selector SELn of the delay circuit 11_n selects the clock delayed by the delay element Dn and outputs it to the flip-flop FFn. Therefore, as shown in FIG. 2B, the clock CLKn supplied to the flip-flop FFn when the signal An is high level (An = 1) is supplied to the flip-flop FFn when the signal An is low level (An = 0). Delayed by the delay time td1 from the clock CLKn.

  In the signal transmission device according to the present embodiment, when the voltage VDD of the power supply line exceeds the reference voltage Vref, the count value of the counter CNT_A is counted up and supplied to the flip-flops FF1 to FFn according to the value of this counter The clocks CLK1 to CLKn to be delayed are delayed. In this way, the position of each clock is changed by delaying a predetermined clock, and the overlap of generated noise can be changed. Then, by optimizing the combination of the clocks that are delayed (that is, by using a delay pattern that reduces noise generated in the power supply), noise generated in the power supply can be suppressed.

  Hereinafter, the operation of the signal transmission apparatus according to the present embodiment will be described in detail. FIG. 3 is a flowchart for explaining the operation of the signal transmission apparatus according to this embodiment.

  When the clock is not adjusted, as shown in FIG. 4A, the clocks CLK1 to CLKn that are synchronized (that is, not subjected to delay processing) are supplied to the flip-flops FF1 to FFn. May contain large noise. That is, as indicated by a broken line in FIG. 4A, the voltage VDD of the power supply line may exceed the reference voltage Vref. In this case, LSIs connected to the same power supply line may malfunction, or noise may be radiated into the space as electromagnetic waves, affecting other electronic devices. Although FIG. 4A shows an example in which all of the clocks CLK1 to CLKn are synchronized, the timings of the clocks CLK1 to CLKn before clock adjustment are determined by the initial design, so the timings of the clocks CLK1 to CLKn are respectively It may be shifted.

  In the signal transmission apparatus according to the present embodiment, in order to suppress a large noise from being included in the voltage VDD of the power supply line, first, adjustment of the clock is started (step S1). That is, the comparator COMP is used to compare the power supply line voltage VDD with the reference voltage Vref to determine whether the power supply line contains noise (step S2). When noise is detected (step S2: Yes), a predetermined clock among the clocks CLK1 to CLKn is delayed using a delay circuit (step S3). At this time, the data DATA1 to DATAn supplied to the flip-flops FF1 to FFn are, for example, pseudo-random patterns or the like, and may be data unrelated to the actual operation, or may be data related to the actual operation. Good.

  For example, when n = 8, when the comparator COMP detects for the first time that the voltage VDD of the power supply line exceeds the reference voltage Vref, the count value of the counter CNT_A is “00000001”. At this time, assuming that the least significant bit of the count value corresponds to the flip-flop FF1 (delay circuit 11_1), a high level signal is output as the signal A1 from the counter CNT_A to the selector SEL1. Therefore, the delayed clock CLK1 is supplied to the flip-flop FF1.

  Then, in a state where the delayed clock CLK1 is supplied to the flip-flop FF1, the voltage VDD of the power supply line is again compared with the reference voltage Vref to determine whether the power supply line includes noise (step S2). . When the comparator COMP detects again that the voltage VDD of the power supply line has exceeded the reference voltage Vref (step S2: Yes), the count value of the counter CNT_A is “00000010”. At this time, if the second least significant bit of the count value corresponds to the flip-flop FF2 (delay circuit 11_2), a high level signal is output from the counter CNT_A to the selector SEL2 as the signal A2. Therefore, the delayed clock CLK2 is supplied to the flip-flop FF2. Then, in a state where the delayed clock CLK2 is supplied to the flip-flop FF2, the power supply line voltage VDD and the reference voltage Vref are compared again to determine whether the power supply line includes noise (step S2). . Thereafter, the above-described operation is repeated until no noise is detected in step S2.

  For example, when the count value of the counter CNT_A is “00000011”, the delayed clocks CLK1 and CLK2 are supplied to the flip-flop FF1 and the flip-flop FF2, respectively. The other clocks CLK3 to CLK8 are supplied to the other flip-flops FF3 to FF8.

  In the signal transmission device according to the present embodiment, for example, when n = 8, the count value of the counter CNT_A is counted from “00000000” to “11111111”, so that the clocks CLK1 to CLK8 are delayed in various patterns. Can do. Therefore, it is possible to automatically determine a delay pattern in which noise generated in the power source is reduced.

  When it is determined that the voltage VDD of the power line does not exceed the reference voltage Vref, that is, when the power line does not contain noise (No at Step S2), the clock adjustment is finished (Step S4). The signal transmission device shifts to normal operation (step S5). When the clock adjustment is completed, the delayed clock is fixed.

  FIG. 4B is a timing chart illustrating the operation of the signal transmission apparatus according to the present embodiment after the clock adjustment is completed. As shown in FIG. 4B, in the signal transmission apparatus according to the present embodiment, a predetermined clock among clocks CLK1 to CLKn supplied to flip-flops FF1 to FFn when the voltage VDD of the power supply line exceeds the reference voltage Vref. Can be suppressed from being generated in the power supply VDD. FIG. 4B shows an example in which noise generated in the power supply VDD can be suppressed by delaying the clock CLK2 by td1 with respect to the input clock CLK.

  Recent products such as computers and portable devices can dramatically process a large amount of data, and their performance has been dramatically improved. In order to process a large amount of data at high speed, it is necessary to transmit signals between LSIs at high speed. For this purpose, it is necessary to increase the amount of data transmitted at one time by increasing the number of bits of signal transmission between LSIs (increasing the number of channels). FIG. 5 is a block diagram showing a comparative example of a signal transmission device, and shows a signal transmission device in which signal transmission between LSIs is multi-bit. The signal transmission apparatus shown in FIG. 5 includes a transmission-side signal transmission apparatus 41 provided in a signal-transmitting LSI, and a reception-side signal transmission apparatus 42 provided in a signal-receiving LSI. .

  The signal transmission device 41 on the transmission side includes flip-flops FF1_a to FFn_a. The flip-flops FF1_a to FFn_a are supplied with power from the power supply line VDD_a and store and output data DATA1 to DATAn according to the supplied clocks CLK1_a to CLKn_a. For example, each of the flip-flops FF1_a to FFn_a can store the data DATA1 to DATAn at the timing when each clock CLK1_a to CLKn_a rises, and then output the data DATA1 to DATAn at the timing when the clock CLK1_a to CLKn_a rises.

  The respective data DATA1 to DATAn output from the respective flip-flops FF1_a to FFn_a pass through the buffers 51_1 to 51_n, the transmission lines 52_1 to 52_n (printed wiring board (PWB), cables, etc.), and the buffers 53_1 to 53_n. Then, the signal is supplied to each flip-flop FF1_b to FFn_b of the signal transmission device 42 on the receiving side.

  The flip-flops FF1_b to FFn_b included in the signal transmission device 42 on the reception side are supplied with power from the power supply line VDD_b and are output from the signal transmission device 41 on the transmission side according to the supplied clocks CLK1_b to CLKn_b. The data DATA1 to DATAn are stored and output. For example, each of the flip-flops FF1_b to FFn_b can store the data DATA1 to DATAn at a timing when each clock CLK1_b to CLKn_b rises, and then output the data DATA1 to DATAn at a timing when the clock CLK1_b to CLKn_b rises. The output data DATA1 to DATAn is taken into the LSI on the receiving side.

  However, if signal transmission between LSIs is made multi-bit in order to speed up signal transmission between LSIs, and these signals are transmitted simultaneously, there is a problem that noise generated in the power source increases. That is, in the signal transmission device 41 on the transmission side shown in FIG. 5, when the flip-flops FF1_a to FFn_a are simultaneously operated using the synchronized clocks CLK1_a to CLKn_a, the voltage VDD_a of the power supply line greatly fluctuates and is generated in the power supply. Noise may increase. Similarly, when the flip-flops FF1_b to FFn_b are simultaneously operated using the synchronized clocks CLK1_b to CLKn_b in the signal transmission device 42 on the receiving side, the voltage VDD_b of the power supply line greatly fluctuates, and noise generated in the power supply May be larger.

  FIG. 6A is a timing chart for explaining the operation (at the time of 1-bit operation) of the signal transmission apparatus shown in FIG. FIG. 6B is a timing chart for explaining the operation of the signal transmission device shown in FIG. 5 (during multi-bit operation). As shown in FIG. 6A, when the signal transmission device transmits a signal of only 1 bit, the number of operating flip-flops is one on each of the transmission side and the reception side. Noise generated in the power supply is small. On the other hand, when the signal transmission apparatus transmits a multi-bit (n-bit) signal as shown in FIG. 6B, there are n flip-flops that operate in synchronization with each other on the transmission side and the reception side. Here, the noise generated in the power supply is determined by the positional relationship between each clock and each data and their overlap, so that the fluctuation of the voltage VDD of the power supply line increases and the noise generated in the power supply may increase (see FIG. 6B).

  As described above, when the noise generated in the power supply increases, the operation margin of the LSI is reduced, which may cause malfunction of the device itself. That is, when the generated noise is small, there is no waveform distortion of the received waveform as shown in FIG. 7A, and a sufficient operation margin is secured, so that no malfunction occurs. Here, the received waveform is a waveform supplied to the buffer buffers 53_1 to 53_n or a waveform output from the flip-flops FF1_b to FFn_b. Reference numeral 60 denotes an LSI threshold voltage. On the other hand, when the generated noise is large, the waveform distortion of the received waveform is large as shown in FIG. 7B, and an operation margin is not ensured, so that there is a high possibility of malfunction. In recent years, the operating voltage has been lowered in the LSI, and the operating margin tends to be small. Therefore, the allowable noise amount is becoming small.

  In addition, noise generated in the power source is radiated as electromagnetic waves to a space through a transmission path such as a printed circuit board or a cable, which may cause other electronic devices to malfunction. There is a public standard for the problem of electromagnetic waves radiated to the space, and satisfying this standard is the shipping condition of products. This standard tends to be strengthened year by year.

  In order to solve such a problem, in the signal transmission device according to the present embodiment, the power supply line voltage VDD is monitored using the comparator COMP, and the power supply line voltage VDD exceeds the reference voltage Vref. A predetermined clock among the clocks CLK1 to CLKn supplied to the flip-flops FF1 to FFn is delayed. In this way, the position of each clock is changed by delaying a predetermined clock, and the overlap of generated noise can be changed. Then, by optimizing the combination of the clocks that are delayed (that is, by using a delay pattern that reduces noise generated in the power supply), noise generated in the power supply can be suppressed.

  Furthermore, in the signal transmission device according to the present embodiment, the counter CNT_A is counted each time the voltage VDD of the power supply line exceeds the reference voltage Vref. The number of bits of this counter is the same as the number of flip-flops, and each bit of the counter has a one-to-one correspondence with each flip-flop. Since the clock supplied to the flip-flops FF1 to FFn corresponding to the bits in the "1" state among the respective bits of the counter is delayed, generation of noise in the power supply is automatically suppressed. Can do.

  With the invention according to the present embodiment described above, it is possible to provide a signal transmission device and a signal transmission method capable of transmitting signals at high speed while reducing noise generated in a power supply.

<Embodiment 2>
Next, a second embodiment of the present invention will be described. FIG. 8 is a block diagram showing the signal transmission apparatus according to the present embodiment. The signal transmission apparatus according to the present embodiment is provided with two counters as compared with the signal transmission apparatus (see FIG. 1) described in the first embodiment, and each delay circuit 21_1 to 21_n includes two delay elements. The difference is that it has two selectors. The rest of the configuration is the same as that of the signal transmission apparatus described in the first embodiment, and thus redundant description is omitted as appropriate.

  As shown in FIG. 8, the signal transmission device according to the present embodiment includes a comparator COMP, counters CNT_A and CNT_B, flip-flops FF1 to FFn, and delay circuits 21_1 to 21_n. Here, n is an integer of 2 or more.

  Since the flip-flops FF1 to FFn are the same as the flip-flops FF1 to FFn described in the first embodiment, redundant description is omitted.

  The delay circuits 21_1 to 21_n are provided so as to correspond to the flip-flops FF1 to FFn. The delay circuits 21_1 to 21_n generate clocks CLK1 to CLKn supplied to the flip-flops FF1 to FFn, respectively, by delaying the supplied input clock CLK. Each delay circuit 21_1 to 21_n includes delay elements D_A1 to D_An, D_B1 to D_Bn, and selectors SEL_A1 to SEL_An, SEL_B1 to SEL_Bn.

  Each delay element D_A1 to D_An delays the supplied input clock CLK, and outputs the delayed clock to the selectors SEL_A1 to SEL_An, respectively. Each selector SEL_A1 to SEL_An inputs the input clock CLK to one input, the clock delayed by the delay elements D_A1 to D_An to the other input, and selects the input clock CLK or the delayed clock according to the signals A1 to An To do.

  Each delay element D_B1 to D_Bn delays the clock selected by the selectors SEL_A1 to SEL_An, and outputs the delayed clock to the selectors SEL_B1 to SEL_Bn, respectively. Each of the selectors SEL_B1 to SEL_Bn receives a clock selected by the selectors SEL_A1 to SEL_An at one input and a clock delayed by the delay elements D_B1 to D_Bn to the other input, and selects the selector SEL_A1 according to the signals B1 to Bn. The clock selected by SEL_An or the clock delayed by the delay elements D_B1 to D_Bn is selected and output to the flip-flops FF1 to FFn as clocks CLK1 to CLKn.

  The comparator COMP compares the voltage VDD of the power supply line with the reference voltage Vref. When the voltage VDD of the power supply line exceeds the reference voltage Vref, a signal (for example, a high level signal) is output to the counter CNT_A and the counter CNT_B. In the signal transmission apparatus according to the present embodiment, first, the counter CNT_A is used to count when the voltage VDD of the power supply line exceeds the reference voltage Vref. When the counter CNT_A overflows, the counter CNT_B is used for counting. For example, the counter CNT_B can start counting when a signal 25 for notifying that the counter CNT_A has overflowed is input from the counter CNT_A.

  For example, the comparator COMP outputs a high level signal when the voltage VDD of the power supply line exceeds the reference voltage Vref. The counters CNT_A and CNT_B count up when a high level signal is output from the comparator COMP. The counter CNT_A outputs signals A1 to An to the delay circuits 21_1 to 21_n according to the count value of the counter CNT_A. Further, the counter CNT_B outputs signals B1 to Bn to the delay circuits 21_1 to 21_n according to the count value of the counter CNT_B. Thereby, each of the delay circuits 21_1 to 21_n can delay the clocks CLK1 to CLKn supplied to the respective flip-flops FF1 to FFn according to the count values of the counters CNT_A and CNT_B.

  Here, the number of bits of the counter CNT_A is the same as the number of flip-flops FF1 to FFn, and each bit of the counter CNT_A has a one-to-one correspondence with each flip-flop FF1 to FFn. The delay circuits 21_1 to 21_n use the delay elements D_A1 to D_An to delay the clocks CLK1 to CLKn supplied to the flip-flops FF1 to FFn corresponding to the bits whose counter CNT_A is in the “1” state. . At this time, the signals A1 to An are output from the counter CNT_A to the selectors SEL1_A1 to SEL1_An of the delay circuits 21_1 to 21_n corresponding to the bits in the “1” state.

  Similarly, the number of bits of the counter CNT_B is the same as the number of flip-flops FF1 to FFn, and each bit of the counter CNT_B corresponds to each flip-flop FF1 to FFn on a one-to-one basis. The delay circuits 21_1 to 21_n use the delay elements D_B1 to D_Bn to delay the clocks CLK1 to CLKn supplied to the flip-flops FF1 to FFn corresponding to the bits whose counter CNT_B is in the “1” state. . At this time, the signals B1 to Bn are output from the counter CNT_B to the selectors SEL1_B1 to SEL1_Bn of the delay circuits 21_1 to 21_n corresponding to the bits in the “1” state.

  Also in the signal transmission apparatus according to the present embodiment, each bit of the counter CNT_A and each flip-flop FF1 to FFn only need to correspond one-to-one, and the combination can be arbitrarily determined. Similarly, each bit of the counter CNT_B and each flip-flop FF1 to FFn only need to correspond one-to-one, and the combination can be arbitrarily determined.

  Next, the operation of the signal transmission apparatus according to this embodiment will be described. First, the basic operation of the signal transmission apparatus according to this embodiment will be described. 9A and 9B are diagrams for explaining the operation of the signal transmission device according to the present exemplary embodiment. The comparator COMP compares the voltage VDD of the power supply line with the reference voltage Vref. When the voltage VDD of the power supply line exceeds the reference voltage Vref as shown by a broken line in FIG. The signal is output.

  The counter CNT_A counts up the count value when a high level signal is output from the comparator COMP. The counter CNT_A outputs a high-level signal An to the delay circuit 21_n corresponding to the bit in the “1” state among the respective bits of the count value. Thereby, the selector SEL_An of the delay circuit 21_n selects the clock delayed by the delay element D_An and outputs it to the selector SEL_Bn. When Bn = 0, the clock delayed by the delay element D_An is supplied to the flip-flop FFn. Therefore, as shown in FIG. 9B, when the signal An is high level and the signal Bn is low level (An = 1, Bn = 0), the clock CLKn supplied to the flip-flop FFn is when the signals An, Bn are low level. Delayed by a delay time td1 from the clock CLKn supplied to the flip-flop FFn at (An = 0, Bn = 0).

  The counter CNT_B counts up the count value when a high level signal is output from the comparator COMP. The counter CNT_B outputs a high-level signal Bn to the delay circuit 21_n corresponding to the bit in the “1” state among the bits of the count value. Thereby, the selector SEL_Bn of the delay circuit 21_n selects the clock delayed by the delay element D_Bn and outputs it to the flip-flop FFn. Note that the counter CNT_B is counting means that the counter CNT_A has already overflowed. Therefore, in this case, a high-level signal is output as the signal An from the counter CNT_A to all of the delay circuits 21_1 to 21_n. For this reason, all the selectors SEL_A1 to SEL_An select the clocks delayed by the delay elements D_A1 to D_An and output them to the selectors SEL_B1 to SEL_Bn. Therefore, as shown in FIG. 9B, when the signal An is at the high level and the signal Bn is at the high level (An = 1, Bn = 1), the clock CLKn supplied to the flip-flop FFn has the signals An and Bn at the low level. In this case (An = 0, Bn = 0), the delay time td1 + td2 is delayed from the clock CLKn supplied to the flip-flop FFn.

  In the signal transmission device according to the present embodiment, when the voltage VDD of the power supply line exceeds the reference voltage Vref, the count values of the counters CNT_A and CNT_B are counted up, and the flip-flops FF1 to FFn according to the value of the counter The clocks CLK1 to CLKn supplied to are delayed. In this way, the position of each clock is changed by delaying a predetermined clock, and the overlap of generated noise can be changed. Then, by optimizing the combination of the clocks that are delayed (that is, by using a delay pattern that reduces noise generated in the power supply), noise generated in the power supply can be suppressed.

  As shown in FIG. 10A, when the clock is not adjusted, the clocks CLK1 to CLKn that are synchronized (that is, not subjected to delay processing) are supplied to the flip-flops FF1 to FFn. May contain large noise. That is, as indicated by a broken line in FIG. 10A, the voltage VDD of the power supply line may exceed the reference voltage Vref. In this case, LSIs connected to the same power supply line may malfunction, or noise may be radiated into the space as electromagnetic waves, affecting other electronic devices.

  In the signal transmission apparatus according to the present embodiment, the clock is adjusted in order to suppress large noise from being included in the voltage VDD of the power supply line. FIG. 10B is a timing chart illustrating the operation of the signal transmission apparatus according to the present embodiment after the clock adjustment is completed. As shown in FIG. 10B, in the signal transmission device according to the present embodiment, a predetermined clock among clocks CLK1 to CLKn supplied to flip-flops FF1 to FFn when the voltage VDD of the power supply line exceeds the reference voltage Vref. Can be suppressed from being generated in the power supply VDD. In FIG. 10B, an example in which noise generated in the power supply VDD can be suppressed by delaying the clock CLK1 by td1 + td2 with respect to the input clock CLK and further delaying the clocks CLK2 to CLKn by td1 with respect to the input clock CLK. Is shown. Here, the fact that the counter CNT_B is counting means that the counter CNT_A has already overflowed. Therefore, a high level signal is output as the signal An from the counter CNT_A to all of the delay circuits 21_1 to 21_n.

  For example, when n = 8, the count value of the counter CNT_A is counted from “00000000” to “11111111”. Then, after the counter CNT_A overflows, the count value of the counter CNT_B is counted from “00000000” to “11111111”.

  As described above, in the signal transmission device according to the present embodiment, a plurality of counters CNT_A and CNT_B are provided, and each delay circuit 21_1 to 21_n has two delay elements D_A1 to D_An and D_B1 to D_Bn and two selectors SEL_A1 to SEL_A1. SEL_An and SEL_B1 to SEL_Bn are provided. Therefore, more combinations of delay patterns than the signal transmission apparatus described in Embodiment 1 can be created, and clocks CLK1 to CLKn delayed in various patterns can be generated. Therefore, the noise generated in the power supply can be suppressed more reliably than the signal transmission apparatus according to the first embodiment.

  With the invention according to the present embodiment described above, it is possible to provide a signal transmission device and a signal transmission method capable of transmitting signals at high speed while reducing noise generated in a power supply.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the number of counters, delay elements, and selectors is one in Embodiment 1 and two in Embodiment 2, but the number of counters, delay elements, and selectors may be three or more.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and can be made by those skilled in the art within the scope of the invention of the claims of the claims of the present application. It goes without saying that various modifications, corrections, and combinations are included.

11_1 to 11_n, 21_1 to 21_n Delay circuit 41 Transmission-side signal transmission device 42 Reception-side signal transmission device 51_1 to 51_n Buffer 52_1 to 52_n Transmission path 53_1 to 53_n Buffer

Claims (9)

A plurality of flip-flops that store power and output data according to the supplied clock, together with power supplied from the power line.
A delay circuit provided to correspond to each of the plurality of flip-flops and delaying a clock supplied to each of the flip-flops;
A comparator for comparing the voltage of the power line with a reference voltage;
A counter that counts when the voltage of the power supply line exceeds the reference voltage,
Each delay circuit delays a clock supplied to each flip-flop according to a count value of the counter.
Signal transmission device. The number of bits of the counter is the same as the number of flip-flops;
Each bit of the counter corresponds to each flip-flop,
The signal transmission device according to claim 1.   The signal transmission device according to claim 2, wherein a clock delayed by the delay circuit is supplied to a flip-flop corresponding to a bit in a state of “1” among the bits of the counter. The counter includes a first counter and a second counter that starts counting when the count value of the first counter overflows,
Each of the delay circuits includes a first delay element that delays the clock, and a second delay element that further delays the clock delayed by the first delay element,
The first delay element delays a clock supplied to each flip-flop according to a count value of the first counter,
The second delay element delays a clock supplied to each flip-flop according to a count value of the second counter;
The signal transmission device according to claim 1. The number of bits of the first and second counters is the same as the number of flip-flops, respectively.
Each bit of the first and second counters corresponds to the respective flip-flop,
The signal transmission device according to claim 4. The clock delayed by the first delay element is supplied to the flip-flop corresponding to the bit in the “1” state among the bits of the first counter,
The clock delayed by the second delay element is supplied to the flip-flop corresponding to the bit in the “1” state among the bits of the second counter.
The signal transmission device according to claim 5. The delay circuit includes a delay element that delays an input clock, and a selector provided at a subsequent stage of the delay element,
The selector is configured to selectively output the clock delayed by the delay element and the input clock,
The counter outputs a signal for causing the selector corresponding to the bit in the “1” state to select the clock delayed by the delay element;
The signal transmission device according to claim 1. A signal transmission method using a plurality of flip-flops that supply power from a power line and store and output data according to a supplied clock,
Compare the voltage of the power line with a reference voltage,
Counting when the voltage of the power line exceeds the reference voltage,
Delaying the clock supplied to each flip-flop according to the count value,
Signal transmission method. The number of bits of the counter value is the same as the number of flip-flops,
Each bit of the counter value corresponds to each of the flip-flops,
The signal transmission method according to claim 8.

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