JP2013152677A - Information processor and start control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor which can control its analog circuit at start time by utilizing the internal status or environmental status of the information processor which is obtained at the time when the information processor was previously operating.SOLUTION: An information processor 1 stores, in a nonvolatile start information memory 13, start information 130 in which at least one of the internal status and environment status of the information processor 1, which are measured when the information processor 1 is operating, is reflected. The information processor 1 controls an analog circuit 12 at the time of future start according to the start information 130 stored in the start information memory 13.

Description

  The present application relates to an information processing apparatus having a CPU, for example, activation control of the information processing apparatus.

  Activation information used when an information processing apparatus having a CPU (Central Processing Unit) is activated may be held in a rewritable nonvolatile memory (eg flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory)). Are known. An information processing apparatus having a CPU may be called a microcomputer or a microcontroller. The CPU is also called a microprocessor or MPU (Micro-Processing Unit).

  Patent Documents 1 and 2 describe holding startup information in a nonvolatile memory for controlling an analog circuit (eg, an internal voltage generation circuit, a clock circuit) built in the information processing device when the information processing device is started. ing. Patent Documents 1 and 2 describe that activation information held in a nonvolatile memory can be rewritten by a user.

  Specifically, the information processing apparatus described in Patent Document 1 stores activation information related to a CPU reset voltage specified by a user in a nonvolatile memory. The information processing apparatus described in Patent Document 1 sets the CPU reset voltage according to the activation information held in the nonvolatile memory.

  The information processing apparatus described in Patent Literature 2 stores activation information related to a clock stabilization time designated by a user in a nonvolatile memory. Then, the information processing apparatus described in Patent Document 2 is configured to output clocks of clock circuits (eg crystal oscillator, PLL (Phase Locked Loop) circuit) at the time of starting the information processing apparatus according to the startup information held in the nonvolatile memory. Adjust the waiting time until the signal stabilizes.

JP 2007-305053 A JP 2004-355362 A

  However, the information processing apparatuses described in Patent Documents 1 and 2 are measured when the information processing apparatus has been operating in the past when controlling an analog circuit incorporated in the information processing apparatus at the time of starting the information processing apparatus. There is a problem that the internal state or environmental state of the information processing apparatus is not used. Other problems / problems or novel features will become apparent from the description of the present specification and the accompanying drawings.

  In one embodiment, the information processing apparatus stores in the nonvolatile memory startup information that reflects at least one of the internal state and the environmental state of the information processing apparatus measured when the information processing apparatus is operating. In the future startup, the analog circuit is controlled according to the startup information stored in the nonvolatile memory.

  In the above-described embodiment, when the information processing apparatus is activated, the analog circuit can be controlled using the internal state or the environmental state of the information processing apparatus when the information processing apparatus has been operating in the past.

1 is a block diagram illustrating a configuration example of an information processing device according to a first embodiment. 3 is a flowchart illustrating an example of a startup procedure of the information processing apparatus according to the first embodiment. 10 is a table relating to an example of control of an internal voltage when the information processing apparatus according to the second embodiment is started. 6 is a graph relating to an example of control of an internal voltage when the information processing apparatus according to the second embodiment is started. 6 is a circuit diagram illustrating a configuration example of an analog circuit (specifically, an internal power supply circuit) included in an information processing apparatus according to Embodiment 2. FIG. FIG. 6 is a circuit diagram illustrating a configuration example of a temperature characteristic adjustment circuit illustrated in FIG. 5. 6 is a timing chart illustrating an example of a startup procedure of the information processing apparatus according to the second embodiment. 14 is a flowchart illustrating an example of a startup procedure of the information processing apparatus according to the third embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of an analog circuit (specifically, an internal power supply circuit) included in the information processing apparatus according to the fourth embodiment. 10 is a table relating to a control example of a phase compensation capacity at the time of activation of the information processing apparatus according to the fourth embodiment. 10 is a circuit diagram illustrating a configuration example of an analog circuit control unit included in an information processing apparatus according to Embodiment 4; FIG. 12 is a truth table regarding the analog circuit control unit shown in FIG. 11. 10 is a timing chart illustrating an example of a startup procedure of the information processing apparatus according to the fourth embodiment. 10 is a timing chart illustrating an example of a startup procedure of the information processing apparatus according to the fifth embodiment. FIG. 18 is a block diagram illustrating a configuration example of a startup information memory included in an information processing apparatus according to a sixth embodiment. FIG. 10 is a block diagram illustrating a configuration example of an information processing device according to a seventh embodiment.

  Hereinafter, specific embodiments will be described in detail with reference to the drawings. In each drawing, the same or corresponding elements are denoted by the same reference numerals, and redundant description is omitted as necessary for clarification of the description.

<Embodiment 1>
FIG. 1 shows a configuration example of an information processing apparatus 1 according to the present embodiment. The information processing apparatus 1 has a main block 11 including a CPU 111. The main block 11 may include other elements coupled with the CPU 111. For example, the main block 11 may include a RAM (Random Access Memory), a DMA (Direct Memory Access) controller, a flash memory module, and the like. That is, the information processing apparatus 1 according to the present embodiment is a computer system called a microcomputer or a microcontroller.

  Analog circuit 12 is electrically coupled to main block 11. The analog circuit 12 supplies signals (signal group) necessary for the operation of the main block 11 to the main block 11. In the example of FIG. 1, the analog circuit 12 includes an internal power supply circuit 121 and a clock circuit 122. The internal power supply circuit 121 generates an internal voltage supplied to the main block 11 from an external voltage. Typically, the clock circuit 122 generates a plurality of internal voltages having different voltage levels required in the main block 11. The clock circuit 122 has a clock generation function and supplies the generated clock signal to the main block 11. Typically, the clock circuit 122 generates a plurality of clock signals having different frequencies required in the main block 11. For example, the clock circuit 122 may have a PLL (Phase Locked Loop) circuit and generate a clock signal based on an external clock supplied from the outside of the information processing apparatus 1. Note that the configuration in FIG. 1 is an example, and the analog circuit 12 may include other analog circuits in addition to the power supply circuit 121 and the clock circuit 122.

  The information processing apparatus 1 stores in the activation information memory 13 activation information 130 that reflects at least one of the internal state and the environmental state of the information processing apparatus 1 measured when the information processing apparatus 1 is activated. . Then, the information processing apparatus 1 controls the analog circuit 12 according to the activation information 130 stored in the activation information memory 13 at the future activation. The activation information memory 13 is a rewritable nonvolatile memory. The activation information memory 13 may be a flash memory, for example. Further, the boot information memory 13 may be an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a magnetic recording medium such as a hard disk drive.

  The internal state of the information processing apparatus 1 reflected in the activation information 130 is, for example, (i) a voltage stabilization time until the output of the internal power supply circuit 121 is stabilized, and (ii) an output of the clock circuit 122 is stabilized. At least one of (iii) maximum current in the information processing apparatus 1, (iv) average current in the information processing apparatus 1, and (v) voltage drop in the information processing apparatus 1 Including. Further, the environmental state of the information processing apparatus 1 reflected in the activation information 130 includes, for example, at least one of (i) temperature and (ii) external voltage level.

  The activation information 130 is, for example, a measurement value of the internal state or the environmental state of the information processing apparatus 1. Further, the activation information may be a control value of the analog circuit 12 generated based on a measurement value of the internal state or the environmental state of the information processing apparatus 1. The control value of the analog circuit 12 may be a value suitable for arithmetic processing by the analog circuit control unit 15 or the analog circuit 12.

  In general, the range of operating conditions guaranteed by the information processing apparatus is wide. Therefore, a sufficiently large margin is set for various parameters (eg voltage stabilization time, clock stabilization time, maximum current) related to the start of the analog circuit of the information processing device in consideration of the worst operating conditions. . However, it is assumed that the information processing apparatus is used in a limited environment or used for a limited application. In addition, it is assumed that the operating condition when the information processing apparatus is activated is often the same as the operating condition when activated in the past. On the other hand, the information processing apparatus 1 according to the present embodiment activates the analog circuit 12 according to the activation information reflecting the internal state or the environmental state measured when the information processing apparatus 1 has been activated in the past. Time control can be implemented. Therefore, for example, the information processing apparatus 1 can perform start-up control of the analog circuit 12 that is adapted to the actual operating conditions of the information processing apparatus by eliminating unnecessary margins.

  For example, as the internal state measured when the information processing apparatus 1 has been activated in the past, “power supply stabilization time” when activated in the past may be activated as activation information. Then, the analog circuit control unit 15 may determine the activation waiting time of the internal power supply circuit 121 or the activation waiting time (clock stabilization time) of the clock circuit 122 based on the activation information.

  Further, for example, in a general information processing apparatus, in order to use an environmental state (eg temperature, external voltage level) for controlling an analog circuit at start-up, until a sensor for measuring the environmental state is stabilized. I need to wait. Therefore, there is a possibility that the time required for starting up the information processing apparatus is increased by the standby time until the sensor is stabilized. In contrast, the information processing apparatus 1 according to the present embodiment, for example, includes activation information (eg measured value of environmental temperature, environmental temperature) that reflects the environmental state when the information processing apparatus 1 has been activated in the past. Control parameter based on the measured value) can be used at the time of future startup. Therefore, the information processing apparatus 1 can start control of the analog circuit 12 using the activation information 130 prior to sensor stabilization, for example.

  Hereinafter, the configuration and operation related to the storage of the startup information 130 in the startup information memory 13 and the control of the analog circuit 12 using the startup information 130 will be described in detail. The activation information creation unit 14 illustrated in FIG. 1 stores activation information 130 in the activation information memory 13 for future activation of the information processing apparatus 1. The activation information 130 reflects at least one of the internal state and the environmental state of the information processing apparatus 1 when the information processing apparatus 1 is operating. More specifically, the activation information 130 reflects at least one of the internal state and the environmental state of the information processing apparatus 1 measured when the information processing apparatus 1 is operating. In the example of FIG. 1, the activation information creation unit 14 generates activation information 130 using the output of the sensor 16.

  The timing at which the activation information creating unit 14 generates the activation information 130 and stores it in the activation information memory 13 is not particularly limited as long as the information processing apparatus 1 is operating. For example, the activation information creation unit 14 may store the activation information 130 in the activation information memory 13 in the activation sequence of the information processing apparatus 1. The activation information creation unit 14 may store the activation information 130 in the activation information memory 13 after the sensor 16 is stabilized and before the normal operation of the main block 11 is started. In addition, the activation information creation unit 14 may store the activation information 130 in the activation information memory 13 at any timing when the main block 11 performs a normal operation after the activation sequence of the information processing apparatus 1 is completed. .

  The sensor 16 measures at least one of the internal state and the environmental state of the information processing apparatus 1. In the example of FIG. 1, the sensor 16 includes sensors 161 to 164. The external voltage sensor 161 measures the voltage level of the external voltage supplied to the information processing apparatus 1 from an external power source (not shown) and outputs a signal corresponding to the external voltage level. The temperature sensor 162 measures the environmental temperature of the information processing apparatus 1 and outputs a signal corresponding to the environmental temperature. The internal voltage sensor 163 measures the voltage level of the internal voltage generated by the internal power supply circuit 121 as an example of the analog circuit 12 and outputs a signal corresponding to the internal voltage level. The time sensor 164 measures the time required to stabilize the internal voltage (voltage stabilization time), the time required to stabilize the clock signal (clock stabilization time), or both, and a signal corresponding to the measured time. Is output. The sensor 16 may be configured to include only a part of the sensors 161 to 164 described above. The sensor 16 may include other sensors that can measure other internal states or environmental states.

  The analog circuit control unit 15 controls the analog circuit 12 according to the activation information 130 stored in the activation information memory 13 when the information processing apparatus 1 is activated. There are various variations in the control of the analog circuit 12 using the startup information 130. For example, the analog circuit control unit 15 may adjust the internal voltage generated by the internal power supply circuit 121 according to the startup information 130 reflecting the past external voltage level or environmental temperature. According to such control, the information processing apparatus 1 can raise the internal voltage in accordance with the environmental temperature when the information processing apparatus 1 has been activated in the past.

  Further, the analog circuit control unit 15 may adjust the capacitance value of the phase compensation capacitance of the internal power supply circuit 121 for phase compensation of the internal voltage according to the activation information 130 reflecting the past environmental temperature. According to such control, the information processing apparatus 1 can appropriately adjust the phase compensation capacity in accordance with the environmental temperature when the information processing apparatus 1 has been activated in the past.

  Further, the analog circuit control unit 15 may adjust the bias voltage applied to the internal power supply circuit 121 according to the activation information 130 reflecting the past environmental temperature. According to such control, the information processing apparatus 1 can appropriately adjust the bias voltage in accordance with the environmental temperature when the information processing apparatus 1 has been activated in the past.

  Further, the analog circuit control unit 15 may compensate for a variation caused by the external voltage level of the internal voltage generated by the internal power supply circuit 121 according to the activation information 130 reflecting the past external voltage level. According to such control, the information processing apparatus 1 can appropriately adjust the internal voltage in accordance with the external voltage level when the information processing apparatus 1 has been activated in the past.

  In addition, the analog circuit control unit 15 compensates for a variation caused by the temperature, the external voltage, or the internal voltage of the resonance frequency of the clock circuit 122 according to the startup information 130 reflecting the temperature, the external voltage level, or the internal voltage level. May be. According to such control, the information processing apparatus 1 appropriately adjusts the clock signal in accordance with the temperature, the external voltage level, or the internal voltage level when the information processing apparatus 1 has been activated in the past. Can do.

  Further, as already described, the analog circuit control unit 15 controls the analog circuit 12 according to the activation information 130 from the start of activation of the information processing apparatus 1 to the stabilization of the operation of the sensor 16, and after the stabilization of the sensor 16, the sensor The analog circuit 12 may be controlled according to the 16 outputs. According to such control, the information processing apparatus 1 can advance the startup procedure of each element (eg, the analog circuit 12 and the main block 11) of the information processing apparatus 1 without waiting for the operation of the sensor 16 to be stabilized. .

  The analog circuit control unit 15 shown in FIG. 1 can be configured by a logic circuit, for example, a combinational logic circuit. Specific configuration examples will be described in detail in other embodiments described later. The activation information creation unit 14 can also be configured by a logic circuit independent of the CPU 10. However, the main block 11 including the CPU 10 may generate the activation information 130 and store the activation information 130 in the activation information memory 13. In other words, the activation information creation unit 14 shown in FIG. 1 is not an essential element. For example, the process of generating and storing the activation information 130 by the activation information creating unit 14 may be performed by the main block 11.

  In the configuration example of FIG. 1, an internal voltage is supplied to the activation information creation unit 14 and the sensor 16. However, at least one of the activation information creation unit 14 and the sensor 16 may be mounted so as to operate with an external voltage.

  FIG. 2 is a flowchart illustrating an example of a startup procedure of the information processing apparatus 1. The procedure of FIG. 2 is started after the information processing apparatus 1 is turned on (e.g. after supplying an external voltage and a reset signal). In step S <b> 11, the analog circuit control unit 15 acquires the activation information 130 read from the activation information memory 13. In step S <b> 12, the analog circuit control unit 15 controls the analog circuit 12 according to the activation information 130. In step S13, the information processing apparatus 1 activates the main block 11 including the CPU 111 after the analog circuit 12 is stabilized. In step S <b> 14, the activation information creation unit 14 stores new activation information 130 reflecting the current internal state or environmental state in the activation information memory 13 for use at the next activation of the information processing apparatus 1. Note that step S14 may be performed before step S13 or may be performed in parallel with step S13.

<Embodiment 2>
In the present embodiment, an example of control of the analog circuit 12 when the information processing apparatus 1 is started will be described. Specifically, an example will be described in which the internal voltage generated by the internal power supply circuit 121 is adjusted according to the startup information 130 reflecting at least one of the past external voltage level and environmental temperature.

  FIG. 3 is a table showing an example of adjusting the internal voltage when the information processing apparatus 1 is started. FIG. 4 is a graph showing an example of a transient change of the internal voltage according to the adjustment example of FIG. 3 and 4 correspond to an operation mode in which the internal voltage is rapidly raised. That is, in the example shown in FIGS. 3 and 4, the internal power supply circuit 121 is controlled so that the internal voltage reaches the target voltage level quickly by allowing the internal voltage to be temporarily overloaded.

  In order to quickly bring the internal voltage close to the target voltage between times T1 and T2 in FIGS. 3 and 4, the analog circuit control unit 15 causes the internal power supply circuit 121 to set the internal voltage level to “target voltage + α”. Set. Next, in order to quickly lower the overshooted internal voltage level between times T2 and T3, the analog circuit control unit 15 sets the internal power supply circuit 121 so that the internal voltage level becomes “target voltage −β”. To do. In order to quickly increase the undershooted internal voltage level between times T3 and T4, the analog circuit control unit 15 sets the internal power supply circuit 121 so that the internal voltage level becomes “target voltage + γ”. . Finally, after the elapse of time T4, the analog circuit control unit 15 sets the internal power supply circuit 121 so that the internal voltage level becomes the “target voltage”. This stabilizes the internal voltage level at the target voltage.

  The magnitude relationship between the offset values α, β, and γ used for adjusting the target voltage may be α> β> γ. That is, the offset values α, β, and γ gradually decrease in the order. The analog circuit control unit 15 may determine the magnitudes of the offset values α, β, and γ according to the startup information 130 that reflects at least one of the past external voltage level and environmental temperature. The activation information 130 may be a measured value of at least one of the past external voltage level and environmental temperature, or may be a control value generated using the measured value. The offset values α, β, and γ may be calculated using the activation information 130 in the analog circuit control unit 15. The offset values α, β, and γ may be stored in advance as a lookup table. When the offset values α, β, γ are stored in advance, the activation information 130 stored in the memory 13 may be the offset values α, β, γ.

  Subsequently, a configuration example of the internal power supply circuit 121 capable of adjusting the internal voltage level will be described below. FIG. 5 is a circuit diagram showing a configuration example of the internal power supply circuit 121. The configuration example of FIG. 5 includes a non-inverting amplifier circuit using an operational amplifier OPA. The internal power supply circuit 121 of FIG. 5 amplifies and outputs the reference voltage V_REF with an amplification factor determined according to the magnitude of the feedback resistor arranged in the feedback path. The magnitude of the feedback resistor is changed by changing the voltage dividing point of the series resistor R by the transistor switches N1 to N4. That is, by controlling on / off of the transistor switches N1 to N4, the internal power supply circuit 121 in FIG. 5 can set the output voltage (internal voltage) as shown in FIGS. On / off of the transistor switches N1 to N4 is controlled by the output voltage adjustment signal S2. The analog circuit control unit 15 generates the output voltage adjustment signal S <b> 2 according to the startup information 130 reflecting at least one of the past external voltage level and environmental temperature, and supplies the output voltage adjustment signal S <b> 2 to the internal power supply circuit 121.

  Further, in the configuration example of FIG. 5, the internal power supply circuit 121 includes a temperature characteristic adjustment circuit 1210. The temperature characteristic adjusting circuit 1210 gives temperature dependency to the output voltage (internal voltage) of the operational amplifier OPA. FIG. 6 is a circuit diagram showing a configuration example of the temperature characteristic adjustment circuit 1210. The circuit 1210 shown in FIG. 6 outputs a voltage having a temperature dependency (temperature gradient) to the output (OUT) when a constant voltage having no reference temperature characteristic is applied to the input (IN). For example, the P channel transistors P11 and P12, P21 and P22, and P31 and P32 have the same characteristics, and the temperature in the relationship between the drain currents and the gate voltages (ie, Id-Vg characteristics) of the N channel transistors N11, N21, and N31. Consider a case where a gate voltage (ie, a constant voltage without temperature characteristics) that is equal to or higher than the intersection is applied to the input IN. At this time, if the gate width of the transistor N11, N21, or N31 is larger than the gate width of the transistor N12, N22, or N32 (however, the gate length is constant), the voltage appearing at the output OUT has a positive temperature characteristic. Conversely, when the gate width of the transistor N11, N21, or N31 is made smaller than the gate width of the transistor N12, N22, or N32, the voltage appearing at the output OUT has a negative temperature characteristic. Further, the internal power supply is changed by changing the size ratio of the P-channel transistor pairs P11 and P12, P21 and P22, and P31 and P32, not the size ratio of the N-channel transistor pairs N11 and N12, N21 and N22, and N31 and N32. The temperature characteristic of the output voltage of the circuit 121 may be changed.

For example, the operation of the temperature characteristic adjustment circuit 1210 may be determined according to the past environmental temperature indicated by the activation information 130 and the operation mode of the information processing apparatus 1 specified by the user.
(1) When a high-speed priority mode (an operation mode that prioritizes high-speed power supply startup) is designated, the temperature characteristic adjustment circuit 1210 is configured so that when the past environmental temperature indicated by the startup information 130 is high, the internal power supply The output voltage of the circuit 121 may be increased. Since a general device has a large operation delay at a high temperature, the operation speed can be compensated for by increasing the voltage. However, some recent microdevices for low voltage have a tendency to increase the operation delay at low temperatures. With respect to such a device, the temperature characteristic adjustment circuit 1210 may increase the output voltage of the internal power supply circuit 121 when the past environmental temperature indicated by the activation information 130 is low.
(2) When a low power priority mode (an operation mode in which low power is prioritized over high-speed start-up) is designated, the temperature characteristic adjustment circuit 1210, when the past environmental temperature indicated by the startup information 130 is low, The output voltage of the internal power supply circuit 121 may be lowered. However, as described above, in recent devices, the temperature characteristic adjustment circuit 1210 may reduce the output voltage of the internal power supply circuit 121 when the past environmental temperature indicated by the activation information 130 is high or normal temperature. Good. Further, the temperature characteristic adjustment circuit 1210 may lower the output voltage of the internal power supply circuit 121 as a whole (direct current (DC)) as compared with the case where the high-speed priority mode is designated.

  FIG. 7 is a timing chart illustrating an example of a startup procedure of the information processing apparatus 1 according to the present embodiment. The activation of the information processing apparatus 1 is started when (a) an external voltage and (b) a reset signal are supplied to the information processing apparatus 1 at time T0. The start-up information memory 13 is started to operate when supplied with (a) an external voltage and (b) a reset signal, and can output start-up information 130. In the example of FIG. 7, (e) activation information A and (g) activation information B correspond to the activation information 130. (E) The startup information A is information used for adjusting the temperature characteristics of the internal power supply circuit 121 described above. (G) The startup information B is information used for adjusting the output voltage of the internal power supply circuit 121 described above.

  (A) The activation information enable signal F_ENB rises at time T1 after a predetermined delay time has elapsed since the external voltage and (b) reset signal were supplied to the information processing apparatus 1. (C) The signal F_ENB is a signal for validating the control of the analog circuit 12 using the activation information 130. (C) The delay time until the signal F_ENB rises may be set longer than the rise time required until the activation information memory 13 can output the activation information 130. For example, (c) the signal F_ENB may be supplied to the analog circuit control unit 15 from a delay circuit (not shown) that delays and outputs a logical product signal of (a) an external voltage and (b) a reset signal.

  The analog circuit control unit 15 acquires the activation information 130 (activation information A and B) at time T1. The analog circuit control unit 15 controls the internal power supply circuit 121 according to the activation information 130 (activation information A and B). In the example of FIG. 7, the analog circuit control unit 15 generates (f) a temperature characteristic adjustment signal S1 according to (e) start-up information A, and supplies this to the temperature characteristic adjustment circuit 1210. (F) The temperature characteristic adjustment signal S1 indicates whether or not temperature characteristic adjustment is performed (selection or non-selection).

  In the example of FIG. 7, the analog circuit control unit 15 generates (h) the output voltage adjustment signal S2 according to (e) start-up information B, and supplies this to the transistor switches N1 to N4. (H) The output voltage adjustment signal S2 sequentially changes the amplification factor of the non-inverting amplifier circuit (the operational amplifier OPA) by turning on the transistor switches N1 to N4 one by one in the order of N4, N1, N3, and N2. Thereby, sequence control of the output voltage (internal voltage) corresponding to FIGS. 3 and 4 is executed.

  Further, in the example of FIG. 7, the activation information memory 13 outputs (d) operation mode information. (D) The operation mode information indicates the operation mode of the information processing apparatus 1. The operation mode defines at least the operation when the information processing apparatus 1 is activated. The operation mode information held in the activation information memory 13 may be specified by the user of the information processing apparatus 1. The operation mode includes, for example, at least one of a fast start mode, a low current start mode, and a low voltage start mode.

  The analog circuit control unit 15 may change the control content of the analog circuit 12 according to the operation mode information. For example, the analog circuit control unit 15 performs the control as shown in FIGS. 3 and 4, that is, the sequence control of the internal voltage for raising the internal voltage at a high speed when the fast start-up mode is designated. Also good. On the other hand, when the low current activation mode is designated, the analog circuit control unit 15 may gently activate the internal voltage without performing the sequence control of the internal voltage. Thereby, in the low current startup mode, it is possible to avoid wasteful power consumption associated with high-speed startup.

  Furthermore, in the example of FIG. 7, at time T5, (i) a completion status signal is output. The completion status signal may be output by the analog circuit control unit 15. The analog circuit control unit 15 may output a completion status signal by setting a flag register associated with the completion status. The time T5 that is the output timing of the completion status signal may be a time when a predetermined delay time has elapsed from the completion time T4 of the control of the analog circuit 12 at the time of activation. The time T5 may be determined based on the detection of the completion of control of the analog circuit 12 by the sensor 16, for example, the detection of the internal voltage by the internal voltage sensor 163. When the completion status signal becomes valid (enabled), the reset signal becomes invalid (disabled), and in response to this, the main block 11 including the CPU 111 is started.

  As described above, (i) the completion status signal is output in response to the completion of the control of the analog circuit 12 at the time of activation. Therefore, by using the completion status signal, activation of the main block 11 including the CPU 111 can be started promptly without waiting for an excessive waiting time determined according to the most severe operating conditions.

<Embodiment 3>
In the present embodiment, an example will be described in which the control of the analog circuit 12 is switched from the control using the activation information 130 to the control using the output of the sensor 16. As described in the first embodiment, according to such control, the information processing apparatus 1 does not wait for the operation of the sensor 16 to be stabilized, and each element of the information processing apparatus 1 (eg analog circuit 12, main block) 11) The startup procedure can be advanced.

  FIG. 8 is a flowchart illustrating an example of a startup procedure of the information processing apparatus 1 according to the present embodiment. The processing / operation in steps S11, S12, S13, and S14 in FIG. 8 may be the same as the processing / operation in the step group having the same reference numeral shown in FIG. In the procedure of FIG. 8, the analog circuit control unit 15 determines whether or not the operation of the sensor 16 has stabilized after starting the control of the analog circuit 12 according to the activation information 130 (step S211). When the sensor 16 is stabilized, the analog circuit control unit 15 continues to control the analog circuit 12 using the output of the sensor 16 instead of the activation information 130.

<Embodiment 4>
In the present embodiment, another example of the control of the analog circuit 12 when the information processing apparatus 1 is activated will be described. Specifically, an example will be described in which the phase compensation capacitance of the internal power supply circuit 121 is adjusted according to the activation information 130 reflecting the past environmental temperature. Further, in the present embodiment, a configuration example of the analog circuit control unit 15 corresponding to the third embodiment (an example in which the control using the activation information 130 is switched to the control using the output of the sensor 16) will be described.

  FIG. 9 is a circuit diagram showing a configuration example of the analog circuit 12 (specifically, the internal power supply circuit 121). In the configuration example of FIG. 9, the operational amplifier OPA includes a differential amplification stage and an output stage. The differential amplification stage includes N channel transistors N41 to N43 and P channel transistors P41 and P42. The output stage includes an N channel transistor N44 and a P channel transistor P43.

  Further, in order to prevent oscillation of the operational amplifier OPA having positive feedback, phase compensation capacitors C0 to C2 are connected in parallel between the output of the operational amplifier OPA and the ground potential. By changing the load capacitance value that the output of the operational amplifier OPA has, the phase of the output voltage that is positively fed back to the gate of the transistor N42 can be adjusted. In the configuration example of FIG. 9, transistor switches N45 and N46 are arranged between the phase compensation capacitors C1 and C2 and the ground potential so that the load capacitance value of the output of the operational amplifier OPA can be changed.

  The analog circuit control unit 15 supplies the control signals CC1 and CC2 to the internal power supply circuit 121, thereby controlling on / off of the transistor switches N45 and N46. That is, the analog circuit control unit 15 can adjust the phase compensation capacitance value by the control signals CC1 and CC2. The analog circuit control unit 15 generates control signals CC1 and CC2 according to the output of the temperature sensor 162 or the activation information 130. The activation information 130 here is created reflecting the environmental temperature measured in the past. Thereby, the analog circuit control part 15 can compensate the output phase fluctuation | variation of operational amplifier OPA resulting from the change of environmental temperature.

  Further, as already described, the analog circuit control unit 15 adjusts the phase compensation capacity of the internal power supply circuit 121 according to the startup information 130 until the operation of the temperature sensor 162 is stabilized, and after the temperature sensor 162 is stabilized, The phase compensation capacity of the internal power supply circuit 121 may be adjusted according to the output of the temperature sensor 162. According to such control, the information processing apparatus 1 can proceed with the startup procedure of each element (eg, the analog circuit 12 and the main block 11) of the information processing apparatus 1 without waiting for the operation of the temperature sensor 162 to stabilize. it can.

  Note that the arrangement of the phase compensation capacitors shown in FIG. 9 is merely an example. For example, a phase compensation capacitor may be provided in a feedback path (for example, between node A and node B in FIG. 9) from the output of the output stage of the operational amplifier OPA to the input.

  FIG. 10 is a table showing an example of the relationship between the environmental temperature, the control signals CC1 and CC2, and the phase compensation capacitance value. In the example of FIG. 10, the capacitance values of the capacitors C0, C1, and C2 are 100 pF, 50 pF, and 25 pF, respectively. According to the example of FIG. 10, when the temperature is lower than 0 ° C., the control signals CC1 and CC2 are both “1”, and the transistors N45 and N46 are both turned on. As a result, all of the capacitors C0 to C2 are connected to the output of the operational amplifier OPA, and the phase compensation capacitance becomes the maximum value (i.e. 175 pF). When the temperature is 100 ° C. or higher, the control signals CC1 and CC2 are both “0”, and the transistors N45 and N46 are both turned off. As a result, only the capacitance C0 is connected to the output of the operational amplifier OPA, and the phase compensation capacitance becomes the minimum value (i.e. 100 pF).

  Next, a configuration example of the analog circuit control unit 15 for performing the control shown in the table of FIG. 10 will be described. FIG. 11 is a circuit diagram illustrating a configuration example of the analog circuit control unit 15. The analog circuit control unit 15 shown in FIG. 11 is configured by a combinational logic circuit. Specifically, the analog circuit control unit 15 in FIG. 11 includes AND circuits 901 to 905, an OR circuit 911, NAND circuits 921 to 923, NOR circuits 931 to 932, an XOR circuit 941, and selectors (multiplexers) 951 to 952. Including.

  In the example of FIG. 11, the temperature sensor 162 includes three temperature sensors 1621 to 1623. The output signal TS1 of the temperature sensor 1621 is “1” when the temperature is 100 ° C. or higher, and is “0” when the temperature is lower than 100 ° C. The output signal TS2 of the temperature sensor 1622 is “1” when the temperature is 50 ° C. or higher, and is “0” when the temperature is lower than 50 ° C. The output signal TS3 of the temperature sensor 1623 is “1” when the temperature is 0 ° C. or higher, and is “0” when the temperature is lower than 0 ° C. The 3-bit output signals TS1 to TS3 of the temperature sensors 1621 to 1623 are converted into 2-bit values TC1 and TC2 in the control circuit 15. FIG. 12A is a truth table showing the correspondence between (TS1, TS2, TS3) and (TC1, TC2).

  In the example of FIG. 11, the activation information 130 read from the activation information memory 13 includes 2-bit values FC1 and FC2. (FC1, FC2) is converted into (PC1, PC2) based on the value of the BOOST signal. The BOOST signal indicates whether or not it is an operation mode in which the internal voltage is rapidly raised. When the BOOST signal is “0”, this corresponds to an operation mode in which the internal voltage is not rapidly raised, and (PC1, PC2) has the same value as (FC1, FC2). On the other hand, when the BOOST signal is “1”, this corresponds to an operation mode in which the internal voltage is rapidly raised. Therefore, (PC1, PC2) is a value obtained by converting (FC1, FC2) so that a relatively small phase compensation capacity is selected. FIG. 12B is a truth table showing the correspondence between (BOOST, FC1, FC2) and (PC1, PC2).

  The selectors 951 to 952 operate based on the activation information selection signal F_SEL. Specifically, the selectors 951 to 952 select the values PC1 and PC2 based on the activation information 130 when the signal F_SEL is “1”, and the values TC1 and TC1 based on the temperature sensor 162 when the signal F_SEL is “0”. Select TC2. The signal F_SEL is “1” until the temperature sensor 162 is stabilized, and is “0” after the temperature sensor 162 is stabilized. The timing at which the activation information selection signal F_SEL falls from 1 to 0 may be set in advance based on the stabilization time of the temperature sensor 162, or is dynamically determined based on the monitoring result of the output of the temperature sensor 162. Also good.

  The activation information enable signal F_ENB is a signal for enabling the control of the analog circuit 12 using the activation information 130 as described above. The AND circuits 904 and 905 calculate the logical product of the output signals of the selectors 951 to 952 and the activation information enable signal F_ENB and output them as control signals CC1 and CC2. FIG. 12C is a truth table showing the correspondence between (F_ENB, F_SEL) and (CC1, CC2). While the activation information enable signal F_ENB is “0”, the control signals (CC1, CC2) are set to the initial values (0, 0) regardless of the value of the activation information selection signal F_SEL.

  FIG. 13 is a timing chart illustrating an example of a startup procedure of the information processing apparatus 1 according to the present embodiment. As described with reference to FIG. 7, the activation of the information processing apparatus 1 is started when (a) the external voltage and (b) the reset signal are supplied to the information processing apparatus 1 at time T0. Then, at time T1 after a predetermined delay time has elapsed since (a) the external voltage and (b) the reset signal were supplied to the information processing apparatus 1, (c) the activation information enable signal F_ENB rises.

  In the example of FIG. 13, (d) the BOOST signal is set to “1” from time (c) when the activation information enable signal F_ENB rises to time T2 after a predetermined delay time. In the example of FIG. 13, (e) the activation information selection signal F_SEL is set to “1” from the time T2 when the BOOST signal is set to “0” to the time T3 after a predetermined delay time. . The time T3 may be determined in advance based on (g) the time until the output of the temperature sensor 162 is stabilized. Further, (g) monitoring the output of the temperature sensor 162 may dynamically determine that the output has been stabilized.

  The analog circuit control unit 15 acquires (f) activation information 130 at time T1. As described above, (f) activation information 130 includes 2-bit values FC1 and FC2. (E) During the period from time T1 when the activation information selection signal F_SEL is “1” to time T3, the analog circuit control unit 15 uses the values (PC1, PC2) determined based on the activation information (FC1, FC2). Output as control signals (CC1, CC2). However, the values (PC1, PC2) based on the activation information (FC1, FC2) change before and after time T2 when the BOOST signal changes from “1” to “0”. As described with reference to FIGS. 11 and 12, (PC1, PC2) is selected so that a relatively small phase compensation capacitance is selected between time T1 and T2 when the BOOST signal is “1”. It is determined. On the other hand, (PC1, PC2) has the same value as (FC1, FC2) from time T2 to T3 when the BOOST signal is “0”.

  Next, the analog circuit control unit 15 acquires the output signals (TS1, TS2, TS3) of the temperature sensor 162 at time T3. Then, after time T3, control signals CC1 and CC2 are generated according to the output signals (TS1, TS2, TS3) of the temperature sensor 162. That is, the analog circuit control unit 15 outputs the values (TC1, TC2) determined based on the output signals (TS1, TS2, TS3) of the temperature sensor 162 as control signals (CC1, CC2).

  The (i) phase compensation capacitance value in FIG. 13 indicates the phase compensation capacitance value selected according to the specific example in FIG. The example of (j) internal power supply circuit output shows an example of the time change of the main voltage of the internal power supply circuit 121.

  The (k) completion status signal in FIG. 13 is the same as the (i) completion status signal shown in FIG.

<Embodiment 5>
In the present embodiment, a modification of the above-described fourth embodiment will be described. In the fourth embodiment described above, the example in which the phase compensation capacitance of the internal power supply circuit 121 is adjusted according to the activation information 130 reflecting the past environmental temperature has been described. However, the control of the internal power supply circuit 121 is not limited to the adjustment of the phase compensation capacitance. As already described in the first embodiment, the analog circuit control unit 15 may adjust the bias voltage (eg, BIAS voltage shown in FIG. 9) for the internal power supply circuit 121. According to such control, the information processing apparatus 1 can appropriately adjust the bias voltage in accordance with the environmental temperature when the information processing apparatus 1 has been activated in the past.

  FIG. 14 is a timing chart showing an example of a startup procedure of the information processing apparatus 1 according to the present embodiment. The waveforms (a) to (g) shown in FIG. 14 are the same as the waveforms (a) to (g) shown in FIG. (H) The bias setting signal VB is a control signal supplied from the analog circuit control unit 15 to the internal power supply circuit 121. (D) When the BOOST signal is “1”, the analog circuit control unit 15 causes the bias voltage value to be higher than the value determined by (f) the activation information 130 from time T1 to time T2. A bias setting signal VB is generated (VB_A). (D) When the BOOST signal is “0”, the analog circuit control unit 15 sets the bias setting signal VB so that the bias voltage value becomes a value determined by (f) start-up information 130 from time T2 to time T3. Is generated (VB_B). (E) When the activation information selection signal F_SEL is “0”, after T3, the analog circuit controller 15 determines that the bias voltage value becomes a value determined by (g) the output of the temperature sensor 162. VB is generated (VB_C).

  The example of (i) bias voltage in FIG. 14 shows a case where the BOOST signal is set to “1” and the internal voltage is rapidly raised. In this case, a relatively high bias voltage (e.g. 1.0 V) is supplied to the internal power supply circuit 121 from time T1 to time T2.

  The example of (j) bias voltage in FIG. 14 shows a case where the BOOST signal is set to “0” and the internal voltage is not rapidly raised. In this case, a startup mode with low power may be used. That is, a relatively small bias voltage (e.g. 0.6 V) may be supplied to the internal power supply circuit 121 as shown by the waveform (j) in FIG.

<Embodiment 6>
In the present embodiment, a configuration example of the activation information memory 13 will be described. FIG. 15 is a block diagram illustrating a configuration example of the activation information memory 13. The activation information memory 13 in FIG. 15 is a flash memory. First, a normal read operation and write operation of the activation information memory 13 which is a flash memory will be described.

  The memory matrix 131 includes a plurality of memory cells arranged in a matrix. FIG. 15 shows two memory cells MC1 and MC2 in the same row among a plurality of memory cells. In the configuration example of FIG. 15, each of the memory cells MC1 and MC2 has two gate electrodes, that is, a control gate and a memory gate. The control gate is connected to the word line WL. The memory gate is connected to the memory gate selection line MGL.

  At the time of normal data reading, the read row selector 132 designates the target row of the memory matrix 131 based on the read address input to the address bus. Specifically, the selector 132 applies a voltage to the word line WL of the read target row. Column selection at the time of reading is performed by the column selector 133. The data read from the memory matrix 131 is supplied to the output data bus via the verify sense amplifier 134 and the input / output circuit 135.

  During normal data writing, the write row selector 137 designates the target row of the memory matrix 131 based on the read address input to the address bus. Specifically, the selector 137 applies a voltage to the word line WL in the write target row. Column selection at the time of writing is performed by the column selector 133. The write data supplied from the input data bus is supplied to the target memory cell via the write latch 136.

  The power supply circuit 138 receives an external voltage and generates an operating voltage supplied to each unit of the activation information memory 13.

  Furthermore, the activation information memory 13 of FIG. 15 is configured to output the activation information 130 by an external voltage without using an internal voltage. More specifically, the activation information memory 13 of FIG. 15 is activated in response to the supply of an external voltage and a reset signal without performing normal row selection and column selection based on a read address input via an address bus. The information 130 can be output.

  Specifically, the word lines WL of the memory cells MC1 and MC2 that store the activation information 130 are connected to the reset signal line via the OR circuit 1321. Accordingly, the activation information 130 stored in the memory cells MC1 and MC2 is held in the write latch 136 in response to the supply of the external voltage and the reset signal. The write latch 136 also serves as a reset transfer register. That is, the write latch (reset transfer register) 136 supplies the activation information 130 read from the memory cells MC1 and MC2 to the analog circuit control unit 15.

  By using the structure shown in FIG. 15, activation information 130 used to activate the analog circuit 12 including the internal power supply circuit 121 can be stored in the information processing apparatus 1. In addition, according to the structure shown in FIG. 15, the activation information 130 can be easily read out only by supplying an external voltage and a reset signal.

<Embodiment 7>
In the present embodiment, an example in which the information processing apparatus 1 is applied to a single-chip microcomputer will be described. FIG. 16 is a block diagram illustrating a configuration example of the information processing apparatus 1 as a single-chip microcomputer. The CPU 111, DMA controller 112, RAM 113, bus interface 114, and flash memory module 115 shown in FIG. 16 are specific examples of the main block 11. Further, the internal power supply circuit 121 and the clock circuit 122 shown in FIG. 16 are specific examples of the analog circuit 12. The completion status flag 151 is a register that holds a completion status output from the analog circuit control unit 15 in response to the completion of activation of the analog circuit 12. The mode register 152 holds the operation mode information read from the activation information memory 13. These components are connected by a peripheral bus 101 and a high-speed bus 102.

  The information processing apparatus 1 described in the first to sixth embodiments is suitable for a single chip microcomputer as shown in FIG. 16, for example. Single-chip microcomputers are used in various applications and environments as so-called embedded systems. Therefore, according to the first to sixth embodiments, for example, an unnecessary margin can be eliminated and the start-up control of the analog circuit 12 adapted to the actual operating conditions of the single-chip microcomputer can be performed. According to the first to sixth embodiments, for example, the control of the analog circuit 12 can be started using the activation information 130 prior to the stabilization of the sensor 16.

  In addition, Embodiment 1-7 mentioned above can be used in combination as appropriate. As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 11 Main block 12 Analog circuit 13 Startup information memory 14 Startup information creation part 15 Analog circuit control part 16 Sensor 101 Peripheral bus 102 High-speed bus 111 CPU (Central Processing Unit)
112 DMA (Direct Memory Access) Controller 113 RAM (Random Access Memory)
114 Bus interface 115 Flash memory module 121 Internal power supply circuit 122 Clock circuit 130 Startup information 131 Memory matrix 132 Read row selector 133 Column selector 134 Verify sense amplifier 135 Input / output circuit 136 Write latch / reset transfer register 137 Write row selector 151 Completion status Flag 152 Mode register 161 External voltage sensor 162 Temperature sensor 163 Internal voltage sensor 164 Time sensor 901-905 AND circuit 911 OR circuit 921-923 NAND circuit 931, 932 NOR circuit 941 XOR circuit 951, 952 Selector (multiplexer)
1210 Temperature characteristic adjustment unit 1321 OR circuit 1621 to 1623 Temperature sensor ADJ # 1 to ADJ # 3 Temperature characteristic adjustment circuit OPA Operational amplifiers CC1 and CC2 Analog circuit control signals TS1, TS2, TS3 Temperature sensor signals FC1, FC2 Activation information signals MC1, MC2 Memory cell WL Word line MGL Memory gate selection line

Claims (20)

An information processing apparatus,
Main block including CPU (Central Processing Unit),
An analog circuit electrically coupled to the main block;
Non-volatile memory;
Startup information reflecting at least one of an internal state and an environmental state of the information processing device measured when the information processing device is operating is used for the non-volatile operation for future startup of the information processing device. A startup information creation unit stored in memory;
An analog circuit controller that controls the analog circuit according to the activation information stored in the nonvolatile memory at the time of the future activation;
An information processing apparatus comprising: A sensor for measuring the internal state or the environmental state;
The control by the analog circuit control unit includes controlling the analog circuit according to the activation information before stabilizing the operation of the sensor, and controlling the analog circuit according to the output of the sensor after stabilizing the sensor. ,
The information processing apparatus according to claim 1. The startup information reflects at least one of the external voltage level and temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The control by the analog circuit control unit includes adjusting the internal voltage according to the startup information.
The information processing apparatus according to claim 1 or 2. The startup information reflects the temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The control by the analog circuit control unit includes adjusting a capacitance value of a compensation capacitor included in the power supply circuit for phase compensation of the internal voltage according to the activation information.
The information processing apparatus according to claim 1 or 2. The startup information reflects the temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The control by the analog circuit control unit includes adjusting a bias voltage applied to the power supply circuit according to the activation information.
The information processing apparatus according to claim 1 or 2. The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The nonvolatile memory is configured to be able to output the activation information by the external voltage without using the internal voltage.
The information processing apparatus according to claim 1 or 2.   The information processing apparatus according to claim 1, wherein the analog control circuit outputs a completion status indicating completion of activation of the analog circuit.   The information processing apparatus according to claim 1, further comprising a sensor that measures the internal state or the environmental state.   The information processing apparatus according to claim 1, wherein the information processing apparatus is a single-chip microcomputer. An information processing apparatus activation control method comprising:
The information processing apparatus includes a main block including a CPU (Central Processing Unit), an analog circuit electrically coupled to the main block, and a nonvolatile memory,
The method
Startup information reflecting at least one of an internal state and an environmental state of the information processing device measured when the information processing device is operating is used for the non-volatile operation for future startup of the information processing device. Storing in memory, and controlling the analog circuit according to the activation information stored in the non-volatile memory during the future activation;
An activation control method comprising: Further comprising measuring the internal state or the environmental state using a sensor included in the information processing apparatus,
The controlling includes controlling the analog circuit according to the activation information before stabilizing the operation of the sensor, and controlling the analog circuit according to the output of the sensor after stabilizing the sensor.
The method of claim 10. The startup information reflects at least one of the external voltage level and temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The controlling includes adjusting the internal voltage according to the activation information;
12. A method according to claim 10 or 11. The startup information reflects the temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The controlling includes adjusting a capacitance value of a compensation capacitor included in the power supply circuit for phase compensation of the internal voltage according to the activation information.
12. A method according to claim 10 or 11. The startup information reflects the temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The controlling includes adjusting a bias voltage applied to the power supply circuit according to the activation information.
12. A method according to claim 10 or 11.   12. The method according to claim 10 or 11, further comprising outputting a completion status indicating completion of startup of the analog circuit. An information processing apparatus,
Main block including CPU (Central Processing Unit),
An analog circuit electrically coupled to the main block;
Non-volatile memory;
An analog circuit control unit for controlling the analog circuit according to the startup information stored in the nonvolatile memory;
With
The main block includes activation information that reflects at least one of an internal state and an environmental state of the information processing device measured when the information processing device is operating, for future activation of the information processing device. Is configured to store in the non-volatile memory,
Information processing device. A sensor for measuring the internal state or the environmental state;
The control by the analog circuit control unit includes controlling the analog circuit according to the activation information before stabilizing the operation of the sensor, and controlling the analog circuit according to the output of the sensor after stabilizing the sensor. ,
The information processing apparatus according to claim 16. The startup information reflects at least one of the external voltage level and temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The control by the analog circuit control unit includes adjusting the internal voltage according to the startup information.
The information processing apparatus according to claim 16 or 17. The startup information reflects the temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The control by the analog circuit control unit includes adjusting a capacitance value of a compensation capacitor included in the power supply circuit for phase compensation of the internal voltage according to the activation information.
The information processing apparatus according to claim 16 or 17. The startup information reflects the temperature as the environmental state,
The analog circuit includes a power supply circuit that generates an internal voltage supplied to the main block from an external voltage,
The control by the analog circuit control unit includes adjusting a bias voltage applied to the power supply circuit according to the activation information.
The information processing apparatus according to claim 16 or 17.

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