JP2013152187A - Device tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of useless waiting time when switching test contents.SOLUTION: A first arithmetic unit 102 attains exclusive OR between pieces of information that are set for the same relay in first relay setting information for which the information on a relay to be used for route changeover of test signals in a first test is set and second relay setting information for which the information on the relay to be used for route changeover of test signals in a second test is set, and outputs the result (arithmetic output).

Description

  The present invention relates to a device tester that performs an electrical test of a device such as an LSI.

  In manufacturing a device such as an LSI, as is well known, an electrical test using a device tester is performed as an inspection of a manufactured device (see Patent Document 1). In this device tester, when a plurality of different tests can be performed and the test content to be measured is changed, the path of the test signal to the device is switched according to the test content along with the change of the measurement condition. This switching is performed using a relay, and the switching of the relay generally requires several milliseconds.

  The switching time is determined by the item (type) of the test content to be performed. This is because the time required for switching the relay differs depending on the type of relay used for switching the signal path in the test. Of the plurality of relays operating in each test, the relay having the longest switching time is set as a reference, and the time required for switching by this relay is set as the switching time described above.

  This switching time is set for each test item to be performed. For example, when the next test is a low pressure item, the switching time is 3 ms. When the next test is a high pressure item, the switching time is 5 ms. When the next test is a high current item, the switching time is set to 50 ms.

  This switching time is set by the circuit shown in FIG. The circuit shown in FIG. 10 includes a ROM 1001 that outputs data at an address corresponding to an input code. A code corresponding to the test item as described above is input to the ROM 1001.

  For example, when a code corresponding to a low voltage item is input, on / off information of each relay used in the test of the low voltage item is output from Q1. When a code corresponding to the high voltage item is input, on / off information of each relay used in the test of the high voltage item is output from Q1, and in addition, a signal for selecting a switching time of 5 ms is output from Q2. When a code corresponding to a large current item is input, on / off information of each relay used in the large current item test is output from Q1, and in addition, a signal for selecting a switching time of 50 ms is output from Q3. The

  This circuit also includes an AND gate 1002 for inputting the output of Q2 from the ROM 1001 and the relay operation start trigger, and an AND gate 1003 for inputting the output of Q3 from the ROM 1001 and the relay operation start trigger. Also, a monostable multivibrator (MM) 1004 that continues the output for 5 ms when the output from the AND gate 1002 is input, and a monostable multivibrator (MM) 1005 that continues the output for 50 ms when the output from the AND gate 1003 is input, A monostable multivibrator (MM) 1006 that continues output for 3 ms when a relay operation start trigger is input, and an OR gate 1007 that inputs the outputs of MM1004, MM1005, and MM1006 are provided.

  According to this circuit, when a code corresponding to a test item is input to the ROM 1001 and a relay operation start trigger is input, the output from the OR gate 1007 is continued corresponding to the output from Q2 and Q3 of the ROM 1001. The For example, when a code corresponding to the low voltage item is input to the ROM 1001, there is no output from Q2 and Q3, so there is no output from MM1004 and MM1005, and the output from MM1006 is continued for 3 ms. As a result, the output from the OR gate 1007 is continued for 3 ms.

  Further, when a code corresponding to a high voltage item is input to the ROM 1001, the output from Q2 is output and there is no output from Q3, so there is no output from MM1005, the output from MM1004 is continued for 5 ms, and from MM1006 Is continued for 3 ms. As a result, the output from the OR gate 1007 is continued for 5 ms.

  Further, when a code corresponding to a large current item is input to the ROM 1001, there is no output from Q3 because there is no output from Q3, so there is no output from MM1004, the output from MM1005 is continued for 50 ms, and MM1006 The output from is continued for 3 ms. As a result, the output from the OR gate 1007 is continued for 50 ms.

Japanese Patent Application Laid-Open No. 5-164813

  However, in the setting of the waiting time at the time of switching the measurement described above, a waiting time is always generated even when the next measurement is on the same route as the previous measurement. If the next measurement is the same route as the previous measurement, there is no need to wait for the relay to be switched because the relay is not switched at all. The waiting time set as described above is a wasteful time and becomes a problem. .

  The present invention has been made to solve the above-described problems, and an object of the present invention is to suppress generation of useless waiting time when switching test contents.

  The device tester according to the present invention includes a test unit configured to output a test signal to a device to be tested to test the device, and a relay information used for switching a test signal path in the first test. Among the relay setting information and the second relay setting information in which the information of the relay used for switching the route of the test signal in the second test performed after the first test is set, the same relay A first computing means for performing an exclusive OR between set information, and a second information for selecting the relay information having the maximum switching time among the relays having a computing output of 1 by the first computing means. The switching time indicated by the information of the relay selected by the calculation means and the second calculation means is set as a waiting time from the end of the first test to the start of the second test. Comprising at least a control means for performing, second calculating means, if there is no output from the first calculating means outputs the information of the relay there is a switching time 0.

  Also, the device tester according to the present invention is configured with test means for outputting a test signal to a device to be tested to test the device and information on a relay used for switching the test signal path in the first test. Among the first relay setting information and the second relay setting information in which the relay information used for switching the test signal path in the second test performed after the first test is set to the same relay. The first arithmetic means for performing an AND operation between the inverted output of one information and the other information between the information set for the information, and transition from OFF to ON set for the same relay The relay switching waiting time identification code and the relay switching waiting time identification code when transitioning from ON to OFF is applied to each relay based on the output of the first computing means. A second computing means for selecting the relay information that maximizes the switching time indicated by the selected identification code, and the switching time indicated by the relay information selected by the second computing means, Control means for controlling the test means as a waiting time from the end of the test until the start of the second test, and the second calculation means switches the switching time when there is no output from the first calculation means Outputs relay information for which is set to 0.

  In the device tester, the first calculation means and the second calculation means may encode the switching time into a larger code as the time is longer and use it for the calculation.

  As described above, according to the present invention, it is possible to obtain an excellent effect that generation of useless waiting time can be suppressed when switching test contents.

FIG. 1 is a configuration diagram showing a configuration of a device tester according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating an example of a circuit constituting the first arithmetic unit 102. FIG. 3 is a circuit diagram illustrating an example of a circuit constituting the second arithmetic unit 103. FIG. 4 is an explanatory diagram showing a relationship (a) between each output (input) and a relay number, and each output example (b). FIG. 5 is a flowchart for explaining relay switching of the device tester according to the embodiment of this invention. FIG. 6 is a flowchart for explaining relay switching of a conventional device tester. FIG. 7 is a circuit diagram illustrating another example of the circuit constituting the first arithmetic unit of the device tester according to the embodiment of the present invention. FIG. 8 is a configuration diagram illustrating another configuration example of the second arithmetic unit of a part of the device tester according to the embodiment of the present invention. FIG. 9 is a circuit diagram illustrating an example of another circuit constituting the second arithmetic unit of the device tester according to the embodiment of the present invention. FIG. 10 is an explanatory diagram for explaining a circuit configuration for setting a waiting time conventionally used.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration of a device tester according to an embodiment of the present invention. The device tester includes a test unit 101, a first calculation unit 102, a second calculation unit 103, and a control unit 104.

  The test unit 101 is provided in a well-known device tester, and outputs a test signal to a test target device to test the device.

  The first calculation unit 102 includes first relay setting information in which relay information used for test signal path switching in the first test is set, and relay information used for test signal path switching in the second test. In the second relay setting information in which is set, the information set for the same relay is exclusive-ORed and this result (calculation output) is output. The second test is a test performed following the first test.

  The second computing unit 103 selects information on the relay that has the longest switching time among the relays whose computation output is 1 in the first computing unit 102. In addition, when there is no output from the first calculation unit 102, the second calculation unit 103 outputs information on a virtual relay whose switching time is zero. In addition, in the control unit 104, the switching unit indicated by the information on the relay selected by the second calculation unit 103 is used as a waiting time from the end of the first test to the start of the second test. Control. When the above-described virtual relay information is output from the second arithmetic unit 103, the control unit 104 starts the second test after the first test ends at the switching time 0 indicated by the virtual relay information. The test unit 101 is controlled as a waiting time until the start.

  For example, the first relay setting information is stored in the first relay setting information storage unit 111, and the second relay setting information is stored in the second relay setting information storage unit 112. For example, as illustrated in FIG. 2, the first arithmetic unit 102 includes an XOR gate that performs an exclusive OR according to the number of relays provided in the device tester. Each XOR gate takes an exclusive OR of the setting information in the first relay information and the setting information in the second relay information regarding the same relay.

  For example, the relay 1 is “ON” in the first relay information and “ON” in the second relay information. The relay 2 is “OFF” in the first relay information and “ON” in the second relay information. Further, the relay 3 is “ON” in the first relay information, and “ON” in the second relay information. Further, the relay 4 is “ON” in the first relay information, and “ON” in the second relay information. The relay 5 is “OFF” in the first relay information and “OFF” in the second relay information. The relay 6 is “OFF” in the first relay information and “ON” in the second relay information. In this case, in the first arithmetic unit 102, an output is generated from the corresponding XOR gate for the relay 2 and the relay 6 ("1" is output).

  In addition, the second calculation unit 103 selects information on the relay that has the maximum switching time among the relays whose calculation output is 1 in the first calculation unit 102. For example, in the configuration illustrated in FIG. 2, each relay is configured by any one of a power relay with a switching time of 3 ms, a reed relay with a switching time of 1 ms, and a semiconductor relay with a switching time of 0.5 ms. Among these, the relays 1, 5 and 6 are constituted by power relays, the relay 2 is constituted by a reed relay, and the relays 3 and 4 are constituted by semiconductor relays.

  In the exclusive OR described above, an output is generated for the relay 2 and the relay 6. Among these, according to the relay configuration described above, the switching time of the relay 2 is 1 ms, and the switching time of the relay 6 is 3 ms. Therefore, the second calculation unit 103 selects relay information of the relay 6. As a result, the control unit 104 controls the test unit 101 with the switching time 3 ms indicated by the information of the relay 6 as a waiting time from the end of the first test to the start of the second test.

  According to the above-described embodiment, the first relay setting information in the first test and the second relay setting information in the second test are the same, such as when continuously executed on the same measurement path. Therefore, nothing is output from the first calculation unit 102. In this case, since the second calculation unit 103 outputs information on the virtual relay whose switching time is set to 0, the control unit 104 waits until the second test is started after the first test is completed. Therefore, the test unit 101 is controlled with the waiting time of 0 being zero. As described above, according to this embodiment, when the test target is the same test item and the switching operation of the relay due to the change of the test target does not occur, the next test is immediately performed without taking a waiting time. Therefore, it is possible to suppress generation of useless waiting time when switching the test contents.

  By the way, the second arithmetic unit 103 having the circuit configuration shown in FIG. 3 can reduce the scale of the circuit even when a large number of relays are provided. The circuit configuration shown in FIG. 3 shows a case where a code for identifying the type of relay is configured with 4 bits. The relay identification code is characterized in that the longer the relay switching waiting time is, the larger the code value is associated with, and the relay switching waiting time information is compressed and used for computation. In this circuit configuration, 4 × 4 AND gates, 5 decoders 301a, 301b, 301c, 301d, and 301e, 16 OR gates with 5 inputs, an encoder 302, a latch unit 303, and data conversion Unit 304.

  The decoders 301a, 301b, 301c, 301d, and 301e are “4to16 Decoder”. The encoder 302 is “16to4 Primary Encoder”, and when there are a plurality of inputs, outputs an encoded value having a larger value. Five outputs from “00” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the “0” OR gate, and this output is input to “00” of the encoder 302.

  Five outputs from “01” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 1, and these outputs are input to “01” of the encoder 302.

  Five outputs from “02” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 2, and this output is input to “02” of the encoder 302.

  Five outputs from “03” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 3, and this output is input to “03” of the encoder 302.

  Five outputs from “04” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 4, and this output is input to “04” of the encoder 302.

  Five outputs from “05” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 5, and these outputs are input to “05” of the encoder 302.

  Five outputs from “06” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 6, and this output is input to “06” of the encoder 302.

  Five outputs from “07” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 7, and this output is input to “07” of the encoder 302.

  Five outputs from “08” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 8, and this output is input to “08” of the encoder 302.

  Five outputs from “09” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 9, and this output is input to “09” of the encoder 302.

  Five outputs from “10” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 10, and this output is input to “10” of the encoder 302.

  Five outputs from “11” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 11, and this output is input to “11” of the encoder 302.

  Five outputs from “12” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 12, and this output is input to “12” of the encoder 302.

  Five outputs from “13” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 13, and this output is input to “13” of the encoder 302.

  Five outputs from “14” of each of the decoders 301 a, 301 b, 301 c, 301 d, and 301 e are input to the OR gate 14, and this output is input to “14” of the encoder 302.

  Five outputs from “15” of each of the decoders 301 a, 301 b, 301 c, 301 d and 301 e are input to the OR gate 15, and this output is input to “15” of the encoder 302.

  Each AND gate receives the output from the first calculation unit 102 and each bit of the identification code of each relay. In FIG. 3, the identification code “0011” of the relay 1 to be processed first, the identification code “0010” of the relay 2, the identification code “0001” of the relay 3, and the identification code “0001” of the relay 4 are shown. Yes. The identification code “0011” indicates a power relay with a switching time of 3 ms, the identification code “0010” indicates a reed relay with a switching time of 1 ms, and the identification code “0001” indicates a semiconductor relay with a switching time of 0.5 ms. Is shown.

  Moreover, the output of the 1st calculating part 102 has shown that the setting information of the relay 2 differs between 1st relay setting information and 2nd relay setting information. In this case, “0, 0, 1, 0” is input to the decoder 301b, and “0, 0, 0, 0” is input to all the other decoders 301a, 301c, 301d, and 301e. The latch unit 303 is initialized to 0 before the calculation.

  As a result, "0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" is output from the decoder 301b, and the decoders 301a, 301c, 301d and 301e output “0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0”. As a result, “1” is input only to the OR gate 2, “0” is input to all the other OR gates, the output from the OR gate 2 becomes “1”, and outputs from the other OR gates. Are all "0".

  Therefore, in the case described above, “0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0” is input to the encoder 302. Thus, “0010” is output from the encoder 302. This output is latched by the latch unit 303 and input to the decoder 301e, and the next processing of relay 5, relay 6, relay 7, and relay 8 is performed.

  Since the relay 5, the relay 6, the relay 7, and the relay 8 are processed in the same manner as described above, the setting information of the relay 6 is different between the first relay setting information and the second relay setting information. The output of 102 is “0, 1, 0, 0”. The relay 6 is a power relay and the identification code is “0011”. Therefore, in this case, “0, 0, 1, 1” is input to the decoder 301b, “0010” is input to the decoder 301e, and all the other decoders 301a, 301c, and 301d have “0”. , 0, 0, 0 "is input.

  As a result, "0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" is output from the decoder 301b, and the decoder 301e outputs , “0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0” are output, and the decoders 301a, 301c, and 301d receive “0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 "is output. As a result, the OR gate 2 and the OR gate 3 have “1” inputs, the other OR gates all receive “0”, and the outputs from the OR gate 2 and OR gate 3 become “1”. The outputs from the other OR gates are all “0”.

  Therefore, in the second calculation described above, the encoder 302 has “0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0”. As a result, “0011” is output from the encoder 302. “0011” indicates a power relay with a switching time of 3 ms, and a setting condition with a longer switching time is selected. As described above, the longer the set time is, the larger the identification code is associated with, so that the relay information with the maximum switching time is selected as a result of the above-described repetitive calculation. After the processing described above is repeated for all the relays, the data conversion unit 304 converts the information into relay switching time information corresponding to the selected identification code and outputs the information. For example, the data conversion unit 304 can be configured by a ROM having a 4-bit address input.

  FIG. 4A shows the correspondence between the output bits of the first calculation unit 102 and the relay number when the calculation is repeated a plurality of times, and the inputs and relay numbers of the decoders 301a to 301d of the second calculation unit 103. Correspondence, contents of output from the encoder 302, and contents output from the latch unit 303 and input to the decoder 301e are shown. 4B shows an example of the output of the first arithmetic unit 102, the inputs of the decoders 301a, 301b, 301c, 301d, and 301e, the output from the encoder 302, and the output from the latch unit 303.

  The output switching time information is, for example, a timer value, which is counted by a counter or the like to ensure a waiting time. When the counting by the counter is finished, the control unit 104 starts the next test by the test unit 101. According to the circuit described above, it is possible to cope with a case where a large number of relays are used with a small circuit configuration.

  Next, a comparison between the device tester relay switching and the conventional device tester relay switching in the above-described embodiment will be described. First, as shown in the flowchart of FIG. 5, the relay switching of the device tester according to the present embodiment is performed by reading the relay setting information in step S501, switching the measurement circuit configuration in step S502, and by the first arithmetic unit 102 in step 503. The transition of the relay is detected, the maximum relay switching time is calculated by the second calculation unit 103 in step 504, the relay switching time is waited in step 505, and the measurement is performed in step 506. When Steps 501 to 506 are performed for all the test contents (Step S507), all the relays are turned off in Step S508, and the measurement is ended.

  In the relay switching in the above-described embodiment, the time required for step S501 is t1, the time required for step S502 is t2, the time required for step S503 is t3, the time required for step S504 is t4, and it is required for step S505. When the time is t5, the relay switching processing time t of the device tester is t = t1 + t2 + t3 + t4 + t5. Here, t3 + t4 is the number of relays / the number of parallel operations (4 in the example of FIG. 3) × clock cycle, and can be ignored because it is less than 1 us. Also, t1 + t2 is sufficiently small and can be ignored. Further, as described above, t5 = 0. As a result, in the device tester according to the embodiment, when the test content is changed without changing the relay configuration, the switching time is t≈0 ms.

  On the other hand, as shown in the flowchart of FIG. 6, the conventional device tester relay switching reads the relay setting information in step S601, switches the measurement circuit configuration in step S602, waits for the relay switching time in step 603, Measure at 604. When Steps 601 to 604 are performed for all the test contents (Step S605), all the relays are turned off in Step S606, and the measurement is ended.

  In the conventional relay switching described above, assuming that the time required for step S601 is t1, the time required for step S602 is t2, and the time required for step S603 is t5 ′, the relay switching processing time t ′ of the device tester is t ′. = T1 + t2 + t5 '. Here, t1 + t2 is sufficiently smaller than t5 'and can be ignored. However, in the past, the longest switching time (for example, 3 ms) is set to t5 ', so even if the test content is changed without changing the relay configuration, the switching time is 3 ms, for example. Therefore, according to the above-described embodiment, a measurement time reduction effect of 3 ms can be obtained. Also, for example, when the power relay with a switching time of 3 ms does not operate and the reed relay with 1 ms and the semiconductor relay with 0.5 ms operate, tt ′ = 1-3 (ms), and the measurement time of 2 ms There is a shortening effect.

  As described above, according to the present invention, the first relay setting information in the first test and the second relay setting information in the second test are set for the same relay. When exclusive OR is performed between information, and the relay information with the maximum switching time is selected from among the relays with this operation output of 1, and in addition, there is no exclusive OR output In other words, when the output of the exclusive OR for each relay is all 0, the information of the virtual relay whose switching time is 0 is used. As a result, when the test contents are switched, if the same measurement path is used, there is no waiting time, so that it is possible to suppress generation of useless waiting time.

  Next, another embodiment will be described. The first arithmetic unit in the embodiment described above constitutes a circuit as shown in FIG. 7, and the inverted output of one information and the other information between the information set for the same relay. The AND operation may be performed.

  As shown in FIG. 8, the second calculation unit uses the above-described output to newly “relay switching waiting time identification code when switching from OFF to ON” and “transition from ON to OFF” for one relay. Relay switching waiting time identification code ”is set, and these are switched by the waiting time code selection circuit 801 based on information in the relay transition table. In this case, as shown in FIG. 9, the outputs of the waiting time code selection circuits 801a, 801b, 801c, 801d corresponding to the respective relays are converted into the decoders 301a, 301b, 301c, 301d may be input, and a setting condition with a longer switching time may be selected.

  In this way, the first arithmetic unit performs a logical product operation of the inverted output of one information and the other information between pieces of information set for the same relay, and is set for the same relay. Based on the output of the first calculation unit, the relay switching waiting time identification code when transitioning from off to on and the relay switching waiting time identification code when transitioning from on to off are performed. It is good also as a structure which selects in 2 and selects the information of the relay from which the switching time shown by the selected identification code becomes the maximum in a 2nd calculating part.

  As a result, when the relay switching waiting time of the power relay from OFF to ON is 3 ms and the relay switching time from ON to OFF is 2 ms, a waiting time of 2 ms is selected when the power relay is switched from ON to OFF. For this reason, there is an effect of shortening the measurement time of 2-3 = 1 (ms) as compared with the method using exclusive OR. In this configuration, a great effect can be obtained particularly for a high voltage / high current mechanical relay having a large difference in absolute value such that the relay waiting time is 50 ms from OFF to ON and 30 ms from ON to OFF. In the present invention, by optimizing the relay switching waiting time as described above, the measurement time can be greatly shortened, the throughput of the device tester can be improved, and the test cost can be reduced.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, a plurality of test units may be provided and these may be controlled by the control unit. In this case, the first calculation unit and the second calculation unit may be provided corresponding to each test unit. Further, the control unit may be configured from computer equipment including a CPU, a main storage device, an external storage device, a network connection device, and the like. Each function is realized by the CPU operating by a program developed in the main storage device.

  In the circuit configuration shown in FIG. 3, for example, the number of decoders is not limited to five, and may be three, four, or nine. The number of decoders, the number of encoders, the code for identifying the type of relay, the number of bits used for encoding, and the like may be appropriately set in accordance with the allowable circuit scale.

  DESCRIPTION OF SYMBOLS 101 ... Test part, 102 ... 1st calculating part, 103 ... 2nd calculating part, 104 ... Control part, 111 ... 1st relay setting information storage part, 112 ... 2nd relay setting information storage part.

Claims (3)

Test means for outputting a test signal to a device to be tested to test the device;
First relay setting information in which relay information used for test signal path switching in the first test is set, and test signal path switching in the second test performed following the first test. Among the second relay setting information in which the relay information is set, a first calculation means that performs an exclusive OR between pieces of information set for the same relay;
Second computing means for selecting information on a relay having a maximum switching time among relays having a computing output of 1 in the first computing means;
Control means for controlling the test means with the switching time indicated by the information of the relay selected by the second calculation means as a waiting time from the end of the first test to the start of the second test. And at least
When there is no output from the first calculation means, the second calculation means outputs information on a relay whose switching time is set to 0. Test means for outputting a test signal to a device to be tested to test the device;
First relay setting information in which relay information used for test signal path switching in the first test is set, and test signal path switching in the second test performed following the first test. Among the second relay setting information in which the relay information is set, a second product that performs an AND operation between the inverted output of one information and the other information between the information set for the same relay. One computing means;
The identification code of the relay switching waiting time when transitioning from OFF to ON and the identification code of the relay switching waiting time when transitioning from ON to OFF are set for the same relay. A second calculation means for selecting information of the relay that is selected in each relay based on the output and that has the maximum switching time indicated by the selected identification code;
Control means for controlling the test means with the switching time indicated by the information of the relay selected by the second calculation means as a waiting time from the end of the first test to the start of the second test. And at least
When there is no output from the first calculation means, the second calculation means outputs information on a relay whose switching time is set to 0. The device tester according to claim 1 or 2,
The device tester characterized in that the first calculation means and the second calculation means encode the switching time into a larger code as the time is longer and use it for the calculation.

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