JP2013149676A - Semiconductor light-emitting element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a high-quality semiconductor light-emitting element.SOLUTION: A semiconductor light-emitting element manufacturing method comprises: (a) arranging a semiconductor layer on a substrate; (b) forming on the semiconductor layer, an electrode layer including an Au layer; and (c) alloying the electrode layer. In the process (b), the Au layer is formed while the substrate is being cooled. The process (c) includes: (c1) a first heat treatment process of heating the electrode layer in a condition of applying energy exceeding grain boundary energy at the Au layer before starting the process (c) and in a condition of not causing recrystallization to start at the Au layer; (c2) a cooling process of cooling the electrode layer to a temperature which only provides energy of grain boundary energy or lower at the Au layer after the process (c1); and (c3) a second heat treatment process of heating the electrode layer until ohmic contact with the semiconductor layer is obtained.

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device (LED).

  In order to realize high luminance and high efficiency of an AlGaInP light emitting element, a method using a metal mirror surface is known (for example, see Patent Document 1). A light emitting layer made of an AlGaInP semiconductor is formed on a GaAs substrate (growth substrate). On the other hand, a metal layer is laminated on a Si substrate (support substrate). Both substrates are bonded together via a metal layer. Thereafter, the GaAs substrate is removed by wet etching or the like, and the electrode is patterned. Furthermore, by forming the light extraction structure on the surface of the AlGaInP light emitting layer, the light extraction efficiency is improved and a highly efficient light emitting element is manufactured. A high-luminance, high-efficiency light-emitting element bonded through a metal layer (metal mirror surface) is called a metal bonding (MB) type.

In light-emitting elements made of AlGaInP-based or GaAs-based III-V group semiconductor materials, including MB type light-emitting elements, the n-side ohmic electrode is generally composed of a metal material such as AuGeNi. Although these materials are formed using a technique such as resistance heating vapor deposition, the contact resistance between the metal layer and the semiconductor layer is high as it is, and ohmic contact does not occur. Therefore, annealing is performed to a temperature at which ohmic contact is obtained in an N ₂ , Ar, H ₂ atmosphere. An example in which heat treatment is performed at 400 ° C. in an N ₂ atmosphere (for example, see Patent Document 2), an example in which heat treatment is performed at 420 ° C. for 15 minutes in an Ar atmosphere (for example, see Patent Document 3), 450 in an Ar atmosphere, An example (for example, see Patent Document 4) in which heat treatment is performed at 10 ° C. for 10 minutes is known.

  Incidentally, there is also a disclosure of an invention of a light emitting element structure in which a semiconductor layer is sandwiched between ohmic electrode materials (see, for example, Patent Document 5). According to the present invention, the electrode configuration is relatively easy, but it is necessary to devise current diffusion inside the semiconductor layer.

  On the other hand, a technique for suppressing the concentration of current by devising the arrangement and configuration of the upper and lower electrodes is disclosed (for example, see Patent Document 6). Patent Document 6 describes a method of arranging an upper electrode (ohmic electrode) and a lower electrode (ohmic electrode). Furthermore, in order to supply power to the divided upper ohmic electrode, an electrode arrangement having a Schottky characteristic that does not flow current to the semiconductor layer is required. Therefore, a method of superimposing the Schottky electrode on the ohmic electrode is disclosed. ing. By adopting a method that combines electrode materials with different electrical characteristics, such as ohmic characteristics and Schottky characteristics, it is possible to reduce the thickness of the semiconductor layer, thereby reducing light loss due to self-absorption and improving the light extraction amount. is there.

JP 2009-4487 A JP 2006-86208 A JP 2002-43621 A Japanese Patent Laid-Open No. 2005-19424 JP-A-6-90020 JP 2011-165853 A

  In order to supply power to the ohmic electrode dispersed on the LED chip, when the Schottky electrode is arranged to intersect with a part of the ohmic electrode, there is a problem if the shape of the ohmic electrode is defective.

  When making an ohmic electrode, a resist film, which is an organic material, is used as a mask, and the ohmic material is formed into a pattern. However, if the substrate is not sufficiently cooled during the film formation, the resist will be thermally deteriorated and the resist shape will be damaged. come. When the resist shape changes, the electrode material adheres to the resist wall surface, and the portion cannot be removed in a later lift-off process, and becomes a metal residue and causes an abnormality in the electrode shape.

  FIG. 7 is a photograph showing the relationship between the shape of the ohmic electrode and the shape of the Schottky electrode. Refer to the “cooling” column for substrate cooling. The ohmic electrode and the Schottky electrode are normally formed. On the other hand, referring to the “none” column of the substrate cooling, it can be seen that the Schottky electrode formed later is disconnected or has a poor contact due to the shape defect due to the metal residue of the ohmic electrode. A defective Schottky electrode causes a defective LED. Even if the disconnection is slight and there is no problem in the initial characteristics, the light intensity may be reduced or the electrical characteristics may be deteriorated due to current concentration during energization, or the lamp may be turned off in some cases. In order to prevent this, in the case of forming an electrode material using a resist mask, it is common to perform sufficient substrate cooling. For this reason, a film forming apparatus to which a function such as water cooling is added is commercially available.

  However, when an ohmic electrode is formed in such a manufacturing process, if annealing is performed to make an ohmic contact with the semiconductor layer, irregularities are formed on the electrode surface, voids are generated inside, and adversely affect energization. Has been found to affect.

  An object of the present invention is to provide a method for manufacturing a high-quality semiconductor light emitting device.

  According to one aspect of the present invention, (a) a step of disposing a semiconductor layer above a substrate, (b) a step of forming an electrode layer including an Au layer on the semiconductor layer, and (c) an alloy of the electrode layer The step (b) includes a step of forming the Au layer while cooling the substrate, and the step (c) includes the step (c1) before the start of the step (c). A first heat treatment step for heating the electrode layer under conditions that give energy exceeding grain boundary energy in the Au layer and recrystallization does not start in the Au layer; and (c2) after the step (c1) A cooling step of cooling the electrode layer to a temperature that gives only energy below the grain boundary energy in the Au layer, and (c3) a second step of heating the electrode layer until ohmic contact with the semiconductor layer is obtained. Heat treatment process The method of manufacturing a semiconductor light-emitting device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of a high quality semiconductor light-emitting device can be provided.

1A to 1D are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment. 2A to 2C are photographs showing ohmic electrodes of a semiconductor light emitting device according to a first comparative example. FIG. 3 is a photograph showing the surface of the ohmic electrode 13 of the semiconductor light emitting device according to the example. FIG. 4 is a cross-sectional photograph of the ohmic electrode 13 of the sample of the semiconductor light emitting device according to the example manufactured at a processing temperature of 250 ° C. in the first heat treatment step. FIG. 5 is a graph showing the results of an energization test. FIG. 6 is a schematic graph showing a temperature sequence of the surface heat treatment step of the n-side electrode in the method for manufacturing a semiconductor light emitting device according to the example. FIG. 7 is a photograph showing the relationship between the shape of the ohmic electrode and the shape of the Schottky electrode.

  1A to 1D are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment.

  Reference is made to FIG. 1A. For example, an n-type GaAs substrate (growth substrate) 1 having a 15 ° off-angle and a thickness of 300 μm is prepared, and a semiconductor layer 2 is formed on the (100) surface by crystal growth as follows.

As the semiconductor layer 2, first, an n-type cladding layer having a thickness of 3.0 μm, an active layer having a thickness of 0.5 μm, and a p-type cladding layer having a thickness of 1.0 μm are sequentially epitaxially grown by MOCVD. The n-type cladding layer, the active layer, and the p-type cladding layer are formed of (Al _z Ga _1-z ) _0.5 In _0.5 P. The n-type cladding layer, the active layer, and the p-type cladding layer are lattice-matched with the n-type GaAs substrate 1.

  The Al composition z of the n-type cladding layer and the p-type cladding layer is adjusted in the range of 0.4 ≦ z ≦ 1.0.

The active layer can adopt a multiple quantum well structure (MQW) or a single quantum well structure (SQW). A single layer may be used. In the case of a multiple quantum well structure, a well layer of (Al _0.1 Ga _0.9 ) _0.5 In _0.5 P and a thickness of 20 nm, (Al _0.56 Ga _0.44 ) _0.5 In _0.5 A barrier layer having a thickness of 10 nm is formed of P, and 15 pairs of both layers are alternately arranged. Lattice strain may be intentionally applied to the well layer or the barrier layer to form a strained quantum well structure. The Al composition z of the well layer is adjusted in the range of 0 ≦ z ≦ 0.4 according to the emission wavelength.

Subsequently, a 1.5 μm thick p-type current diffusion layer made of Ga _1-x In _x P is epitaxially grown on the p-type cladding layer by MOCVD. The VPE method may be used. The In composition ratio x is determined on the condition that the light emitted from the active layer is not absorbed. In the example, x = 0.1.

The materials used in the MOCVD method are arsine (AsH ₃ ) and phosphine (PH ₃ ) as group V materials, and trimethylgallium (TMGa), trimethylaluminum (TMAl), and trimethylindium (TMI) as group III materials. It is an organometallic material. The n-type impurity was Si, the raw material was silane (SiH ₄ ), the p-type impurity was Mg, and the raw material was biscyclopentadienylmagnesium (CP2Mg). Other organometallic materials may be used as raw materials. For example, organic raw materials such as tertiary butyl arsine can be used instead of arsine, and dimethyl zinc can be used instead of biscyclopentadienyl magnesium. In carrying out the MOCVD method, hydrogen was allowed to flow as a carrier gas, and the growth pressure was controlled to 10 kPa.

A dielectric reflection layer (SiO ₂ layer) 4 is formed of SiO ₂ on the p-type current diffusion layer of the semiconductor layer 2. The dielectric reflecting layer 4 is formed by, for example, forming a SiO ₂ film using a plasma CVD method, a thermal CVD method, a sputtering method, etc., and then performing photolithography and etching using buffered hydrofluoric acid (BHF). The pattern is formed by patterning. Etching may be performed by either wet etching or dry etching. The thickness d of the dielectric reflection layer 4 is defined by the following formula (1).

d = λ ₀ / (4n) × m (1)

Here, λ ₀ is the emission wavelength in vacuum, n is the refractive index of SiO ₂ , and m is an integer. In the examples, λ ₀ = 625 nm, n = 1.45, m = 3, and d = 320 nm. The dielectric reflection layer 4 can be formed of a transparent dielectric material such as Si ₃ N ₄ or Al ₂ O _{3 in} addition to SiO ₂ .

  Next, the reflective electrode layer 3 is formed. The reflective electrode layer 3 is formed by using a resistance heating vapor deposition method, an EB vapor deposition method, a sputtering method, or the like using a metal capable of forming an ohmic junction with the p-type current diffusion layer of the semiconductor layer 2. In the examples, a sputtering method was used, and AuZn was deposited to a thickness of 300 nm, so that the coverage was 17%. It is also possible to form the reflective electrode layer 3 with another highly reflective metal. The reflective electrode layer 3 functions as an ohmic electrode (p-side electrode) by forming an ohmic junction with the p-type current diffusion layer of the semiconductor layer 2 in the opening of the dielectric reflective layer 4 by an alloy process described later.

  The reflective electrode layer 3 and the dielectric reflective layer 4 constitute a reflective layer for reflecting the light emitted from the active layer toward the side opposite to the light extraction side to improve the light extraction efficiency. . That is, the reflective electrode layer 3 has a function as a p-side electrode and a function as a reflective layer in a semiconductor light emitting device after manufacture.

  After removing AuZn other than the opening of the dielectric reflective layer 4, a barrier layer 5 is formed on the reflective electrode layer 3 and on the dielectric reflective layer 4. The barrier layer 5 is formed by sequentially stacking AuZn, TaN, TiW, and TaN using a sputtering method. The film thicknesses of AuZn, TaN, TiW, and TaN are, for example, 300 nm, 100 nm, 50 nm, and 50 nm, respectively.

  The barrier layer 5 can be formed of a single layer or a multilayer film made of a refractory metal such as Ta, Ti, W, or a nitride thereof (for example, TaN). The method may be used.

  The barrier layer 5 has a function of preventing the Zn in the reflective electrode layer 3 (AuZn) from diffusing outward and preventing the eutectic material from entering (diffusing) into the reflective electrode layer 3 side in a subsequent process. Have. When the barrier layer 5 does not function sufficiently, the electrical characteristics are deteriorated, such as the drive voltage Vf of the semiconductor light emitting element increases due to the influence of heat in the subsequent process, or the reflection composed of the reflective electrode layer 3 and the dielectric reflective layer 4. The reflectance of the layer may decrease, and the luminance of the semiconductor light emitting device may decrease.

  Here, heat treatment is performed at 500 ° C. in a nitrogen atmosphere (alloy process). As a result, a good ohmic junction is formed between the p-type current diffusion layer of the semiconductor layer 2 and the reflective electrode layer 3 in the opening of the dielectric reflective layer 4.

  On the barrier layer 5, an adhesive layer 6 made of, for example, a Ni layer or an Au layer is formed by EB vapor deposition. For example, the thickness of the Ni layer is 300 nm, and the thickness of the Au layer is 30 nm. Layer formation may be performed using a resistance heating vapor deposition method, a sputtering method, or the like. The adhesive layer 6 improves the wettability with the eutectic bonding layer on the conductive support substrate side in the step of thermocompression bonding of the laminate structure including the semiconductor layer 2 and the laminate structure on the conductive support substrate side, which will be described later, It has a function of forming a good bond.

  Refer to FIG. 1B. An ohmic metal layer 8 is deposited on both surfaces of the conductive substrate (support substrate) 7. Further, on the ohmic metal layer 8 on one side, an adhesion layer 9, an adhesive layer 10, and a eutectic bonding layer 11 are formed by vapor deposition in this order.

  As the conductive substrate 7, a Si substrate to which a p-type impurity is added at a high concentration can be used. The ohmic metal layer 8 is formed using, for example, Pt. The thickness was 100 nm to 300 nm, and in the examples 200 nm. In the combination of Pt and a Si substrate to which a p-type impurity is added at a high concentration, ohmic characteristics can be obtained by simply depositing Pt, and by heating in a process such as thermocompression bonding described later, The adhesion of the metal layer 8 is improved. The ohmic metal layer 8 can be formed using a metal that can form an ohmic junction with the Si substrate, such as Au, Ni, and Ti, in addition to Pt. In that case, in order to obtain ohmic contact with the Si substrate, alloying in a nitrogen atmosphere is necessary as appropriate. The conductive substrate 7 can be formed of a material having conductivity and high thermal conductivity. In addition to Si, Ge, Al, Cu, etc. can be used.

  The adhesion layer 9 is made of, for example, Ti. The film thickness was 100 nm to 200 nm, and in the examples 150 nm. The adhesive layer 10 is made of, for example, Ni, and has a thickness of 50 to 150 nm, and in the examples, 100 nm. The adhesive layer 10 can also be formed of NiV, Pt, or the like. The eutectic bonding layer 11 formed on the adhesive layer 10 is made of, for example, AuSn.

  By providing the adhesion layer 9 and the adhesion layer 10, the adhesion reliability of the conductive substrate 7 is improved, and the wettability is improved in the step of performing thermocompression bonding with the stacked structure including the semiconductor layer 2 shown in FIG. 1A later. Further, ball-up of the eutectic bonding layer 11 can be prevented.

  The eutectic bonding layer 11 can be formed by resistance heating vapor deposition, EB vapor deposition, sputtering, or the like. The film thickness of the eutectic bonding layer 11 is 300 nm to 3000 nm, and 600 nm in the examples. The composition ratio of AuSn is desirably Au: Sn = about 80 wt%: about 20 wt% (about 70 at%: about 30 at%). In the example, the eutectic bonding layer 11 was formed at this composition ratio. The eutectic bonding layer 11 only needs to contain AuSn as a main component. For example, an additive may be added to AuSn.

  Reference is made to FIG. 1C. The laminated structure including the semiconductor layer 2 shown in FIG. 1A and the laminated structure formed on the conductive substrate 7 shown in FIG. 1B are joined by, for example, thermocompression bonding. In thermocompression bonding, the eutectic bonding layer (AuSn layer) 11 and the adhesive layer 6 (Ni layer, Au layer) form a new bonding layer (AuSnNi layer) by applying a temperature and pressure at which the eutectic material melts. In this way, the stacked structure including the semiconductor layer 2 and the stacked structure formed on the conductive substrate 7 are joined. For bonding, the adhesive layer 6 on the semiconductor layer 2 side and the eutectic bonding layer 11 on the conductive substrate 7 side are brought into close contact with each other, and held in a nitrogen atmosphere at a pressure of about 1 MPa and a temperature of 330 ° C. for 5 minutes. It was done by doing. Note that the bonding material, the atmosphere during bonding, the bonding temperature, and the bonding time do not change the characteristics of the eutectic material used (for example, deterioration of bonding strength due to oxidation or the like), and the semiconductor layer 2 Any material, atmosphere, temperature, and time may be sufficient to bond the side and the conductive substrate 7 side.

  Next, the n-type GaAs substrate 1 which is a growth substrate is removed. In the examples, the etching was removed by wet etching using an ammonia / hydrogen peroxide mixed etchant. The removal of the n-type GaAs substrate 1 is not limited to wet etching, and dry etching, mechanical polishing, chemical mechanical polishing (CMP), or the like can be used. You may carry out by the combination containing at least 1 of these.

  Reference is made to FIG. 1D. The n-type cladding layer of the semiconductor layer 2 is processed, and the light extraction structure 12 is formed on the surface of the semiconductor layer 2. First, an area where the n-side electrode is formed (an area where the light extraction structure 12 is not formed) is protected by a method such as photolithography or lift-off. Thereafter, an uneven structure is formed as the light extraction structure 12 in a region excluding the protection area. In the examples, an etchant using hydrobromic acid was used, and the time and temperature were controlled so that the light extraction structure 12 had a desired shape. The processing depth (unevenness depth) was 1.0 μm. It should be noted that a hydrochloric acid-based etchant can also be used for surface roughening (formation of the concavo-convex structure). The photonic crystal may be formed by dry etching instead of wet etching.

  Subsequently, an ohmic electrode 13 layer that is in ohmic contact with the n-type cladding layer is formed in a non-formation area of the light extraction structure 12 on the semiconductor layer 2 (n-type cladding layer). First, a resist (mask) matching a desired electrode pattern is formed. Next, AuGeNi is deposited by resistance heating evaporation as a material capable of forming an ohmic junction with the n-type semiconductor. Instead of AuGeNi, AuGe, AuSn, AuSnNi, or the like may be used. Further, a TaN layer, a TiW layer, and an Au layer are laminated in this order as a barrier layer by sputtering. The film thicknesses are, for example, 150 nm, 50 nm, and 200 nm, respectively. The barrier layer has a function of preventing outward diffusion of Ge in AuGeNi. If the barrier layer does not function sufficiently, the function of the Schottky layer to be formed later is lost, and a desired current distribution may not be obtained, and local current concentration may occur. Finally, the resist is removed by a lift-off method, and the electrode layer of the ohmic electrode 13 is formed. In the examples, the electrode coverage was 5%.

  As described in “Problems to be Solved by the Invention”, when the resist deteriorates due to heat (changes in shape) during the electrode layer formation (film formation) of the ohmic electrode 13, the film formation material is applied to the end of the electrode. It remains as a metal residue (burr). This residue causes, for example, disconnection of the Schottky electrode in the semiconductor light emitting device having a structure in which the Schottky electrode is formed on the ohmic electrode. For this reason, in the examples, during the film formation, the support of the conductive substrate 7 was sufficiently cooled to prevent resist deterioration due to heat.

  Next, the ohmic electrode 13 is electrically connected, and further, a bonding pad for electrical connection with the outside is formed. In the example, TiW, TaN, TiW, and Au, which are materials capable of Schottky connection of the n-type cladding layer, were sequentially formed by sputtering using the resist as a mask. The film thicknesses were 50 nm, 200 nm, 50 nm, and 100 nm, respectively. Next, Au was formed into a thickness of 1200 nm by resistance heating vapor deposition. Thereafter, the resist is removed by a lift-off method to form a Schottky electrode 14 layer (including a bonding pad) on the semiconductor layer 2 and the ohmic electrode 13 layer.

  Next, in order to alloy the electrode layer of the ohmic electrode 13 and form an ohmic junction between the semiconductor layer 2 and the ohmic electrode 13, the surface of the n-side electrode (the ohmic electrode layer 13 and the Schottky electrode 14) is heat-treated. . The method for manufacturing a semiconductor light emitting device according to the embodiment is characterized by this heat treatment step. In the embodiment, this heat treatment is performed twice. Specifically, first, in a heat treatment furnace in a nitrogen atmosphere, the temperature is raised to a temperature of 230 ° C. to 300 ° C. (first heat treatment step), once taken out from the furnace, and cooled to a temperature of 150 ° C. or less (cooling). Process). The contact resistance between the metal and the semiconductor is high, and ohmic contact cannot be obtained in the first heat treatment step. Subsequently, the temperature is raised to a temperature at which ohmic contact can be obtained, for example, 400 ° C. (second heat treatment step), and the heat treatment is completed.

After the heat treatment, for the purpose of surface protection, for example, a plasma CVD method, a thermal CVD method, a sputtering method or the like is used to form a SiO ₂ layer. Thereafter, cutting is performed by blade dicing or laser dicing to complete the chip.

  The semiconductor light emitting device according to the embodiment manufactured by using the method as described above is a semiconductor light emitting device that extracts light emitted from the semiconductor layer 2 from the n-side electrode side.

  Hereinafter, the semiconductor light emitting device manufactured by the manufacturing method according to the example will be described while comparing with the first to fourth comparative examples.

  In the semiconductor light emitting device according to the first comparative example, the heat treatment of the n-side electrode surface for forming the ohmic junction between the semiconductor layer 2 and the ohmic electrode 13 is performed in two steps as in the embodiment. Instead, it is a semiconductor light emitting device manufactured by raising the temperature to 400 ° C. at once. Other manufacturing processes are the same as those in the example.

  2A to 2C are photographs showing ohmic electrodes of a semiconductor light emitting device according to a first comparative example. FIG. 2A shows the ohmic electrode surface of the first comparative example. Innumerable irregularities are observed on the surface of the ohmic electrode. 2B and 2C are cross-sectional SEM photographs of the concavo-convex part. In the concavo-convex portion, it can be seen that the grain boundary of the Au layer on the outermost surface of the ohmic electrode is abnormally enlarged. It is also confirmed that innumerable voids are generated. As described in “Problems to be Solved by the Invention”, during the heat treatment of the n-side electrode for making ohmic contact with the semiconductor layer, irregularities are generated on the electrode surface and voids are generated inside the electrode. The size of the crystal grain boundary in the uppermost ohmic electrode layer (Au layer) of the first comparative example is 100 nm with a small maximum cross section length and 1200 nm or more with a large cross section. .

  FIG. 3 is a photograph showing the surface of the ohmic electrode 13 of the semiconductor light emitting device according to the example. The inventor of the present application changes the temperature in the first heat treatment step in the heat treatment of the n-side electrode surface, specifically, samples of a plurality of semiconductor light emitting devices at the treatment temperatures of 230 ° C., 250 ° C., and 300 ° C. Was made. For comparison, temperatures outside the processing temperature range in the examples, specifically, 200 ° C. (second comparative example), 325 ° C. (third comparative example), and 350 ° C. (fourth comparative example). The first heat treatment step was performed at the temperature of), and the other steps were made equal to produce a plurality of semiconductor light emitting device samples.

  In the sample of the semiconductor light emitting device according to the example (samples in which the processing temperatures in the first heat treatment step are 230 ° C., 250 ° C., and 300 ° C.), the surface of the ohmic electrode 13 is not uneven. On the other hand, in the samples of the semiconductor light emitting devices according to the second, third, and fourth comparative examples (samples in which the processing temperatures in the first heat treatment step are 200 ° C., 325 ° C., and 350 ° C., respectively), ohmic electrodes Unevenness is observed on the surface.

  FIG. 4 is a cross-sectional photograph of the ohmic electrode 13 of the sample of the semiconductor light emitting device according to the example manufactured at a processing temperature of 250 ° C. in the first heat treatment step. From the cross-sectional photograph and the longitudinal cross-sectional photograph, it can be seen that the crystal grain boundaries of the outermost Au layer of the ohmic electrode 13 are formed substantially uniformly. It was found that these crystal grain boundaries are composed of particles having a size (maximum cross-section length) of 100 nm to 300 nm. Further, as is apparent from the photograph, no void has occurred.

  Next, the inventor of the present application conducted an energization test on the semiconductor light emitting device according to the example and the semiconductor light emitting device according to the first comparative example.

  FIG. 5 is a graph showing the results of an energization test. The condition of the energization test was 135 mA at room temperature (25 ° C.), and the time-dependent changes in luminous intensity and forward voltage at 60 mA after energization were examined.

  In the semiconductor light emitting device according to the first comparative example, fluctuations in forward voltage and luminous intensity are large. In particular, the variation in luminous intensity is large, and the rise and variation are remarkable in the initial stage. This is because the desired current distribution cannot be obtained due to voids in the ohmic electrode, current concentration occurs locally in the semiconductor layer, and local crystal damage occurs in the semiconductor layer during energization. It is done.

  On the other hand, in the semiconductor light emitting device according to the example, both the forward voltage and the luminous intensity are stable.

  According to the method for manufacturing a semiconductor light emitting device according to the embodiment, it is possible to manufacture a semiconductor light emitting device in which unevenness on the surface of the ohmic electrode and generation of voids inside the electrode are suppressed. Not only can the appearance defect of the semiconductor light-emitting element be suppressed, but also the deterioration of the reliability of the semiconductor light-emitting element due to the disconnection of the electrode and current concentration due to the void generated inside the electrode can be suppressed. The semiconductor light emitting device manufactured by the manufacturing method according to the embodiment is a high quality semiconductor light emitting device.

  FIG. 6 is a schematic graph showing a temperature sequence of the surface heat treatment step of the n-side electrode in the method for manufacturing a semiconductor light emitting device according to the example. The horizontal axis of the graph represents time, and the vertical axis represents temperature. As described above, in the method for manufacturing a semiconductor light emitting device according to the embodiment, the surface heat treatment step of the n-side electrode includes the first and second heat treatment steps and the cooling step therebetween.

  In this graph, the processing temperature in the first heat treatment step is “first heat treatment temperature Th1”, the treatment time is “first heat treatment time t1”, the treatment temperature in the cooling step is “cooling temperature Tc”, and the treatment time is “cooling”. “Time t2”, the treatment temperature in the second heat treatment step is indicated as “second heat treatment temperature Th2”, and the treatment time is indicated as “second heat treatment time t3”. Further, the temperature rising gradient at the start of the first heat treatment step is Δ1, the temperature decreasing gradient at the end (cooling) is Δ2, the temperature rising gradient at the start of the second heat treatment step is Δ3, and the temperature decreasing gradient at the end (cooling). The slope was denoted as Δ4.

  In the examples, (Th1, Th2, Tc, t1, t2, t3, Δ1, Δ2, Δ3, Δ4) = (230 ° C. to 300 ° C., 400 ° C., 150 ° C., 1 second, 1 second, 1 second, 50 ° C / min, 50 ° C / min, 50 ° C / min, 50 ° C / min). Here, with regard to t1 and t3, the time required for the operation of pulling out the semiconductor light emitting element in the process from the high temperature part of the furnace immediately after reaching the target temperature was set to “1 second”. Regarding t2, the case where the temperature increase was started immediately after reaching the cooling temperature Tc toward the second heat treatment step was described as “1 second”.

  With regard to the first heat treatment time t1, even when the time is 1 second to 60 minutes, no irregularities or voids were observed in the ohmic electrode 13, and a high-quality semiconductor light emitting device was obtained. Although it can be seen that there is no problem even if the first heat treatment temperature Th1 is left for a long time, it is preferable to start the temperature decrease immediately after reaching the target temperature from the viewpoint of cost reduction.

  It has been found that the cooling temperature Tc is at least effective when the temperature is in the range of room temperature (25 ° C.) to 150 ° C.

  With regard to the cooling time t2, even when the temperature starts to rise immediately toward the second heat treatment step after reaching the cooling temperature Tc, or when the second heat treatment step is performed after being left at room temperature for several days, Both were effective. In the cooling process, it is suggested that it is important to cool to a temperature of 150 ° C. or lower.

  Regarding the second heat treatment time t3, when cooling is started immediately after reaching the second heat treatment temperature Th2 (t3 = 1 second), or when cooling is performed after maintaining the second heat treatment temperature Th2 for 30 minutes (t3 = 30 minutes), both were effective, and there was no difference in the quality of the semiconductor light emitting devices. In the second heat treatment step, it is sufficient if an ohmic contact between the semiconductor layer 2 and the ohmic electrode 13 is obtained, so that a long-time heat treatment is not necessary from the viewpoint of cost reduction.

  Regarding the temperature rising gradients Δ1 and Δ3 at the start of the first and second heat treatment steps, in addition to 50 ° C./min, 20 ° C./min and 100 ° C./min were carried out, but the effect exhibited was not affected. .

  Further, regarding the temperature drop gradient Δ2 at the end of the first heat treatment step (during cooling), even when the first heat treatment temperature Th1 was reached and taken out with tweezers and rapidly cooled with a cooling plate, the effect exhibited was not affected.

  Furthermore, the temperature decrease gradient Δ4 at the end of the second heat treatment step (during cooling) was carried out at 20 ° C./min and 100 ° C./min in addition to 50 ° C./min, but there was no effect on the effect exhibited.

  The inventor of the present application considered the reason why the surface of the ohmic electrode 13 and the generation of voids inside the ohmic electrode 13 were suppressed in the semiconductor light emitting device manufactured by the manufacturing method according to the example.

  First, in the first comparative example in which the heat treatment of the n-side electrode for making ohmic contact with the semiconductor layer was performed only once at a high temperature (400 ° C.), as described with reference to FIGS. The crystal grain boundary of the Au layer, which is the outermost layer of the electrode, results in a wide range of bonds between the crystal grain boundaries. For example, the maximum cross-sectional length is increased to 1200 nm or more, and irregularities are generated on the ohmic electrode surface. There is a void. This is because, before the heat treatment step, the substrate is cooled at the time of film formation, so the crystal grain boundaries of the Au layer are dense, but the bonding force between adjacent crystal grain boundaries is weak. It is considered that the crystal grain boundary of the Au layer was increased and the voids were accompanied by the increase in the crystallized temperature.

  On the other hand, in the method for manufacturing a semiconductor light emitting device according to the example, grain boundary growth does not occur in the first heat treatment step. In the examples, since the maximum cross-sectional length of the final crystal grain boundary of the outermost surface layer (Au layer) of the ohmic electrode 13 was 100 nm to 300 nm, the maximum cross-section of the crystal grain boundary after the first heat treatment step. It can be seen that the length does not exceed 300 nm.

  In the first heat treatment step, it is considered that by applying a certain range of energy, the bonding between the adjacent grain boundaries of the Au layer is promoted and strengthened.

  In the Au layer immediately after film formation as the outermost layer of the ohmic electrode 13 (before the surface heat treatment step of the n-side electrode), the atomic structure of the grain boundary is disturbed and the grain boundary energy is high. In the first heat treatment step, at least a condition (temperature) that gives energy exceeding the grain boundary energy is set so that energy is imparted to atoms existing at the grain boundary, and at least the grain boundary interface, and in some cases, the crystal grain A rearrangement of atoms occurs inside the field. As a result, it is considered that the disorder of the atomic structure of the grain boundary is reduced.

  In addition, the first heat treatment step is performed at a temperature lower than the recrystallization temperature that does not cause grain boundary growth (conditions in which recrystallization does not start in the Au layer). When the recrystallization temperature is exceeded, the grain boundary moves and its shape changes. The reason why the appropriate processing temperature in the first heat treatment step is higher than the recrystallization temperature of Au (around 200 ° C.) is considered to be because the Au layer contains impurities.

  The cooling step is considered to fix once the state in which atoms are arranged in a stable state and the bonds between adjacent grain boundaries are strengthened. That is, in the cooling step, the state where the maximum length of the cross section of the crystal grain boundary does not exceed 300 nm is maintained, and the atomic structure with less disturbance is fixed. For this purpose, it is necessary to reduce the temperature (energy to be added), but the temperature at this time will be equal to or lower than the grain boundary energy at this time (the temperature at which energy is applied within a range not exceeding the grain boundary energy). The cooling process restricts the movement of crystal grain boundaries, and it seems that the growth of crystal grain boundaries and the generation of voids can be suppressed.

  Here, the treatment temperature in the first heat treatment step is 230 ° C. or more, and the treatment temperature in the cooling step is 150 ° C. or less because the disorder of atoms decreases after the first heat treatment step, and the grain boundary in the Au layer This is thought to be due to a decrease in energy.

  In the process up to the cooling process, the disordered atomic structure is fixed, and the bonds between adjacent grain boundaries (bonds between atoms at the interface) are strengthened. Even if the temperature is raised to a temperature at which contact can be obtained (a temperature higher than the temperature in the first heat treatment step), no significant change occurs in the crystal grain boundary, and the grain boundary of the Au layer does not change as in the first comparative example. However, the surface of the ohmic electrode is uneven and voids are not generated inside the electrode. For this reason, according to the manufacturing method of the semiconductor light-emitting device according to the embodiment, a high-quality semiconductor light-emitting device can be manufactured.

  If heat is continuously applied without performing the cooling step, it is considered that only the adjacent crystal grain boundaries are not in a stable state, and bonding and separation between distant crystal grain boundaries are promoted. When the large movement of the crystal grain boundary is promoted, the crystal grain boundary increases, and voids are easily generated accordingly.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.

  For example, the present invention can be used for an AlGaInP-based MB type semiconductor light emitting element that is bonded via a metal layer.

1 n-type GaAs substrate 2 semiconductor layer 3 reflective electrode layer 4 dielectric reflective layer 5 barrier layer 6 adhesive layer 7 conductive substrate 8 ohmic metal layer 9 adhesion layer 10 adhesive layer 11 eutectic bonding layer 12 light extraction structure 13 ohmic electrode 14 Schottky electrode

Claims (7)

(A) a step of disposing a semiconductor layer above the substrate;
(B) forming an electrode layer including an Au layer on the semiconductor layer;
(C) alloying the electrode layer,
The step (b) includes a step of forming the Au layer while cooling the substrate,
The step (c)
(C1) A first heat treatment that heats the electrode layer under conditions that provide energy exceeding grain boundary energy in the Au layer before the start of the step (c) and recrystallization does not start in the Au layer Process,
(C2) a cooling step of cooling the electrode layer to a temperature that gives only energy below the grain boundary energy in the Au layer after the step (c1);
(C3) A method for manufacturing a semiconductor light emitting element, comprising: a second heat treatment step in which the electrode layer is heated until ohmic contact with the semiconductor layer is obtained.   2. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein in the step (c1), heating is performed in a range in which a maximum cross-sectional length of a grain boundary of the Au layer does not exceed 300 nm.   The manufacturing method of the semiconductor light-emitting device according to claim 1 or 2, wherein in the step (c1), heating is performed at a temperature of 230 ° C to 300 ° C.   The manufacturing method of the semiconductor light-emitting device according to claim 1, wherein in the step (c2), the semiconductor light-emitting device is cooled to a temperature of 150 ° C. or lower.   The method for manufacturing a semiconductor light-emitting element according to claim 1, wherein in the step (c3), heating is performed to a temperature higher than the temperature in the step (c1).   The method for manufacturing a semiconductor light-emitting element according to claim 1, wherein in the step (b), the Au layer is formed as an uppermost layer of the electrode layer. Furthermore, between the step (b) and the step (c),
(D) The manufacturing method of the semiconductor light emitting element of any one of Claims 1-6 including the process of forming a Schottky electrode layer on the said semiconductor layer and the said electrode layer.