JP2013143164A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for improving a margin of data holding characteristics of an SRAM cell.SOLUTION: A semiconductor device comprises: at least one evaluation cell; a word line level determination circuit for determining a word line level on the basis of time after a control signal changes from one of levels "H" and "L" to the other until the output node of a fourth inverter changes from one of the levels "H" and "L" to the other; and a word line drive circuit. The evaluation cell comprises: a third inverter having third PMOS and NMOSTRS; a fourth inverter having fourth PMOS and NMOSTRS; a third transfer TRS having an end, the other end, and a gate connected to an output node of the third inverter, a first bit line, and a ground power supply, respectively; a fourth transfer TRS having an end, the other end, and a gate connected to an output node of the fourth inverter, a second bit line, and a dummy word line, respectively; and a control circuit connected to a source of the fourth NMOSTRS for controlling potential of the output node of the fourth inverter on the basis of the control signal.

Description

  Embodiments described herein relate generally to a semiconductor device.

  In recent years, with the high integration of semiconductor integrated circuits and the reduction of power supply voltage, the data retention characteristics of SRAM (Static Random Access Memory) cells used in these integrated circuits may become poor.

  As a technique for improving the data retention characteristic, a technique is known in which the level of the word line is lowered in a memory cell having a poor data retention characteristic and the level of the word line is raised in a memory cell having a poor write characteristic. This is to ensure a balance between a write defect margin and a data retention characteristic margin.

A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits, IEICE. ICD 106 (207), 149-153, 2006 A 32nm High- Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation, ISSCC10

  The present embodiment is to provide a semiconductor device capable of improving a margin of data retention characteristics of an SRAM cell.

  The semiconductor device of the present embodiment includes a first inverter having a first PMOS transistor and a first NMOS transistor, a second inverter having a second PMOS transistor and a second NMOS transistor and cross-connected to the first inverter, and one end of a current path being A first transfer transistor connected to the output node of the first inverter, the other connected to the first bit line and the gate connected to the word line; and one end of the current path connected to the output node of the second inverter; A second transfer transistor having a gate connected to the word line and a gate connected to the word line; a third inverter having a third PMOS transistor and a third NMOS transistor; and a fourth PMOS transistor. And 4th NM A fourth inverter having an S transistor and cross-connected to the third inverter; one end of a current path connected to the output node of the third inverter; the other connected to the first bit line; and a gate connected to a dummy word line A fourth transfer transistor having one end of a current path connected to the output node of the fourth inverter, the other connected to the second bit line, and a gate connected to the dummy word line; A control circuit connected to the source of the fourth NMOS transistor and controlling the potential of the output node of the fourth inverter based on a control signal; and the control signal is at the “H” level and “ After the output level of the fourth inverter changes from one of the “L” levels to the other, the “H” level and the “ And a word line level determination circuit for determining a level for activating the word line based on a time until the level changes from one to the other, and driving the word line to the determined level. And a word line driving circuit.

1 is a block diagram showing a semiconductor device according to a first embodiment. 1 is a circuit diagram showing an SRAM cell according to a first embodiment. FIG. 1 is a circuit diagram showing an SRAM cell according to a first embodiment. FIG. The figure explaining SNM. The figure explaining the correlation with SNM and Tdis. 6A and 6B are diagrams illustrating an evaluation cell array according to the second embodiment. 7A and 7B are views for explaining a semiconductor device according to the second embodiment. 8A and 8B illustrate an evaluation cell array of the semiconductor device illustrated in FIGS.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
1. Overall Configuration The semiconductor device according to the first embodiment will be described with reference to FIG. As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a memory cell array 100, a first control circuit 102 that controls the row direction, and a second control circuit 104 that controls the column direction and includes a sense amplifier. A command interface circuit 106, a data input / output buffer 108, a state machine 110, an address buffer 112, and a pulse generator 114. The command interface circuit 106, the data input / output buffer 108, and the address buffer 112 operate based on a control signal from the host (controller) 120.

1.1 Memory Cell Array The memory cell array includes an SRAM cell 10 and an evaluation cell that evaluates data retention characteristics of the SRAM memory. That is, the evaluation cell is formed in a memory cell array in the same chip as the memory.

(1) SRAM Cell 10 As shown in FIG. 2, the SRAM cell 10 includes a first inverter 11, a second inverter 12, and transfer transistors (NMOS) TN ₃ and TN ₄ . The input node 13 of the first inverter 11 is connected to the output node 16 of the second inverter 12. The input node 15 of the second inverter 12 is connected to the output node 14 of the first inverter 11.

The first inverter 11 includes a PMOS transistor TP ₁ and an NMOS transistor TN ₁ . The transistor TP ₁ has one end of the current path connected to the power supply line VDD, the other end connected to one end of the current path of the transistor TN ₁ , the input node 15, and the gate connected to the input node 13. The transistor TN ₁ has one end of the current path connected to the other end of the current path of the transistor TP ₁ and the input node 15, the other end connected to the ground potential VSS, and the gate connected to the input node 13.

The second inverter 12 includes a PMOS transistor TP ₂ and an NMOS transistor TN _2. Similar to the first inverter 11, the transistor TP ₂ is connected one end of a current path to the power supply line VDD, the other end is connected one end of a current path of the transistor TN _2, the input node 13, a gate to the input node 15 Connected. The transistor TN ₂ has one end of the current path connected to the other end of the current path of the transistor TP ₂ and the input node 13, the other end connected to the ground potential VSS, and the gate connected to the input node 15.

In the transistor TN ₃ , one end of the current path is connected to the bit line BL, the other end of the current path is connected to the output node 14 of the first inverter 11, and the gate is connected to the word line WL. Furthermore, transfer transistor TN _4, one end of a current path connected to a bit line BLB, the other current path is connected to the output node 16 of the second inverter 12, a gate connected to a word line. The bit line BL and the bit line BLB constitute a pair of bit lines. _One ends of the current paths of the PMOS transistors TP ₁ and TP ₂ are connected to the drive power supply, and the other ends are connected to the output node 14 and the output node 16, respectively. One end of the current path of the NMOS transistors TN ₁ and TN ₂ is connected to the ground power supply, and the other end is connected to the output node 14 and the output node 16, respectively. The gates of transistors TP1 and TN1 are both connected to output node 16, and the gates of transistors TP2 and TN2 are both connected to output node 14.

On the other hand, as shown in FIG. 3, the evaluation cells 20 includes a SRAM cell 10A, an NMOS transistor TN _5. The SRAM cell 10A has the same configuration as the SRAM cell 10 except for the following points (1) to (4), and detailed description thereof will be omitted.

In the SRAM cell 10A, (1) a gate of the transfer transistor TN ₃ is connected to the ground power supply. (2) The gate of the transfer transistor TN ₄ is connected to the dummy word line DWL. (3) The source of the NMOS transistor TN ₂ is connected to the drain of the NMOS transistor TN ₅ . (4) The source of the NMOS transistor TN ₅ is connected to the ground power supply, the control signal CS _i-1 is input to the gate, and the control signal CS _i is output from the output node 14 of the first inverter 11.

  The semiconductor device of the present embodiment evaluates the data retention characteristics of a memory having SRAM cells formed on the same chip using the evaluation cell 20 configured as described above, and based on this evaluation result, the SRAM The cell word line is driven.

First, an evaluation method performed using the evaluation cell 20 will be described. FIG. 4 shows the eyeglass characteristics (butterfly curve) of the evaluation cell 20. The eyeglass characteristic is that the voltage transfer curve VTC (solid line) of the second inverter 12 and the inverted first inverter 11 when the potential of the control signal CS _i-1 is set to the drive voltage Vdd (eg, 1.1 V). The voltage transfer curve VTC ⁻¹ (dashed line) is shown on the same graph. At this time, the largest square in the area surrounded by the curve VTC and the curve VTC- ¹ indicates SNM (Static Noise Margin). There are two types of SNMs: a case where data is read from a cell and a case where a cell holds data. FIG. 4 shows the eyeglass characteristics in reading. In FIG. 4, the horizontal axis indicates the potential V ₁₄ of the output node 14 of the first inverter 11, and the vertical axis indicates the potential V ₁₆ of the output node 16 of the second inverter 12. 4 is obtained when the potential of the control signal CS _i-1 is set to the drive potential Vdd, and the evaluation cell 20 and the SRAM cell 10 are formed on the same chip. The eyeglass characteristics of the SRAM cell 10 shown in FIG.

In the evaluation cell 20, the dummy word line DWL is activated by applying the drive potential Vdd, and then the potential of the bit line BLB is set to the “L” level. As a result, the potential of the node 16 also becomes “L” level, and “L” data is written to the node 16. On the other hand, “H” data is written in the node 14. When the potential level of the control signal CS _i-1 is lowered from Vdd in this state, the node 16 cannot be held “L” data and is inverted. This is because the data retention characteristic is determined by the potential V ₁₆ of the node 16 depending on the ratio of the driving forces of the transfer transistor TN ₄ and the transistor TN ₂ . By reducing the potential level of the control signal CS _i−1 , the driving power of the transistor TN ₂ is reduced. Then, as shown in FIG. 4, the voltage transfer curve of the second inverter 12 rises, and the SNM decreases. As can be seen from the above description, the transistor TN ₅ controls the driving force of the transistor TN ₂ , and the transistor TN ₅ forms a driving force control circuit.

In the evaluation cell 20, bringing the potential level of the control signal CS _i-1 closer to the ground potential Vss from the drive potential Vdd means that the drive power of the transistor TN ₂ is reduced and the size of the SNM is reduced. SNM is in the data held in the node 16 even with a small amount of decrease in the control signal _{CS i-1} potential level _{V 16} is small SRAM cell 10A is reversed, in the SNM is greater SRAM cell 10A, the control signal CS _i It will be reversed when the amount of decrease in the potential level V _{16 -1} is large.

In this embodiment, the time Tdis until the “L” data held in the node 16 is inverted due to the fluctuation of the potential level V ₁₆ of the control signal CS _i−1 is used as an index of the data holding characteristic. From the above description, it can be seen that time Tdis and SNM have a positive correlation. Specifically, this will be described later with reference to FIG.

  Further, in the present embodiment, FIG. 5 shows a result of obtaining SNM and Tdis by simulation when various threshold values of the PMOS transistor and the NMOS transistor constituting the SRAM cell 10A are changed. As can be seen from FIG. 5, there is a positive correlation between SNM and Tdis.

The state machine 110 monitors the potential of the output node nb in the evaluation cell 20, and measures a time Tdis from when the potential of the output node nb reaches a desired potential after the potential level of the control signal CSi-1 is lowered, for example. . State machine 110, when the measured time Tdis is smaller than the first reference value of a predetermined is lower than the driving voltage potential V _WL for the activation of the word line WL for driving the SRAM cell 10 The first control circuit is controlled.

That is, when the time Tdis is smaller than the predetermined first reference value, it means that the corresponding SNM is also smaller than the desired SNM, but the potential V _WL for activating the word line WL that drives the SRAM cell 10. Is made lower than the drive potential, an increase in the voltage transfer curve of the second inverter 12 can be suppressed and SNM can be prevented from decreasing. As a result, the SNM can be improved, and the data retention characteristics are improved.

The state machine 110 activates the word line WL that drives the SRAM cell 10 when the measured time Tdis exceeds a predetermined second reference value that is larger than the first reference value. The potential V _WL is set higher than the driving potential. As a result, the ease of writing in a trade-off relationship with the data retention characteristics is improved, and the performance as a cell can be improved.

  As described above, according to this embodiment, the margin of the data retention characteristic of the SRAM cell can be improved.

(Second Embodiment)
A semiconductor device according to the second embodiment will be described with reference to FIGS. 6 (a) and 6 (b). The semiconductor device of this embodiment includes an SRAM array in which SRAM cells 10 shown in FIG. 2 are arranged in a matrix, and an evaluation cell array in which one row of evaluation cells 10A shown in FIG. 3 is arranged in the row direction of the SRAM array. It has. FIG. 6A shows the configuration of this evaluation cell array, and FIG. 6B shows a waveform diagram for explaining the operation thereof.

As shown in FIG. 6A, the evaluation cell array 200 includes a plurality of (three in the drawing) evaluation cells 20 ₁ , 20 ₂ , and 20 ₃ arranged in one row. Each evaluation cell 20 _i (i = 0, 1, 2) has the same configuration as the evaluation cell 20 shown in FIG. That is, the evaluation cells ₂₀ i (i = 90,1,2) comprises a SRAM cell 10A, an NMOS transistor TN _5. SRAM cell 10A, like SRAM cell 10, PMOS transistors TP ₁ and a first inverter having an NMOS transistor TN _1, and a second inverter having a PMOS transistor TP ₂ and an NMOS transistor TN _2, transfer transistor _TN 3, and a TN _4. However, in the SRAM cell 10A, the gate of the transfer transistor TN ₃ is connected to the ground power supply, the source of the NMOS transistor TN ₂ is a configuration that is connected to the drain of the NMOS transistor TN _5. The transfer transistor TN ₃ of each evaluation cell 20 _i (i = 0, 1, 2) has one end of the current path connected to the bit line BL _i and the other end of the current path connected to the output node of the first inverter. Is connected to the dummy word line DWL. The transfer transistor TN ₄ of each evaluation cell 20 _i (i = 0, 1, 2) has one end of the current path connected to the bit line BLB _i and the other end of the current path connected to the output node of the second inverter. The gate is connected to the dummy word line DWL. The bit line BL _i (i = 0, 1, 2) and the bit line BLB _i constitute a pair of bit lines.

NMOS transistor TN ₅ of evaluation cells 20 ₀ has a source connected to the ground power supply, the gate, the control signal CS ₀ from the terminal S is input, the output node of the first inverter 11, i.e. controlled from the drain of the PMOS transistor TP ₁ Signal CS ₁ is output.

Further, NMOS transistor TN ₅ of the evaluation cells 20 ₁ has a source connected to the ground power supply, the gate control signal CS ₁ is input, the output node of the first inverter 11, that is, the control signal CS from the drain of the PMOS transistor TP _{1 2} is output.

Further, NMOS transistor TN ₅ of evaluation cells 20 ₂ has a source connected to the ground power supply, the gate control signal CS ₂ is input, the output node of the first inverter 11, that is, the control signal CS from the drain of the PMOS transistor TP _{1 3} is output.

In such evaluation cell array 200 configured, the evaluation cell 200 ₀ is an evaluation cell in the first stage, the evaluation cell _{200 i + 1 (i = 0,1} ) is the next stage of the evaluation cell evaluation cell 200 _i.

Next, the operation of the evaluation cell array 200 according to the second embodiment will be described with reference to FIG. The operation of the evaluation cell array 200 has two phases: a write phase and an evaluation phase. In the write phase, data is written using the column decoders 400 ₁ and 400 ₂ in FIGS. 7A and 7B. In the evaluation phase, the control signal CS is input to the evaluation cell array 200 using the row decoders 300 ₁ and 300 ₂ in FIGS. 7A and 7B.

First, the write phase will be described. The word line level determination circuit 600 sets “L” data to the bit line BLB _i (i = 0, 1, 2) via the multiplexers 500 ₁ and 500 ₂ and activates the dummy word line DWL. That is, the drive voltage Vdd is applied to the dummy word line DWL. Then, the “L” data set in the bit line BLB _i (i = 0, 1, 2) is sent to and held in the node nb _i of each evaluation cell 20 _i via the transfer transistor TN4. That is, “L” data is written in each evaluation cell 20 _i (i = 0, 1, 2). At this time, the control signal CS _i (i = 0, 1, 2) is maintained at the “H” level, that is, the drive potential Vdd. An evaluation phase is performed after the writing phase is completed.

In the evaluation phase, the word line level determination circuit 600 sets “H” data to the bit line BLB _i (i = 0, 1, 2) via the multiplexers 500 ₁ and 500 ₂ and activates the dummy word line DWL. To do. The potentials of CS ₀ terminal S from the driving voltage Vdd is changed to the ground potential Vss. Then, the change in the potential of the terminal S becomes a trigger, and the “L” data written in the node nb _i of each evaluation cell 20 _i (i = 0, 1, 2) becomes the evaluation cell 20 ₀ , 20 ₁ , 20 _2. It will be destroyed in the order. This destruction of data is performed while the dummy word line DWL is active. At this time, as shown in FIG. 6B, from the rise of the potential of the node nb _i of the evaluation cell 20 _i (i = 0, 1, 2), the potential of the node nb _{i + 1} of the next evaluation cell 20 _{i + 1} The time until the rise is Tdis.

In this evaluation phase, when the dummy word line DWL is in the active state, the row decoder 300 determines the number of evaluation cells whose data is destroyed based on the evaluation result input from the word line level determination circuit 600 in the first stage. counted from the evaluation cells, compared with the values T _sigma and the first and second reference value obtained by multiplying the Tdis to this number, and controls the potential applied to the word line of the SRAM cell array on the basis of the comparison result.

In the evaluation phase, a specific example of detecting how many stages of evaluation cells have data corruption will be described with reference to FIGS. 7 (a) and 7 (b). Consider a semiconductor device in which _four SRAM cell arrays 200 ₁ to 2004 are arranged in a matrix as shown in FIG. This semiconductor device includes a row decoder 300 ₁ is disposed between the SRAM cell array 200 ₁ and the SRAM cell array 200 _2, the row decoder 300 ₂ is provided between the SRAM cell array 200 ₃ and the SRAM cell array 200 _4, the SRAM cell array 200 ₁ and the column decoder 400 ₁ between the SRAM cell array 200 ₃ are provided, a configuration in which the column decoder 400 ₂ is provided between the SRAM cell array 200 ₂ and the SRAM cell array 200 _4.

In the semiconductor device configured as described above, one row of evaluation cell arrays 200 is provided in each SRAM cell array 100 _i (i = 1, 2, 3, 4). This is shown in FIG. Then, the evaluation cell array 200 is divided into four stages, and the bit line pairs BL and BLB of the divided four stages of evaluation cells are connected to one multiplexer, and the data of the evaluation cell array is read through the bit line pairs BL and BLB. The number of evaluation cells up to which level data destruction is detected is detected. For example, as shown in FIG. 8, the evaluation cell ₂₀₀ 1 to 200 ₃ are connected to the multiplexer ₅₀₀₁ via a pair of bit lines _{BL 0, BLB 0 ~BL 3,} BLB 3, the evaluation cell ₂₀₀ 4-200 _7-bit It is connected to a multiplexer ₅₀₀₂ via a line pair _{BL 4, BLB 4 ~BL 7,} BLB 7. Then, the word line WL _{n + 1} connected to the evaluation cell array 200 is activated for a predetermined period, and evaluation is performed in the evaluation phase mode as in the first embodiment. This evaluation result, that is, the result indicating how many stages of evaluation cells have data destruction, is obtained by sending the output of each multiplexer to the word line level determination circuit 600 and reading it out. Based on the evaluation result, the potential _{V WL} for activating the SRAM cell array 200 _{and second} word lines is determined by the word line level determining circuit 600. Based on the determined potential _{V WL,} row decoder 300 ₁ activates the word line in the SRAM array 100 _2. When the evaluation result is smaller than a predetermined first reference value, the potential V _WL for activating the word line that drives the SRAM cell is set lower than the drive potential. As a result, the SNM can be improved and the data retention characteristics are improved. When the evaluation result exceeds a predetermined second reference value larger than the first reference value, the potential V _WL for activating the word line that drives the SRAM cell is made higher than the drive potential. . As a result, the ease of writing in a trade-off relationship with the data retention characteristics is improved, and the performance as a cell can be improved.

The evaluation cell array 200 is provided in each SRAM cell array, and the potential V _WL for activating the word line is determined corresponding to each SRAM cell array. Alternatively, one evaluation cell array 200 may be provided for a plurality of SRAM cell arrays, and the potential V _WL for activating the word lines of the plurality of SRAM cell arrays may be set based on the result detected from the evaluation cell array. .

  Note that the evaluation cell array 200 is provided in the n + 1th row of the SRAM cell array in FIGS. 7A and 7B, but may be provided in the first row.

  In the above description, the evaluation result is obtained by detecting how many stages of evaluation cells have data destruction within the period in which the dummy word line DWL of the evaluation cell array 200 is activated. As an alternative method, the evaluation result may be obtained by measuring the time until all the evaluation cells in the evaluation cell array 200 are destroyed.

  The evaluation phase mode may be performed when the power is turned on or periodically after the power is turned on.

  Similarly to the first embodiment, the second embodiment can improve the margin of the data retention characteristic of the SRAM cell.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof as well as included in the scope and gist of the invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 SRAM cell 10A SRAM cell 11 1st inverter 12 2nd inverter 13 Input node of 1st inverter 14 Output node of 1st inverter 15 Input node of 2nd inverter 16 Output node of 2nd inverter 20 Evaluation cell 100 Memory Cell array 102 first control circuit 104 second control circuit 106 command interface circuit 108 data input / output circuit 110 state machine 112 address buffer 114 pulse generator

Claims (4)

A first inverter having a first PMOS transistor and a first NMOS transistor, a second inverter having a second PMOS transistor and a second NMOS transistor and cross-connecting to the first inverter, and one end of a current path at the output node of the first inverter A first transfer transistor, the other connected to the first bit line and the gate connected to the word line; one end of the current path connected to the output node of the second inverter; the other connected to the second bit line; A second transfer transistor connected to the word line, at least one SRAM cell comprising:
A third inverter having a third PMOS transistor and a third NMOS transistor, a fourth inverter having a fourth PMOS transistor and a fourth NMOS transistor and cross-connected to the third inverter, and one end of a current path serving as an output node of the third inverter A third transfer transistor having the other connected to the first bit line and a gate connected to the dummy word line; one end of the current path connected to the output node of the fourth inverter; the other connected to the second bit line A fourth transfer transistor having a gate connected to the dummy word line, and a control circuit connected to a source of the fourth NMOS transistor and controlling a potential of an output node of the fourth inverter based on a control signal. At least one evaluation cell;
The time from when the control signal changes from one of the “H” level and “L” level to the other until the output node of the fourth inverter changes from one of the “H” level and “L” level to the other. A word line level determining circuit for determining a level for activating the word line,
A word line driving circuit for driving the word line to be at the determined level;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the control circuit includes a fifth NMOS transistor having a drain connected to a source of the fourth NMOS transistor, a source grounded, and a gate receiving the control signal. When m and n are integers of 2 or more, an SRAM cell array in which the SRAM cells are arranged in m rows and n columns,
The evaluation cell is provided corresponding to each column of the SRAM cell array, the dummy word line is common, and the first and second bit lines of each evaluation cell are the first and second of the corresponding column of the SRAM cell array. In the evaluation cell array connected to each bit line, the control signal in the evaluation cell corresponding to the i-th (i = 2,..., N) column is the first in the evaluation cell corresponding to the i-th column. An evaluation cell array configured to be a signal from an output node of the four inverters;
With
The word line level determination circuit detects how many columns of the evaluation cells have changed in the output node of the fourth inverter while the dummy word line is activated, or first Detecting a time from when the evaluation cell in the column receives the control signal until the output node of the fourth inverter of the evaluation cell in the last column changes, and activating the word line based on the detection result 3. The semiconductor device according to claim 1, wherein the level is determined.   4. The semiconductor device according to claim 1, wherein the evaluation cell array is provided before the first row or after the last row of the SRAM cell array.

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