JP2013141024A - Plasma etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance uniformity of etching characteristics in the etching of an insulator film or an organic film containing Si.SOLUTION: The capacitor coupling plasma etching device divides an upper electrode, in the radial direction, into an inner upper electrode 60 and an outer upper electrode 62, and applies first and second DC voltages V, Vfrom two variable DC power supplies 80, 82 simultaneously to both upper electrodes 60, 62. For example, in the etching of an insulator film containing Si, the first DC voltage Vbeing applied to the inner upper electrode 60 is selected to have an appropriate value of negative polarity (preferably, from -600 V to -150 V), and the second DC voltage Vbeing applied to the outer upper electrode 62 is varied within an appropriate range of negative polarity (preferably, from -1500 V to -300 V), thus controlling the in-plane distribution characteristics of E/R freely, while enhancing the in-plane uniformity easily.

Description

  The present invention relates to a technique for performing plasma processing on a substrate to be processed, and more particularly to a plasma etching method using a capacitively coupled plasma processing apparatus.

  In processes such as etching, deposition, oxidation, sputtering and the like in the manufacturing process of semiconductor devices and FPDs (Flat Panel Displays), plasma is often used in order to cause a favorable reaction to a processing gas at a relatively low temperature. Conventionally, in a single wafer type plasma processing apparatus, a capacitively coupled plasma processing apparatus that can easily realize a large-diameter plasma has been mainly used.

  In general, in a capacitively coupled plasma processing apparatus, an upper electrode and a lower electrode are arranged in parallel in a processing vessel configured as a vacuum chamber, and a substrate to be processed (semiconductor wafer, glass substrate, etc.) is placed on the lower electrode. A high frequency is applied between both electrodes. Then, the electrons accelerated by the high-frequency electric field between the electrodes, the secondary electrons emitted from the electrodes, or the heated electrons cause ionization collisions with the molecules of the processing gas, and plasma of the processing gas is generated. Desired fine processing such as etching is performed on the substrate surface by the radicals and ions therein.

  In a plasma etching apparatus, a relatively high frequency (normally 40 MHz or more) suitable for plasma generation (high frequency discharge) and a relatively low frequency (normally 13.56 MHz) suitable for ion attraction (bias) to the substrate. The lower two-frequency application method in which the second high frequency of the following is simultaneously applied to the lower electrode has been widely used.

  By the way, in a capacitively coupled plasma processing apparatus that handles large-diameter plasma, it is difficult to make the plasma process uniform at each position on the substrate, and it is a big problem to solve this from the viewpoint of product yield. In general, in a plasma processing apparatus, the plasma density distribution in a chamber is likely to vary depending on process parameters (pressure, RF power, gas type, etc.), so that a uniform process result can be obtained under certain process conditions. However, when the process conditions are changed in accordance with the required specifications of the processing characteristics, the uniformity is often deteriorated, and it is difficult to realize a chamber structure that can always guarantee the process uniformity over a wide range of process conditions. In particular, when etching a multi-layered film on a substrate continuously in multiple steps, the process parameters and etching mask materials used differ for each step or each processed film. It is difficult to obtain good uniformity.

  On the other hand, since the technique (Patent Document 1) for controlling the impedance of an electrode, which is conventionally known as an adjustment knob for changing the plasma density distribution, by an electric circuit is not an active control method, various processes or processes are used. It was difficult to respond flexibly to changing conditions, which was insufficient for the level of uniformity required in today's plasma processes.

JP 2004-96066 A

  The present invention has been made in view of such problems of the prior art, and provides a plasma etching method that improves the uniformity of etching characteristics in etching of an insulating film or organic film containing Si.

  A plasma etching method according to a first aspect of the present invention includes a processing container that can be evacuated, a lower electrode on which a substrate to be processed is placed in the processing container, and a direct opposite of the lower electrode in the processing container. An inner upper electrode, an outer upper electrode that is insulated from the inner upper electrode in the processing container and arranged in a ring shape radially outward, and a process between the inner and outer upper electrodes and the lower electrode. A processing gas supply unit that supplies a desired processing gas to the space, and a first high-frequency power supply unit that applies a first high frequency for generating plasma of the processing gas by high-frequency discharge to the lower electrode or the inner and outer upper electrodes A first DC power supply that applies a variable first DC voltage to the inner upper electrode, and a second DC power supply that applies a variable second DC voltage to the outer upper electrode A plasma etching method of etching a Si-containing insulating film using a plasma processing apparatus having the above structure, wherein both of the first and second DC voltages are negative and the absolute value of the second DC voltage is The value is greater than or equal to the absolute value of the first DC voltage.

In a more specific aspect of the present invention, in the etching process for forming a contact hole in the SiO ₂ film, the first DC voltage is selected from −600 V to −150 V, and the second DC voltage is −1000 V to −1000 V. 150V is selected. The frequency of the second high frequency may be selected from 2 MHz to 3.2 MHz. By varying the second DC voltage, it is possible to effectively vary the etching rate at the edge of the substrate with little or no change in the etching rate at the center of the substrate, and improve the uniformity of the etching rate. You can also.

In another aspect, in the etching process for forming a via hole in the SiOC film, the first DC voltage is selected from −900 V to −300 V, and the second DC voltage is selected from −1500 V to −300 V. The frequency of the second high frequency may be selected from 10 MHz to 13.56 MHz. In addition, an etching gas containing a fluorocarbon gas, an inert gas, and O ₂ gas or N ₂ gas can be suitably used as the processing gas. Again, by varying the second DC voltage, it is possible to effectively vary the etching rate at the edge of the substrate with little or no change in the etching characteristics at the center of the substrate. It can also be improved.

  In another aspect, in the etching process for transferring the mask pattern to the SiN film of the intermediate layer or the lowermost layer in the multilayer resist method, the first DC voltage is selected from −300 V to 0 V, and the second DC voltage Is selected from -900V to -300V. The frequency of the second high frequency may be selected from 10 MHz to 13.56 MHz. In this case, by changing the second DC voltage, not only can the etching rate at the center of the substrate be changed but also the etching rate at the edge of the substrate can be effectively varied, and the CD shift of the pattern can also be reduced. Since the substrate edge portion can be effectively varied as compared with the center portion, CD uniformity can be improved.

  A plasma etching method according to a second aspect of the present invention includes a processing container that can be evacuated, a lower electrode on which a substrate to be processed is placed in the processing container, and a direct opposite of the lower electrode in the processing container. An inner upper electrode, an outer upper electrode that is insulated from the inner upper electrode in the processing container and arranged in a ring shape radially outward, and a process between the inner and outer upper electrodes and the lower electrode. A processing gas supply unit that supplies a desired processing gas to the space, and a first high-frequency power supply unit that applies a first high frequency for generating plasma of the processing gas by high-frequency discharge to the lower electrode or the inner and outer upper electrodes A first DC power supply that applies a variable first DC voltage to the inner upper electrode, and a second DC power supply that applies a variable second DC voltage to the outer upper electrode A plasma etching method in which an organic film is etched using a plasma processing apparatus having the following: both the first and second DC voltages are negative, and the absolute value of the second DC voltage is the first DC It is characterized by being larger than the absolute value of the voltage.

In the plasma etching method, preferably, the first DC voltage is selected from −100 V to 0 V, and the second DC voltage is selected from −900 V to 0 V. The frequency of the second high frequency may be selected from 10 MHz to 13.56 MHz. An etching gas containing O ₂ gas or N ₂ gas can be preferably used as the processing gas. In this case, by varying the second DC voltage, it is possible to effectively vary the etching rate at the center of the substrate with little or no change in the etching rate at the substrate edge, and the etching rate is uniform. It can also improve the performance.

  According to the plasma etching method of the present invention, the uniformity of the etching characteristics can be improved in the etching process of the insulating film or organic film containing Si by the above-described configuration and action.

It is a longitudinal cross-sectional view which shows the structure of the capacitive coupling type plasma etching apparatus in one Embodiment of this invention. Is a diagram showing an in-plane distribution characteristic of the SiO ₂ film blanket etch experiments obtained in etching rate (E / R) in the embodiment. It is a figure which shows the in-plane distribution characteristic of E / R change rate when the value of the 2nd DC voltage applied to an outer side upper electrode is changed in the etching of FIG. It is a diagram showing an in-plane distribution characteristic of the SiO ₂ film in the contact hole formation to HARC etching experiments resulting etching rate (E / R) in the embodiment. FIG. 5 is a diagram showing an in-plane distribution characteristic of an E / R change rate when the value of the second DC voltage applied to the outer upper electrode is changed in the etching of FIG. 4. It is a figure which shows the structure which provides a level | step difference in an electrode gap direction between an inner side upper electrode and an outer side upper electrode in the said plasma etching apparatus. It is a figure which shows the in-plane distribution characteristic of the etching rate (E / R) obtained by the experiment of HARC etching using the electrode structure of FIG. It is a figure which shows the in-plane distribution characteristic of the electron density (Ne) obtained by the experiment of HARC etching in embodiment. It is a figure which shows the in-plane distribution characteristic of Ne change rate when the value of the 2nd DC voltage applied to an outer side upper electrode is changed in the etching of FIG. It is a figure which shows the process sequence of the multilayer resist method in embodiment. It is a figure which shows the in-plane distribution characteristic of the etching rate (E / R) obtained by the etching of the organic film contained in the multilayer resist of FIG. It is a figure which shows the in-plane distribution characteristic of E / R change rate when the value of the 2nd DC voltage applied to an outer side upper electrode is changed in the etching of FIG. It is sectional drawing (SEM photograph) which shows the shape of the pattern obtained by the etching of the antireflection film and organic film contained in the multilayer resist of FIG. It is a figure which shows the in-plane distribution characteristic of the etching rate (E / R) obtained by the etching of the SiN film | membrane contained in the multilayer resist of FIG. It is a figure which shows the in-plane distribution characteristic of CD shift when the value of the 2nd DC voltage applied to an outer side upper electrode is changed in the etching of FIG. It is a longitudinal cross-sectional view which shows the structure of the modification of the said capacitive coupling type plasma etching apparatus.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 shows the configuration of a plasma etching apparatus according to an embodiment of the present invention. This plasma processing apparatus is configured as a cathode-coupled capacitively coupled plasma etching apparatus adopting a lower two-frequency application method, and has a metal cylindrical chamber (processing vessel) 10 made of, for example, aluminum or stainless steel. ing. The chamber 10 is grounded for safety.

  In the chamber 10, for example, a disk-shaped susceptor 12 on which a semiconductor wafer W is placed as a substrate to be processed is horizontally disposed as a lower electrode. The susceptor 12 is made of, for example, aluminum, and is supported by an insulating cylindrical support portion 14 that extends vertically upward from the bottom of the chamber 10. An annular exhaust path 18 is formed between the conductive cylindrical support portion (inner wall portion) 16 extending vertically upward from the bottom of the chamber 10 and the side wall of the chamber 10 along the outer periphery of the cylindrical support portion 14. A ring-shaped baffle plate (exhaust ring) 20 is attached to the inlet of the exhaust path 18, and an exhaust port 22 is provided at the bottom of the exhaust path 18. An exhaust device 26 is connected to the exhaust port 22 via an exhaust pipe 24. The exhaust device 26 has a vacuum pump such as a turbo molecular pump, and can reduce the processing space in the chamber 10 to a desired degree of vacuum. A gate valve 28 for opening and closing the loading / unloading port for the semiconductor wafer W is attached to the side wall of the chamber 10.

  First and second high frequency power supplies 30 and 32 are electrically connected to the susceptor 12 via a matching unit 34 and a power feed rod 36. Here, the first high frequency power supply 30 outputs a first high frequency having a frequency (usually 40 MHz or more) that mainly contributes to plasma generation. The second high frequency power supply 32 outputs a second high frequency having a frequency (usually 13.56 MHz or less) that contributes mainly to ion attraction to the semiconductor wafer W on the susceptor 12. The matching unit 34 includes a first matching unit for matching between the impedance on the first high-frequency power source 30 side and the impedance on the load (mainly electrodes, plasma, chamber) side, and the second high-frequency power source 32 side. A second matching unit for matching between the impedance and the impedance on the load side is accommodated.

  A semiconductor wafer W to be processed is placed on the susceptor 12, and a focus ring (correction ring) 38 is provided so as to surround the semiconductor wafer W. The furcus ring 38 is made of a conductive material such as Si, SiC or the like that has little adverse effect on the process, and is detachably attached to the upper surface of the susceptor 12 as a consumable part.

  On the upper surface of the susceptor 12, an electrostatic chuck 40 for attracting the wafer is provided. The electrostatic chuck 40 has a sheet-like or mesh-like conductor sandwiched between a film-like or plate-like dielectric. A DC power source 42 disposed outside the chamber 10 is electrically connected to the conductor via an on / off switch 44 and a power supply line 46. The semiconductor wafer W can be attracted and held on the electrostatic chuck 40 by a Coulomb force by a DC voltage applied from the DC power source 42.

  An annular coolant chamber 48 extending in the circumferential direction, for example, is provided inside the susceptor 12. A coolant having a predetermined temperature, such as cooling water, is circulated and supplied to the coolant chamber 48 through pipes 50 and 52 from a chiller unit (not shown). The temperature of the semiconductor wafer W on the electrostatic chuck 40 can be controlled by the temperature of the coolant. Further, in order to further increase the accuracy of the wafer temperature, a heat transfer gas such as He gas from a heat transfer gas supply unit (not shown) is passed through the gas supply pipe 54 and the gas passage 56 inside the susceptor 12 to form an electrostatic chuck. 40 and the semiconductor wafer W.

  A disk-shaped inner (or center) upper electrode 60 and a ring-shaped outer (or peripheral) upper electrode 62 are provided concentrically on the ceiling of the chamber 10 so as to face the susceptor 12 in parallel. As a preferred size in the radial direction, the inner upper electrode 60 has the same diameter (diameter) as the semiconductor wafer W, and the outer upper electrode 62 has the same diameter (inner diameter / outer diameter) as the focus ring (correction ring) 38. )have. However, the inner upper electrode 60 and the outer upper electrode 62 are electrically insulated from each other (more accurately, DC). In the illustrated configuration example, a ring-shaped insulator 63 made of ceramic, for example, is inserted between the electrodes 60 and 62.

  The inner upper electrode 60 has an electrode plate 64 facing the susceptor 12 directly in front, and an electrode support 66 that detachably supports the electrode plate 64 from the back (upper side) thereof. The material of the electrode plate 64 is preferably a silicon-containing conductive material such as Si or SiC that has little adverse effect on the process and can maintain good DC application characteristics. The electrode support 66 may be made of anodized aluminum.

  The outer upper electrode 62 also has an electrode plate 68 that faces the susceptor 12 and an electrode support 70 that removably supports the electrode plate 68 from behind (upper). The electrode plate 68 and the electrode support 70 may also be made of the same material as the electrode plate 64 and the electrode support 66 of the inner upper electrode 60, respectively.

  In this embodiment, in order to supply the processing gas to the processing space PS set between the upper electrodes (60, 62) and the susceptor 12, the inner upper electrode 60 is also used as a shower head. More specifically, a gas diffusion chamber 72 is provided inside the electrode support 66, and a number of gas discharge holes 74 penetrating from the gas diffusion chamber 72 toward the susceptor 12 are formed in the electrode support 66 and the electrode plate 64. . A gas supply pipe 78 from the processing gas supply unit 76 is connected to a gas introduction port 72 a provided in the upper part of the gas diffusion chamber 72. Note that a shower head may be provided not only on the inner upper electrode 60 but also on the outer upper electrode 62.

Outside the chamber 10, for example, two variable DC power sources 80 and 82 that can output variable DC voltages V _C and V _E in a range of −2000 to +1000 V are provided. In the plasma etching method of the present invention, as described below, both the DC voltage V _C, V _E is usually 0V following values i.e. negative (-) is used with the value of each of the absolute value | V _C | , | V _E |, they are used together while maintaining the relationship of | V _C | ≦ | V _E |.

The output terminal of one variable DC power supply 80 is electrically connected to the inner upper electrode 60 via an on / off switch 84 and a filter circuit 86. The filter circuit 86 applies the first DC voltage V _C output from the variable DC power source 80 to the inner upper electrode 60 through, while passing from the susceptor 12 through the processing space PS and the inner upper electrode 60 to the DC power supply line 88. The high frequency wave that has entered is configured to flow to the ground line and not to the variable DC power supply 80 side.

The output terminal of the other variable DC power source 82 is electrically connected to the outer upper electrode 62 via an on / off switch 90 and a filter circuit 92. The filter circuit 92 applies the second DC voltage V _E output from the variable DC power supply 82 to the outer upper electrode 62 through, while passing from the susceptor 12 through the processing space PS and the outer upper electrode 62 to the DC power supply line 94. The high frequency wave that has entered is configured to flow to the ground line and not to the variable DC power supply 82 side.

Further, as a suitable location facing the processing space PS in the chamber 10, for example, a ring-shaped DC ground part (DC grounding electrode) 96 made of a conductive member such as Si, SiC or the like is provided outside the outer upper electrode 62 in the radial direction. It is attached. The DC ground part 96 is attached to a ring-shaped insulator 98 made of ceramic, for example, and is also connected to the ceiling wall of the chamber 10, and is always grounded via the chamber 10. When a DC voltage (V _C , V _E ) is applied to the upper electrodes (60, 62) from the variable DC power sources 80, 82 during plasma processing, the upper electrodes (60, 62) and the DC ground part 96 are connected via plasma. DC electronic current flows between them.

  Each part in the plasma etching apparatus, for example, the exhaust device 26, the high-frequency power sources 30, 32, the electrostatic chuck on / off switch 44, the processing gas supply unit 76, the DC application on / off switch 84, 90, and the chiller. Individual operations of the unit (not shown), the heat transfer gas supply unit (not shown), and the operation (sequence) of the entire apparatus are controlled by a control unit (not shown) composed of, for example, a microcomputer.

  In order to perform etching in this plasma etching apparatus, first, the gate valve 28 is opened, and the semiconductor wafer W to be processed is loaded into the chamber 10 and placed on the electrostatic chuck 40. Then, an etching gas (generally a mixed gas) is introduced into the chamber 10 from the processing gas supply unit 76 at a predetermined flow rate, and the pressure in the chamber 10 is adjusted to a set value by the exhaust device 26. Further, the first and second high frequency power supplies 30 and 32 are turned on to output the first high frequency (40 MHz or higher) and the second high frequency (13.56 MHz or lower) at a predetermined power, respectively. The voltage is applied to the susceptor 12 through the power supply rod 36. Further, the switch 44 is turned on, and the heat transfer gas (He gas) is confined in the contact interface between the electrostatic chuck 40 and the semiconductor wafer W by the electrostatic adsorption force. The etching gas discharged from the shower head 60 is turned into plasma by high-frequency discharge between both electrodes 12, (60, 62), and the film to be processed on the surface of the semiconductor wafer W has a desired pattern by radicals and ions generated by the plasma. Is etched.

  In this capacitively coupled plasma etching apparatus, by applying a first high frequency of a relatively high frequency suitable for plasma generation of 40 MHz or more to the susceptor 12, the plasma is densified in a preferable dissociation state, and even under a lower pressure condition High density plasma can be formed. At the same time, by applying a second high frequency wave having a relatively low frequency suitable for ion attraction of 13.56 MHz or less to the susceptor 12, anisotropic etching with high selectivity for the film to be processed of the semiconductor wafer W is performed. Can be applied. However, the first high frequency for plasma generation is always used in any plasma process, but the second high frequency for ion attraction may not be used depending on the process.

The main feature of this capacitively coupled plasma etching apparatus is that, as described above, the upper electrode is divided into the inner upper electrode 60 and the outer upper electrode 62 in the radial direction, and the first and second variable DC power supplies 80 and 82 are used. Two DC voltages V _C and V _E are applied to both upper electrodes 60 and 62 simultaneously. By appropriately selecting a combination of these two DC voltages V _C and V _E , the uniformity of the plasma process and etching characteristics can be improved in various applications. Hereinafter, an embodiment of an etching method using this plasma etching apparatus will be described.

Application of HARC (High Aspect Ratio Contact) that forms thin and deep contact holes in SiO ₂ film, SiOC film, etc. and BEOL (Back End Of Line) that forms relatively shallow via holes as etching processes for insulating films containing Si Is well known.

FIG. 2 shows in-plane distribution characteristics of the etching rate (E / R) obtained in an experiment in which the blanket SiO ₂ film was etched on the entire surface using the plasma etching apparatus of the embodiment. The main etching conditions are as follows.
Wafer diameter: 300mm
Etching gas: C ₄ F ₈ / Ar / O ₂ = 45/200/30 sccm
Pressure in chamber: 15mTorr
High frequency power: 40MHz / 2MHz = 1000 / 3000W
Temperature: Upper electrode / chamber sidewall / lower electrode = 60/60/20 ° C.
DC voltage: V _C = -300V, V _E = -300V, -900V (2 types)

FIG. 3 shows the E / R change rate at each position on the wafer when the second DC voltage V _E is changed from −300V to −900V.

As shown in FIG. 2, in the case of V _C / V _E = −300 V / −300 V, the E / R on the wafer drops more than the center portion, but V _C / V _E = −300 V / −900 V. In this case, the difference between the center portion and the edge portion is reduced and the in-plane uniformity is greatly improved. What is important here is that, as shown in FIG. 3, the E / R at the center portion hardly changes and the E / R at the edge portion changes significantly. Accordingly, the first DC voltage V _C applied to the inner upper electrode 60 is selected to an appropriate value (preferably −600 V to −150 V), and the second DC voltage V _E applied to the outer upper electrode 62 is set to an appropriate range ( Preferably, the in-plane distribution characteristics of E / R can be freely controlled, and the in-plane uniformity can be easily improved.

Since the BEOL etching is the same process as the blanket SiO ₂ film etching, the plasma etching method can be applied as it is. Note that N ₂ gas may be used instead of O ₂ gas as an additive gas for the etching gas used for etching the Si-containing insulating film.

FIG. 4 shows the in-plane distribution characteristics of the etching rate (E / R) obtained in the HARC etching experiment in which a contact hole having a diameter of 0.25 μm is formed in the SiO ₂ film using the plasma etching apparatus of the embodiment. . The main etching conditions are the same as those for the blanket SiO ₂ film, and the second DC voltage V _E is two types, −300V and −900V. FIG. 5 shows the E / R change rate at each position on the wafer when the second DC voltage V _E is changed from −300V to −900V.

As shown in FIG. 4 and FIG. 5, the same characteristics as the etching of the blanket SiO ₂ film were obtained with HARC. That is, the first DC voltage V _C applied to the inner upper electrode 60 is selected to an appropriate value (for example, −300 V), and the second DC voltage V _E applied to the outer upper electrode 62 is within the range of −900 V to −300 V. , The E / R of the edge is remarkably changed without substantially changing the E / R of the center, and the profile of the E / R distribution characteristics on the wafer is lower than that of the center. It can be seen that both the profile in which the edge portion is substantially flat (uniform) and the profile in which the edge portion is higher than the center portion can be easily realized.

In the plasma etching apparatus of this embodiment, a configuration in which a step is provided in the electrode gap direction between the inner upper electrode 60 and the outer upper electrode 62 is preferable. On the other hand, the structure which makes the outer side upper electrode 62 protrude below can be taken. 6, the inter-electrode gap D _C of the semiconductor wafer W on the inner upper electrode 60 and the susceptor 12 is set to, for example, 30 cm, gap between electrodes D _E of the focus phosphorus ring 38 on the outer upper electrode 62 and the susceptor 12 May be set to 20 to 25 cm, for example.

FIG. 7 shows experimental results (E / R distribution characteristics) in which the present invention is applied to HARC under the same etching conditions as described above using the plasma etching apparatus of the embodiment employing the stepped electrode gap structure of FIG. According to the experimental results, the in-plane uniformity of E / R was improved to ± 0.9% under the conditions of V _C = −300 V and V _E = −600 V.

In the application of the present invention to HARC, the first DC voltage V _C can be selected within the range of −600 V to −150 V under the condition that the relationship | V _C | ≦ | V _E | is maintained. The second DC voltage V _E can be selected within a range of −1000V to −150V. Moreover, the second high frequency applied to the susceptor 12 is preferably a low frequency so that ions can be strongly implanted into the film to be processed in the etching process of the connection hole, and may be preferably selected from 2 MHz to 3.2 MHz.

In the etching of the Si-containing film, can control the profile of the E / R distribution characteristic of the semiconductor wafer W by changing the value of the second DC voltage V _E as described above, the value of the second DC voltage V _E This is because the electron density (Ne) distribution characteristic on the semiconductor wafer W can be controlled by changing, and there is a correlation between the Ne distribution characteristic and the E / R distribution characteristic.

As an example, the Ne distribution characteristic and the Ne change rate distribution characteristic obtained when the value of the second DC voltage V _E is varied by the HARC etching are shown in FIGS. 8 and 9, respectively. As shown in the figure, when the absolute value of the second DC voltage V _E is increased from 0V → 300V → 600V → 900V, Ne at the wafer center changes slightly, but Ne at the wafer periphery changes greatly. It was confirmed that there was a correlation with the E / R distribution characteristics.

  The plasma etching apparatus and the plasma etching method of the present invention can be suitably applied to an application for continuously etching a multilayer film on a substrate surface in a plurality of steps. Examples of the present invention relating to the multilayer resist method as shown in FIG. 10 will be described below.

  In FIG. 10, an SiN layer 102 is formed on the main surface of a semiconductor wafer W to be processed as a lowermost layer (final mask) on an original film to be processed (for example, a Si film for a gate) 100. An organic film (for example, carbon) 104 is formed as an intermediate layer, and an uppermost photoresist 108 is formed thereon via a Si-containing antireflection film (BARC) 106. For the formation of the SiN layer 102, the organic film 104 and the antireflection film 106, a coating film by CVD (chemical vacuum deposition) or spin-on is used, and for the patterning of the photoresist 108, photolithography is used.

First, the Si-containing antireflection film 106 was etched using the patterned photoresist 108 as a mask as shown in FIG. The main etching conditions are as follows.
Wafer diameter: 300mm
Etching gas: CF ₄ / O ₂ = 250/13 sccm
Pressure in chamber: 30mTorr
High frequency power: 40MHz / 13MHz = 400 / 0W
DC voltage: V _C = 0V, V _E = 0V, -300V, -600V (3 types)

Although not shown in the drawings, the in-plane distribution characteristics of the etching rate can be changed by changing the absolute value of the second DC voltage V _E when the antireflection film 106 is etched.

Next, as shown in FIG. 10B, the organic film 104 was etched using the photoresist 108 and the antireflection film 106 as a mask. The main etching conditions are as follows.
Wafer diameter: 300mm
Etching gas: O ₂ = 750 sccm
Pressure in chamber: 20mTorr
Temperature: Upper electrode / chamber sidewall / lower electrode = 150/150/30 ° C.
High frequency power: 40MHz / 13MHz = 400 / 200W
DC voltage: V _C = 0V, V _E = 0V, -300V, -600V (3 types)

  FIG. 11 shows in-plane distribution characteristics of the etching rate (E / R) obtained by etching the organic film 104. FIG. 12 shows the in-plane distribution characteristics of the rate of change of E / R.

As shown in FIG. 11, in the organic film etching, the first DC voltage V _C applied to the inner upper electrode 60 is fixed to a constant value (0V), and the second DC voltage applied to the outer upper electrode 62 with a negative polarity. When the absolute value of V _E is changed, the E / R of the wafer edge portion is almost constant. When V _E = 0V, the profile becomes a high chevron that rises at the center of the wafer, and when V _E = −300V, E / R. Is a low chevron profile that rises small at the center of the wafer, and when V _E = −600 V, it becomes a pan-bottom profile that falls greatly at the center of the wafer. Therefore, it can be easily estimated that an almost flat E / R profile is obtained in the middle of V _E = −600 V to −300 V (around −400 V).

As described above, when the absolute value of the second DC voltage V _E is changed in the application of the organic film etching of the present invention, unlike the etching of the Si-containing insulating film, the E / R of the peripheral portion of the wafer is hardly changed. The E / R at the center of the wafer changes. Although this principle (action) is not yet clear, it is considered that the interaction between the plasma (oxygen plasma) and the upper electrodes (60, 62) is more dominant than the distribution characteristics of the electron density (Ne).

In the organic film etching according to the present invention, the first DC voltage V _C may be selected within a range of −100 V to 0 V, and the second DC voltage V _E may be selected within a range of −900 V to 0 V. . When the accuracy of the pattern processing shape is important, the frequency of the second high frequency may be selected in a higher region (preferably 10 MHz to 13.56 MHz) so as to lower the energy of ion attraction. As an etching gas, N ₂ gas, CO, COS, H ₂ , or NH ₃ may be added to O ₂ gas. The following can be mentioned as gas combinations in organic film etching.

O ₂ , O ₂ / N ₂ , O ₂ / CO, O ₂ / SO ₂ , O ₂ / COS, O ₂ / NH ₃ , N ₂ / H ₂ , NH ₃ , N ₂ / H ₂ / O ₂

FIG. 13 shows a cross-sectional view (SEM photograph) of a pattern obtained by etching the antireflection film 106 and the organic film 104. As shown in the figure, when the absolute value of the second DC voltage V _E is increased from 0V → 400V → 900V, the shoulder slip (106 ′) of the antireflection film 106 at the upper end of the pattern is reduced, and the verticality of the pattern is increased. Can be seen to improve. This effect is noticeable in a sparse pattern (right side) rather than a dense pattern (left side). Further, when the value of the second DC voltage V _E is changed, the accuracy and uniformity of the pattern CD changes in the wafer radial direction (between the center portion and the edge portion), and V _E increases from 0V → 400V → 900V. It can also be seen that CD accuracy and uniformity improve as the process proceeds.

In FIG. 10 again, as shown in FIGS. 10C and 10D, the SiN film 102 was etched using the patterned antireflection film 106 and organic film 104 as a mask. The main etching conditions are as follows.
Wafer diameter: 300mm
Etching gas: CHF ₃ / CF ₄ / Ar / O ₂ = 125/225/600/60 sccm
Pressure in chamber: 75mTorr
Temperature: Upper electrode / chamber sidewall / lower electrode = 150/150/30 ° C.
High frequency power: 40MHz / 13MHz = 0 / 1000W
DC voltage: V _C = −300V, V _E = 0V, −300V, −900V (3 types)

FIG. 14 shows the in-plane distribution characteristics of the etching rate (E / R) obtained by etching the SiN film 102. As shown in the figure, when the first DC voltage V _C is kept at a constant value (−300V) and the absolute value of the second DC voltage V _E is increased from 0V → 300V → 900V, the E / R at the center of the wafer changes greatly. Without any change, the E / R at the wafer peripheral portion changes greatly. This is the same as in the case of the HARC or BEOL.

Further, as shown in FIG. 15, when the absolute value of the second DC voltage V _E is changed from 300 V to 900 V, the CD shift of the pattern changes more greatly at the wafer peripheral (edge) portion than at the wafer central portion. Accordingly, by appropriately selecting the value of the second DC voltage V _E , the uniformity and accuracy of the CD can be improved for each semiconductor wafer, and consequently the pattern transfer accuracy in the multilayer resist method can be improved.

In the etching of the SiN film according to the present invention, the first DC voltage V _C may be selected within a range of −300V to 0V, and the second DC voltage V _E may be selected within a range of −900V to −300V. . Also, since SiN film etching requires radical-based high-accuracy pattern etching, it is desirable to lower the energy of ion attraction, and to increase the frequency of the second high frequency (preferably 10 MHz to 13.3). 56 MHz) may be selected.

  The preferred embodiment of the present invention has been described above, but the present invention is not limited to the above embodiment, and various modifications are possible. In particular, in the plasma etching apparatus used in the etching method of the present invention, various configurations and modifications can be made for the configuration around the inner upper electrode 60 and the outer upper electrode 62.

For example, a configuration in which independent first and second DC voltages V _C and V _E are respectively applied to the inner upper electrode 60 and the outer upper electrode 62 using a single or common variable DC power supply is also possible. For example, in the configuration example shown in FIG. 16, the output terminal of the variable DC power supply 110 is connected to the outer upper electrode 62 via the filter circuit 112 and the changeover switch 114, and the filter circuit 112, the changeover switch 116, and the variable resistor 118 are connected. To the inner upper electrode 60. The direct current voltage V _A output from the variable direct current power supply 110 is applied as it is to the outer upper electrode 62 as the second direct current voltage V _E , and the first voltage obtained by subtracting the voltage drop of the variable resistor 118 from the direct current voltage V _A. A DC voltage V _C is applied to the inner upper electrode 60. Each change-over switch 116, 114 connects the corresponding upper electrode 60, 62 to the ground potential and the through position for passing the output voltage of the variable DC power supply 110 toward the corresponding upper electrode 60, 62 (that is, And a grounding position for applying OV).

  In the configuration example shown in FIG. 16, shower heads are provided on both the inner upper electrode 60 and the outer upper electrode 62. It is also possible to independently select and control the type or flow rate of gas discharged from each shower head.

  Further, the present invention is not limited to the application to the lower two-frequency application method as in the above-described embodiment. For example, plasma of a method in which the first high frequency for plasma generation is applied to the upper electrodes (60, 62). It can also be applied to an etching apparatus.

  The present invention is not limited to a plasma etching apparatus, but can be applied to other plasma processing apparatuses such as plasma CVD, plasma oxidation, plasma nitridation, and sputtering. Further, the substrate to be processed in the present invention is not limited to a semiconductor wafer, and various substrates for flat panel displays, photomasks, CD substrates, printed substrates, and the like are also possible.

10 chamber (processing vessel)
12 Susceptor (lower electrode)
26 Exhaust device 30 First high frequency power supply 32 Second high frequency power supply
60 Inner upper electrode (shower head)
62 outer upper electrode 76 processing gas supply unit 80, 82, 110 variable DC power supply 118 variable resistor

Claims (12)

A processing container capable of being evacuated;
A lower electrode for placing a substrate to be processed in the processing container;
An inner upper electrode disposed directly opposite the lower electrode in the processing vessel;
An outer upper electrode that is electrically insulated from the inner upper electrode in the processing vessel and arranged in a ring shape radially outward;
A processing gas supply unit for supplying a processing gas to a processing space between the inner and outer upper electrodes and the lower electrode;
A first high-frequency power feeding unit that applies a first high frequency for generating plasma of the processing gas by high-frequency discharge to the lower electrode or the inner and outer upper electrodes;
A first DC power supply that applies a variable first DC voltage to the inner upper electrode;
A plasma etching method for etching an insulating film containing Si using a plasma processing apparatus having a second DC power supply unit that applies a variable second DC voltage to the outer upper electrode,
Both the first and second DC voltages are negative in polarity, and the absolute value of the second DC voltage is greater than or equal to the absolute value of the first DC voltage. The insulating film is a SiO ₂ film;
The etching process is a process of forming a contact hole in the SiO ₂ film;
The first DC voltage is selected from -600V to -150V;
The second DC voltage is selected from -1000V to -150V;
The plasma etching method according to claim 1.   The plasma etching method according to claim 2, wherein a frequency of the second high frequency is selected from 2 MHz to 3.2 MHz. The insulating film is a SiOC film;
The etching process is a process of forming a via hole in the SiOC film;
The first DC voltage is selected from -900V to -300V,
The second DC voltage is selected from -1500V to -300V;
The plasma etching method according to claim 1.   The plasma etching method according to claim 4, wherein the frequency of the second high frequency is selected from 10 MHz to 13.56 MHz. The plasma etching method according to claim 1, wherein the processing gas is an etching gas containing a fluorocarbon gas, an inert gas, and an O ₂ gas or an N ₂ gas. The insulating film is a SiN film used for an intermediate layer or a lowermost layer of a multilayer resist;
The etching process is a process for forming a SiN mask for etching a base film or a base substrate,
The first DC voltage is selected from -300V to 0V;
The second DC voltage is selected from -900V to -300V;
The plasma etching method according to claim 1.   The plasma etching method according to claim 7, wherein a frequency of the second high frequency is selected from 10 MHz to 13.56 MHz. A processing container capable of being evacuated;
A lower electrode for placing a substrate to be processed in the processing container;
An inner upper electrode disposed directly opposite the lower electrode in the processing vessel;
An outer upper electrode that is electrically insulated from the inner upper electrode in the processing vessel and arranged in a ring shape radially outward;
A processing gas supply unit for supplying a processing gas to a processing space between the inner and outer upper electrodes and the lower electrode;
A first high-frequency power feeding unit that applies a first high frequency for generating plasma of the processing gas by high-frequency discharge to the lower electrode or the inner and outer upper electrodes;
A first DC power supply that applies a variable first DC voltage to the inner upper electrode;
A plasma etching method for etching an organic film using a plasma processing apparatus having a second DC power supply unit that applies a variable second DC voltage to the outer upper electrode,
Both the first and second DC voltages are negative in polarity, and the absolute value of the second DC voltage is greater than or equal to the absolute value of the first DC voltage. The first DC voltage is selected from -100V to 0V;
The second DC voltage is selected from -900V to 0V;
The plasma etching method according to claim 9.   The plasma etching method according to claim 10, wherein a frequency of the second high frequency is selected from 10 MHz to 13.56 MHz. The plasma etching method according to claim 10 or 11, wherein the processing gas is an etching gas containing O ₂ gas or N ₂ gas.

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