JP2013138103A - Wiring board, electronic component and electronic component manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component which can inhibit disconnection of a conductor pattern adjacent to a semiconductor element; and provide a manufacturing method of the electronic component.SOLUTION: An electronic component 10 includes a conductor part 158S formed directly below a circumference of a semiconductor element 90. The conductor part 158S is provided between an interlayer resin insulation layer 150 in the outermost layer and an underfill material 94 in a thickness direction of the electronic component 10.

Description

The present invention relates to an electronic component in which a semiconductor element is mounted on a wiring board having a resin insulating layer and a conductor pattern and not including a core substrate.

Patent Document 1 discloses an electronic component including a coreless wiring board and a semiconductor element mounted on the upper surface of the wiring board. Usually, such an electronic component has an underfill resin filled between the wiring board and the semiconductor element and a sealing resin for sealing the semiconductor element.

JP 2010-118635 A

As a result of intensive studies, the present inventors have found that the above-described electronic components are susceptible to disconnection of the inner layer conductor pattern by receiving a thermal history. Details will be described below.
FIG. 13 is an explanatory diagram showing a result of simulating thermal expansion and stress generated in the electronic component described above. The electronic component includes a wiring layer 530 having resin insulating layers 550, 650, 750 and conductor patterns 534, 558, 658, and a semiconductor element 590 mounted on the wiring layer 530 via solder bumps 576. An underfill resin 598 is filled between the wiring layer 530 and the semiconductor element 590 and on the side of the semiconductor element. The semiconductor element is sealed with a sealing resin 594.

13A1 and 13A2 illustrate a state in which heat of about 260 ° C. is applied to the electronic component, and FIGS. 13B1 and 13B2 illustrate the electronic component at room temperature.
With regard to the wiring layer constituting such an electronic component, when heat is applied, the region R1 immediately below the semiconductor element is constrained by the semiconductor element via the bump, and thus normally expands in a substantially horizontal direction (FIG. 13). (See (A1)). On the other hand, in the region R2 other than directly below the semiconductor element, the restraint by the semiconductor element is relatively weak, and the underfill resin expands, and is easily swelled by the stress in the arrow Y direction generated at that time.
Thereby, thermal stress is likely to occur in the vicinity of the virtual plane K including the side surface of the semiconductor element. As a result, the conductor pattern 558 located near the virtual plane K is easily disconnected or peeled off.
Even when the electronic component is returned to room temperature from such a heated state, thermal stress is likely to occur near the virtual plane K as the underfill resin contracts, and the same problem is considered to occur (FIG. 13 (B1)). (See (B2)).

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an electronic component capable of suppressing disconnection of a conductor pattern in the vicinity of a semiconductor element and a method for manufacturing the same. There is.

The electronic component of claim 1 includes a plurality of interlayer resin insulation layers, a conductor pattern formed on the interlayer resin insulation layer, and a bump formed on the conductor pattern on the outermost interlayer resin insulation layer. And a semiconductor element mounted on the wiring board via the bump, and a sealing resin that seals the semiconductor element, and the wiring board surrounds the semiconductor element. A technical feature is that at least a part of the conductor part has a conductor part, and at least a part of the conductor part is located immediately below the semiconductor element.

The wiring board constituting the electronic component of claim 1 has a conductor part at least at a part of the periphery of the semiconductor element, and is located at a part of the conductor part immediately below the semiconductor element. That is, the conductor portion is provided at a location where deformation such as expansion or contraction is likely to occur. As a result, the deformation of the interlayer resin insulation layer is suppressed by the conductor portion, and the end portion of the wiring board is hardly warped. Furthermore, since the conductor part is provided over the position (virtual plane K including the side surface of the semiconductor element) that becomes the starting point of the warp, the warp of the end portion of the wiring board is more easily suppressed.

It is a manufacturing-process figure of the electronic component of 1st Embodiment of this invention. It is a manufacturing process figure of the electronic component of 1st Embodiment. It is a manufacturing process figure of the electronic component of 1st Embodiment. It is a manufacturing process figure of the electronic component of 1st Embodiment. It is a manufacturing process figure of the electronic component of 1st Embodiment. It is a manufacturing process figure of the electronic component of 1st Embodiment. It is sectional drawing of the electronic component of 1st Embodiment. It is sectional drawing of the electronic component which concerns on the 2nd modification of 1st Embodiment. FIG. 9A is a cross-sectional view of an electronic component according to a second modification of the first embodiment, and FIG. 9B is a cross-sectional view of an electronic component according to the third modification. FIG. 10A is a cross-sectional view of an electronic component according to the second embodiment, and FIG. 10B is a cross-sectional view of the electronic component according to the third embodiment. FIG. 11A is a plan view of the wiring board according to the first embodiment, and FIG. 11B is a plan view of the wiring board according to the fourth modification of the first embodiment. FIG. 12A is a plan view of a wiring board according to a second modification of the first embodiment, and FIG. 12B is a plan view of the wiring board according to the third embodiment. It is explanatory drawing which shows the result of having simulated the thermal expansion and stress which arise in an electronic component.

[First embodiment]
FIG. 7 is a cross-sectional view of the electronic component 10 of the first embodiment.
The electronic component 10 includes a wiring board 30 in which a conductor pattern and a resin insulating layer are stacked, and a semiconductor element 90 mounted on the wiring board 30.
The wiring board 30 has a first surface F and a second surface S opposite to the first surface, the second surface-side conductor pattern 34, the first resin insulating layer 50, and the first resin insulating layer. 50 formed on the first resin pattern 58, the second resin insulation layer 150 formed on the first resin insulation layer 50 and the first conductor pattern 58, and the second resin insulation layer 150. The second conductor pattern 158 is provided. Solder bumps 98 for connecting an external substrate are formed on the conductor pattern 34.
The thickness of the wiring board 30 is 100 μm or less.

The conductor pattern 34 and the first conductor pattern 58 are connected via a first via conductor 60 formed in the first resin insulation layer 50. The first conductor pattern 58 and the second conductor pattern 158 are connected via a second via conductor 160 formed in the second resin insulation layer 150.
Solder bumps 76 are formed on the second conductor pattern 158. The semiconductor element 90 is mounted by the solder bumps 76. An underfill 94 is filled between the semiconductor element 90 and the wiring board 30.
The semiconductor element 90 is sealed with a mold resin 96.

The first resin insulation layer 50 and the second resin insulation layer 150 are a thermosetting resin, a photosensitive resin, a resin in which a photosensitive group is added to a part of the thermosetting resin, a thermoplastic resin, or these resins. Is a layer made of a resin composite or the like. The underfill 94 and the mold resin 96 are made of an epoxy resin containing inorganic and organic fillers.

On the second resin insulation layer 150, a conductor portion 158S is provided. The conductor portion 158 </ b> S is provided around the semiconductor element 90 on the second resin insulating layer 150. That is, as shown in FIG. 11A, a frame is formed around the semiconductor element 90. The conductor portion 158S is provided between the underfill 94 and the second resin insulating layer 150 in the thickness direction of the electronic component. The conductor portion 158S is provided up to the outer end of the second resin insulation layer 150. A part of the conductor portion 158 </ b> S is located in the region R <b> 1 immediately below the semiconductor element 90. The conductor portion 158S functions as a power source or ground conductor.

In the present embodiment, if the electronic component is exposed to a high temperature, the underfill 94 expands, and the stress generated at that time is applied to the end of the wiring board. As a result, waviness is likely to occur at the end of the wiring board. However, in this embodiment, the stress generated by the expansion of the underfill 94 is relaxed through the conductor portion 158S. Thereby, the stress added to the edge part of a wiring board is weakened, and it becomes difficult to produce a wave | undulation. As a result, stress applied to the conductor pattern located below the conductor portion 158S is also reduced, and disconnection can be suppressed.

In the electronic component of the first embodiment, since the thickness of the wiring board 30 is 100 μm or less, the rigidity is low, and it is easily affected by the thermal stress accompanying the expansion of the underfill material as described above. However, by providing the conductor portion 158S capable of relieving such thermal stress, the undulation is effectively suppressed, and as a result, it is easy to prevent the conductor pattern from being disconnected.

The manufacturing method of the electronic component of 1st Embodiment is demonstrated with reference to FIGS.
(1) First, a glass plate 20 having a thickness of about 1.1 mm is prepared (FIG. 1A).
The glass plate has a CTE of about 3.3 (ppm) or less so that the difference in coefficient of thermal expansion from the mounted silicon IC chip is small. It is desirable that the transmittance is 90% or more.

(2) A release layer 22 mainly composed of a thermoplastic polyimide resin is provided on the glass plate 20 (FIG. 1B).

(3) A conductor pattern 34 is formed on the release layer 22 (FIG. 1C).

(4) The first insulating layer 50 is formed on the release layer 22 (FIG. 1D).

(5) An electrode body opening 51 that penetrates the first insulating layer 50 and reaches the conductor pattern 34 is provided by a CO2 gas laser (see FIG. 2A).

(6) A conductor layer 52 made of TiN, Ti, and Cu is formed on the first insulating layer 50 by sputtering (FIG. 2B).

(7) A commercially available photosensitive dry film is affixed on the conductor layer 52, and after the photomask film is placed and exposed, it is developed with sodium carbonate to provide a plating resist 54 having a thickness of about 15 μm. (FIG. 2 (C)).

(8) Using the conductor layer 52 as a power feeding layer, electrolytic plating is performed to form an electrolytic plating film 56 (FIG. 2D).

(9) The plating resist 54 is peeled and removed. Then, the conductor layer 52 under the peeled plating resist is removed, and a first conductor pattern 58 and a first via conductor 60 composed of the conductor layer 52 and the electrolytic plating film 56 are formed (FIG. 3A).

(10) Similarly to the above (4) to (7), the second insulating layer 150 having the opening 151 is formed on the first insulating layer 50 and the first conductor pattern 58, and TiN, A conductor layer 152 made of Ti and Cu is formed, and a plating resist 154 having a predetermined pattern is formed (FIG. 3B).

(11) The electrolytic plating film 156 is provided on the portion where the plating resist 154 is not formed, and the second conductor pattern 158, the conductor layer 158S, and the second via conductor 160 are formed (FIG. 3C).

(12) The plating resist 154 is removed, and the conductor layer 152 under the plating resist 154 is removed (FIG. 4A).

(13) The intermediate body 100 is manufactured by forming the solder bumps 76 on the second conductor pattern 158. (FIG. 4B). This intermediate body 100 is formed of a glass plate 20 and a wiring board 30 formed on the glass plate 20.

(14) Next, the semiconductor element 90 is mounted on the intermediate body 100 via the solder bumps 76 (FIG. 5A). At this time, since the glass plate 20 has a thermal expansion coefficient close to that of the semiconductor element 90, the stress applied to the wiring board 30 is reduced.

(15) An underfill 94 is filled between the wiring board 30 and the semiconductor element 90 (FIG. 5B). At this time, the underfill 94 covers the conductor portion 158S.

(16) In the mold, the semiconductor element 90 is sealed with the sealing material 96 (FIG. 6A).

(17) A 308 nm laser beam is transmitted through the glass plate 20 and irradiated onto the release layer 22, and the release layer 22 is softened. And the glass plate 20 is slid with respect to the wiring board 30, and the glass plate 20 peels (FIG. 6 (B)).

(18) The release layer 22 is removed by ashing, and the pad 34 is exposed. Then, solder bumps 98 are formed on the pads 34, and the wiring board 30 is completed (FIG. 7).

[First Modification of First Embodiment]
As shown in FIG. 8, a layer 74 made of solder may be provided on the surface of the conductor portion 158S. In this case, by providing a layer made of a material (solder) whose Young's modulus is smaller than that of copper, the stress associated with the expansion of the underfill material as described above is easily relaxed by the conductor portion 158S.

[Second modification of the first embodiment]
FIG. 9A is a cross-sectional view of an electronic component according to a second modification of the first embodiment, and FIG. 12A is a plan view of a second insulating layer of the electronic component. In the first embodiment, the conductor portion 158 </ b> S is provided up to the outer end of the second resin insulation layer 150. On the other hand, in the second modification of the first embodiment, the conductor portion does not extend to the outer end, and is provided only directly under the periphery of the semiconductor element. In the second modification of the first embodiment, the shrinkage difference in each insulating layer can be reduced by reducing the conductor area and reducing the area difference of the conductor pattern on each insulating layer.

[Third Modification of First Embodiment]
FIG. 9B is a cross-sectional view of an electronic component according to a third modification of the first embodiment. That is, the conductor portion 74S is made only of solder. Thereby, it is considered that the stress accompanying expansion of the underfill material can be more easily relaxed.

[Fourth modification of the first embodiment]
FIG. 11B is a plan view of an electronic component according to a fourth modification of the first embodiment. In the first embodiment, the conductor portion 158S is annularly formed on the outer periphery of the semiconductor element. In contrast, in the fourth modification of the first embodiment, a plurality of rectangular conductor portions 74S are arranged along the outer periphery of the semiconductor element. According to this, the shrinkage difference in each insulating layer can be reduced by reducing the area difference of the conductor pattern on each insulating layer.

[Second Embodiment]
FIG. 10A is a cross-sectional view of an electronic component according to the second embodiment. In the second embodiment, dummy bumps 76D are provided in the vicinity of the end of the semiconductor element of the conductor portion 158S, dummy via conductors 160D and 60D and dummy bumps 98D connected to the conductor portion 158S are provided, and the electronic component 10 is mounted. Heat is conducted to the through-hole conductor 306 on the substrate 300 side. The electronic component of the second embodiment is excellent in heat dissipation.

[Third embodiment]
FIG. 10B is a cross-sectional view of the electronic component according to the third embodiment, and FIG. 12B is a plan view of the wiring board. In the third embodiment, a third insulating layer 250 is further provided on the second insulating layer, and the semiconductor element 90 is connected via the third via conductor 260 and the third conductor pattern 258 provided in the third insulating layer. Is taken. In the third embodiment, the conductor portion 75 </ b> S is provided between the second insulating layer 150 and the third insulating layer 250.
Even when the conductor portion 75S is provided in the inner layer of the wiring board, it is possible to effectively suppress the disconnection of the conductor pattern provided below the conductor portion 75S.

DESCRIPTION OF SYMBOLS 10 Electronic component 30 Wiring board 50 1st interlayer resin insulation layer 58 1st wiring pattern 60 1st via conductor 76 Solder bump 94 Underfill 96 Mold resin 90 Semiconductor element 150 2nd interlayer resin insulation layer 158 2nd wiring pattern 158S Conductor part

Claims (13)

A wiring board comprising a plurality of interlayer resin insulation layers, a conductor pattern formed on the interlayer resin insulation layer, and a bump formed on a conductor pattern on the outermost interlayer resin insulation layer;
A semiconductor element mounted on the wiring board via the bump;
An underfill material filled between the semiconductor element and the wiring board;
An electronic component having a sealing resin for sealing the semiconductor element,
The wiring board has a conductor part at least at a part around the semiconductor element, and at least a part of the conductor part is located immediately below the semiconductor element. The electronic component of claim 1, wherein:
The conductor portion is provided over the entire outer periphery of the semiconductor element. The electronic component of claim 2, wherein:
The said conductor part is provided to the edge of a wiring board over the perimeter of the outer periphery of the said semiconductor element. The electronic component of claim 1, wherein:
The conductor portion is provided on the outermost interlayer resin insulation layer. The electronic component of claim 1, wherein:
The conductor portion is provided between the outermost interlayer resin insulation layer and the underfill in the thickness direction. The electronic component of claim 1, wherein:
The surface of the conductor pattern provided on the outermost interlayer resin insulation layer and the surface of the conductor portion are located on substantially the same plane. The electronic component of claim 1, wherein:
The conductor portion functions as a power source or ground conductor. The electronic component of claim 1, wherein:
The wiring board has a thickness of 100 μm or less. The electronic component of claim 1, wherein:
A layer made of solder is formed on the conductor portion. The electronic component of claim 1, wherein:
The conductor portion is formed only from solder. A wiring board comprising a plurality of interlayer resin insulation layers, a conductor pattern formed on the interlayer resin insulation layer, and a bump formed on a conductor pattern on the outermost interlayer resin insulation layer is prepared. And
Mounting a semiconductor element on the wiring board via the bump;
Sealing the semiconductor element with a sealing resin;
A method of manufacturing an electronic component including:
On the interlayer resin insulation layer forming the wiring board, a conductor portion is formed on at least a part of the periphery of the semiconductor element,
At least a part of the conductor is provided directly below the semiconductor element. 12. The method of manufacturing an electronic component according to claim 11, wherein:
The conductor portion is provided on the outermost interlayer resin insulation layer. A wiring comprising a plurality of interlayer resin insulation layers, a conductor pattern formed on the interlayer resin insulation layer, and a bump formed on the conductor pattern on the outermost interlayer resin insulation layer and connecting a semiconductor element A board,
The wiring board has a conductor part in at least a part of the periphery of the semiconductor element, and at least a part of the conductor part is located immediately below the semiconductor element.

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