JP2013137707A - Processor and debug device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor capable of reducing the number of deleting/writing times with respect to a flash memory when returning from a break state.SOLUTION: An instruction decoder 24 decodes a fetched instruction. A control unit 25 controls a processor 11 according to a decoded result by the instruction decoder 24. When an interruption restoration instruction is decoded by the instruction decoder 24 while the processor 11 is in a brake state, an instruction replacement unit 26 replaces a fetched return destination instruction by an original instruction to be saved in a stack according to the control by the control unit 25, and causes the instruction decoder 24 to decode it. This configuration can thus reduce the number of deleting/writing times with respect to the flash memory.

Description

  The present invention relates to a technique for debugging a program or the like executed by a processor, and in particular, a processor having a function for realizing a software break (hereinafter abbreviated as an S / W break) and a debugging apparatus using the processor. About.

  In recent years, CPUs (Central Processing Units) have become more sophisticated and multifunctional, and various debugging functions have been developed to debug them. One of the debugging functions is an S / W break function.

  The S / W break function is realized by rewriting an original instruction at a specified address as a breakpoint to a break instruction. When the CPU to be debugged is executing a program, if a break instruction at a specified address is executed, an interrupt is generated and the CPU transits to a break state. Here, the original instruction refers to the original instruction of the program.

  When the CPU resumes program execution without releasing the S / W breakpoint, the break instruction at the designated address is first written back to the original instruction. Then, after the CPU executes step execution of the original instruction, the original instruction at the designated address is rewritten to a break instruction again, and the CPU resumes execution of instructions following the next instruction. As techniques related to this, there are inventions disclosed in Patent Document 1 and Patent Document 2 below.

  Patent Document 1 aims to provide an in-circuit emulator device and an in-circuit emulation method capable of simplifying a monitor program. The emulation memory that stores the monitor program, the register that stores the original instruction of the user program that was originally stored at the address of the emulation memory where the break occurred, and the output and register of the emulation memory according to the switching signal A multiplexer that selectively outputs one of the outputs, and the original instruction of the user program instead of the instruction that generates a break that is replaced with the address where the break occurred as the first instruction after returning from the monitor program to the user program And a control circuit for generating a switching signal for controlling to output the command.

  Patent Document 2 aims to simplify debugging work by debugging in a conversational form without operating hardware when debugging a program operating in an offline state. Link the debug program and the program to be debugged, jump from any breakpoint in the debugged program to the break means, transfer control from the debugged program to the debug program, and wait for input in the command input analysis means Realize the halt.

Japanese Patent Laid-Open No. 10-011315 Japanese Patent Laid-Open No. 04-332049

  When S / W breakpoints are set in the flash memory, erase / rewrite in block units for writing back from the break instruction to the original instruction, and in block units for rewriting from the original instruction to the break instruction There is a problem in that it is necessary to erase / rewrite, and the response of operation becomes slow.

  In addition, the flash memory has a limit on the number of erase / write operations. For this reason, there has been a problem that if the erasing / rewriting is frequently performed as described above, the lifetime of the flash memory is shortened.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a processor capable of reducing the number of times of erasing / writing to the flash memory when returning from a break state, and debugging using the processor. Is to provide a device.

  According to an embodiment of the present invention, there is provided a processor that generates an interrupt and transitions to a break state when a break instruction is executed. The instruction decoder decodes the fetched instruction. The control unit controls the processor according to the decoding result by the instruction decoder. When an interrupt return instruction is decoded by the instruction decoder while the processor is in a break state, the instruction replacement unit replaces the fetched return destination instruction with the original instruction saved in the stack under the control of the control unit. To be decoded by the instruction decoder.

  According to one embodiment of the present invention, the instruction replacement unit replaces the fetched return destination instruction with the original instruction saved in the stack and causes the instruction decoder to decode in accordance with control by the control unit. It is possible to reduce the number of times of erasing / writing with respect to.

It is a figure which shows the structural example of the system containing the debugging apparatus for debugging the user system containing the processor in embodiment of this invention. It is a block diagram for demonstrating the internal structure of CPU11 in embodiment of this invention. It is a figure for demonstrating operation | movement when CPU11 in embodiment of this invention performs the interruption return command with a designation | designated command. It is a figure for demonstrating the S / W break function of the system containing CPU11 in embodiment of this invention. It is a figure for demonstrating the operation | movement (the 1) when instruction execution by CPU11 reaches an S / W breakpoint. It is a figure for demonstrating operation | movement (the 2) when instruction execution by CPU11 reaches an S / W breakpoint. It is a figure for demonstrating operation | movement (the 3) when instruction execution by CPU11 reaches an S / W breakpoint. It is a figure for demonstrating the operation | movement at the time of the interruption generation | occurrence | production by the break instruction of CPU11 in embodiment of this invention. It is a figure for demonstrating the process when CPU11 restarts execution from a break state. It is a figure for demonstrating a process when CPU11 in embodiment of this invention performs the interruption return instruction with a designation | designated instruction. It is a figure for demonstrating operation | movement (the 1) when CPU11 in embodiment of this invention performs the process instruct | indicated from the debugger apparatus. It is a figure for demonstrating operation | movement (the 2) when CPU11 in embodiment of this invention performs the process instruct | indicated from the debugger apparatus. It is a figure for demonstrating operation | movement (the 3) when CPU11 in embodiment of this invention performs the process instruct | indicated from the debugger apparatus. It is a figure for demonstrating operation | movement (the 4) when CPU11 in embodiment of this invention performs the process instruct | indicated from the debugger apparatus. It is a figure for demonstrating the whole operation | movement when CPU11 in embodiment of this invention fetches and executes the interruption return instruction with a designated instruction.

  FIG. 1 is a diagram illustrating a configuration example of a debugging device for debugging a user system including a processor according to an embodiment of the present invention. This system includes a host machine 1, an emulator 2, and a user system 3. The user system 3 is one of computer systems and includes a CPU 11 to be debugged, a debug control circuit 12, a RAM 13, and a flash memory (hereinafter simply referred to as a ROM) 14, and a bus 15 is provided. These are connected through.

The host machine 1 is a computer device such as a PC (Personal Computer), and executes a program (debugger) for supporting debugging of the user system 3. This debugger provides a function in which an operator interactively controls the execution of a program in the user system 3 and changes register values in the CPU 11 and memory contents such as the RAM 13 and the ROM 14.
The debugger communicates with the emulator 2 via a communication I / F (Interface) such as USB (Universal Serial Bus) in the host machine 1 and operates in cooperation with the emulator 2.

  The emulator 2 is a device used for debugging a program executed by the CPU 11 in the user system 3 which is a computer system. The emulator 2 communicates with the debug control circuit 12 via a communication I / F such as JTAG (Joint Test Action Group), executes execution control of the CPU 11 in the user system 3, obtains or changes the register value in the CPU 11, and the RAM 13 Controls debugging functions such as acquisition and modification of memory contents such as ROM 14.

  The debug control circuit 12 operates under the control of the emulator 2, and executes execution control of the CPU 11, acquisition and change of register values in the CPU 11, acquisition and change of memory contents such as the RAM 13 and ROM 14, and execution of a program at a specified address. Realize debugging functions such as breakpoints to stop.

  As a breakpoint, there are an S / W break function that realizes a break by replacing an original instruction at a specified address with an instruction for a break, and an H / W break function that is realized by providing a dedicated register for setting conditions such as an address is there.

  The S / W break function is realized by replacing the original instruction at the breakpoint address with a break instruction as described above. The CPU 11 in the user system 3 replaces the breakpoint with the breakpoint while executing the program. When the given break instruction is executed, an interrupt is generated and the break state is entered.

  In this embodiment, the case where the emulator 2 and the debug control circuit 12 exist will be described. However, a monitor program for collecting information of the CPU 11 is written in advance in a part of the ROM 14, and the UART (Universal Asynchronous Receiver Transmitter), a method in which the monitor program and the host machine 1 communicate directly via a communication I / F such as USB may be used.

  FIG. 2 is a block diagram for explaining the internal configuration of the CPU 11 according to the embodiment of the present invention. The CPU 11 includes an address register 21, a program counter 22, an instruction register 23, an instruction decoder 24, a control unit 25, an instruction replacement unit 26, a data register 27, an ALU (Arithmetic Logical Unit) 28, and an accumulator. 29, and operates in synchronization with the clock pulse. The instruction replacement unit 26 originally includes an instruction temporary storage register 30.

  The address register 21 is a register that holds an address used when the CPU 11 accesses an instruction or data to a memory or I / O (Input / Output). For example, when fetching an instruction, the program counter 22 is used. Holds the value stored in.

  The program counter 22 stores an address on the memory of an instruction to be executed next, and is controlled by the control unit 24.

  The instruction register 23 is a register that holds an instruction fetched by an instruction fetch unit (not shown) under the control of the control unit 25, and transfers the held instruction to the instruction decoder 24.

  The instruction decoder 24 decodes the instruction transferred from the instruction register 23 and transfers the decoding result to the control unit 25. The control unit 25 controls each block such as the ALU 28 and the accumulator 29 in the CPU 11 according to the decoding result by the instruction decoder 24.

  The instruction replacement unit 26 receives a control signal from the control unit 25 when the instruction decoder 24 decodes an “interrupt return instruction with a designated instruction” described later, and stores the original instruction acquired from the stack in the original instruction temporary storage register. When the control unit 25 executes the “interrupt return instruction with a designated instruction” and returns from the interrupt, the instruction fetched from the return destination PC (program counter) is stored in the instruction register 23. However, the instruction replacement unit 26 originally stores a part or all of the return destination instruction stored in the instruction register 23 in the instruction temporary storage unit 30 before the return destination instruction is decoded by the instruction decoder 24. The original instruction is replaced and stored in the instruction register 23. As a result, the CPU 11 originally executes the instruction after executing the “interrupt return instruction with designated instruction”.

  The instruction replacement unit 26 stores the instruction stored in the data register 27 as it is in the instruction register 23 when no other instruction replacement is required. The instruction register 23 receives a control signal from the control unit 25, holds the instruction stored in the data register 27 or the instruction replaced by the replacement unit 26, and gives the instruction decoder 24 the instruction to decode it.

  The data register 27 is a register that temporarily holds instructions and data read from the memory and I / O by the CPU 11 and data to be written to the memory and I / O. For example, in the case of instruction fetch, the fetched instruction is stored. Is done.

  FIG. 3 is a diagram for explaining an operation when the CPU 11 executes an interrupt return instruction with a designated instruction in the embodiment of the present invention. In Example 1, when returning from an interrupt, the original instruction saved in the stack is acquired as a designated instruction, stored in the instruction temporary storage register 30, and the stack is added after adding 4 to the SP (stack pointer) value. PSW (Program Status Word) saved in is restored. After the SP value is incremented by 4, the PC saved in the stack is restored, and the SP value is incremented by 4.

  In example 2, when returning from an interrupt, the original instruction saved in the stack is acquired as the designated instruction, stored in the instruction temporary storage register 30, and after being added to the SP value by 4, it is saved in the stack. Recover the PC. After the SP value is incremented by 4, the PSW saved in the stack is restored, and the SP value is incremented by 4.

  In the example 3, when returning from the interrupt, the PC saved in the stack is restored, and after adding the SP value by 4, the PSW saved in the stack is restored. Then, the SP value is further incremented by 4, and the original instruction saved in the stack is acquired as the designated instruction and stored in the original instruction temporary storage register 30, and the SP value is incremented by 4.

  Example 4 shows a case where a PC saving register and a PSW saving register are provided as dedicated registers. The value of the PC saving register is restored to PC, the value of the PSW saving register is restored to PSW, and The original instruction saved in the stack is acquired as the designated instruction and stored in the original instruction temporary storage register 30, and the value of SP is incremented by four.

  In any case of Examples 1 to 4, as described above, after returning from the interrupt, the original instruction originally stored in the instruction temporary storage register 30 is executed instead of the break instruction set in the PC. It will be.

FIG. 4 is a diagram for explaining the S / W break function of the system including the CPU 11 according to the embodiment of the present invention. First, when the debugger operator uses the host machine 1 to instruct the debugger to set an S / W breakpoint, the debugger device instructs the CPU 11 to embed a break instruction in the S / W breakpoint setting address.
This instruction is performed via a communication I / F between the emulator 2 and the debug control circuit 12 or the monitor program. Here, the debugger device is assumed to be configured by emulator control software (debugger) operating on the host computer 1 and the emulator 2.

  Finally, the CPU 11 rewrites the original instruction at the S / W breakpoint setting address with a break instruction in accordance with an instruction from the emulator 2.

5 to 7 are diagrams for explaining operations when instruction execution by the CPU 11 reaches an S / W breakpoint. Note that the order in which the PC value and the PSW value are saved differs depending on the specifications of the CPU 11.
FIG. 5 shows a case corresponding to the specification of Example 1 of FIG. When the CPU 11 executes a break instruction at a specified address, an interrupt is generated and a break state is entered. At this time, the CPU 11 saves the value of PSW in the stack after saving the value of PC in the stack.

  FIG. 6 shows a case corresponding to the specifications of Example 2 and Example 3 of FIG. When the CPU 11 executes a break instruction at a specified address, an interrupt is generated and a break state is entered. At this time, the CPU 11 saves the PC value in the stack after saving the PSW value in the stack.

  FIG. 7 shows a case corresponding to the specification of Example 4 of FIG. Since the PC saving register and the PSW saving register are provided as the dedicated registers, the PC value and the PSW value are not saved in the stack as shown in FIG. Further, as shown in FIG. 7B, the PC value is stored in the PC saving register, and the PSW value is stored in the PSW saving register.

  FIG. 8 is a diagram for explaining an operation when an interrupt is generated by the break instruction of the CPU 11 in the embodiment of the present invention. First, when the CPU 11 sequentially executes a program and reaches an S / W breakpoint, an interrupt is generated by executing a break instruction embedded in the address.

  When the interrupt occurs, the CPU 11 saves the PC value and the PSW value of the breakpoint on the stack. This process corresponds to the cases of FIGS.

  Further, when an interrupt occurs, the CPU 11 may save the PC value of the breakpoint in the PC saving register and save the PSW value in the PSW saving register. This process corresponds to the case of FIG.

  Next, the CPU 11 branches to an interrupt processing routine and waits for an instruction from the emulator 2 by the debug control circuit 12. When the process is performed by the monitor program, the interrupt processing routine waits for an instruction from the emulator 2.

FIG. 9 is a diagram for explaining processing when the CPU 11 resumes execution from the break state. First, the debugger operator instructs the debugger to resume execution of the CPU 11 using the host machine 1.
The debugger apparatus instructs the CPU 11 to move the SP (subtract by 4) and store the original instruction of the S / W breakpoint in the stack. This process corresponds to FIG. 11, FIG. 12, and FIG.

  Further, the debugger device instructs the CPU 11 to copy the PC value and the PSW value saved in the stack in the stack, and to store the original instruction of the S / W breakpoint in the stack. , SP movement (subtraction of 4) may be instructed. This process corresponds to FIG.

  When the CPU 11 receives an instruction from the debugging device, the CPU 11 performs processing corresponding to the instruction. These processes will be described later with reference to FIGS.

  Next, when the debug device instructs the CPU 11 to execute the interrupt return instruction with the designated instruction, the CPU 11 executes the designated interrupt return instruction with the designated instruction. This process will be described later with reference to FIGS.

Finally, the CPU 11 sequentially executes the subsequent instructions of the program.
FIG. 10 is a diagram for explaining processing when the CPU 11 executes an interrupt return instruction with a designated instruction in the embodiment of the present invention. First, the CPU 11 acquires the original instruction, the return destination PC value, and the PSW value from the stack. This processing corresponds to Example 1, Example 2, and Example 3 in FIG.

  The CPU 11 may acquire only the original instruction from the stack. This processing corresponds to Example 4 in FIG.

  Next, after the acquired original instruction is stored in the original instruction temporary storage register 30, the PC and PSW are restored with the PC value and the PSW value acquired from the stack. This processing corresponds to Example 1, Example 2, and Example 3 in FIG.

  In addition, after the acquired original instruction is originally stored in the temporary instruction storage register 30, the PC and PSW may be restored with the PC value and the PSW value acquired from the PC saving register and the PSW saving register. This processing corresponds to Example 4 in FIG.

  Next, an instruction is fetched from the return destination PC. At this time, since the instruction is fetched while including the break instruction, the instruction fetched by the instruction replacing unit 26 is replaced with the original instruction stored in the original instruction temporary storage register 30.

  Next, the instruction decoder 24 decodes the original instruction replaced by the instruction replacement unit 26, and the control unit 25 executes the original instruction.

  FIGS. 11 to 14 are diagrams for explaining an operation when the CPU 11 in the embodiment of the present invention performs processing instructed by the debugger device. Note that the address where the instruction is originally saved differs depending on the specifications of the CPU 11.

  FIG. 11 shows a case corresponding to the specification of Example 1 of FIG. The CPU 11 moves the SP (subtracts 4) and stores the original instruction of the S / W breakpoint on the stack. The resume PC and PSW are those saved by the CPU 11 when an interrupt occurs.

  FIG. 12 shows a case corresponding to the specification of Example 2 of FIG. The CPU 11 moves the SP (subtracts 4) and stores the original instruction of the S / W breakpoint on the stack. Note that the PSW and the resume PC are saved by the CPU 11 when an interrupt occurs.

  FIG. 13 shows a case corresponding to the specification of Example 3 of FIG. The CPU 11 copies the restart PC value to the address subtracted by 4, further copies the PSW value to the address subtracted by 4, and stores the original instruction of the S / W breakpoint at the address where the original PSW was. , Move SP (subtract 4).

  FIG. 14 shows a case corresponding to the specification of Example 4 of FIG. The CPU 11 moves the SP (subtracts 4) and stores the original instruction of the S / W breakpoint on the stack. The resume PC and PSW are saved in the PC saving register and the PSW saving register.

  FIG. 15 is a diagram for explaining the overall operation when the CPU 11 fetches and executes an interrupt return instruction with a designated instruction in the embodiment of the present invention. First, when the CPU 11 fetches an interrupt return instruction with a designated instruction (described as an invention instruction in FIG. 15), the instruction decoder 24 decodes the interrupt return instruction with a designated instruction, and the control unit 25 performs an interrupt return instruction with a designated instruction. Start running.

  At this time, the control unit 25 acquires the original instruction, PC value, and PSW value from the stack by memory access, stores the original instruction in the original instruction temporary storage register 30, sets the return PSW to PSW, and sets the return destination PC to Set to PC. This processing corresponds to Examples 1 to 3 in FIG.

  Further, the control unit 25 acquires the original instruction from the stack by memory access and stores it in the original instruction temporary storage register, acquires the return PSW from the PSW save register, sets it to the PSW, and returns from the PC save register. You may make it acquire PC and set to PC. This processing corresponds to Example 4 in FIG.

  Next, the CPU 11 fetches the instruction of the return destination PC. Since this instruction includes a break instruction, the instruction replacement unit 26 originally stores the break instruction in the instruction temporary storage register 30. The original instruction is replaced and stored in the instruction register 23.

  When the instruction decoder 24 decodes the original instruction stored in the instruction register 23, the control unit 25 starts executing the original instruction.

  As described above, according to the CPU 11 in the present embodiment, when executing an interrupt return instruction with a designated instruction, the original instruction saved in the stack is stored in the original instruction temporary storage register 30 and includes the break instruction. However, since the instruction of the return PC value is replaced with the original instruction, it is not necessary to erase / rewrite the flash memory in units of blocks, and it is possible to solve the problem that the operation response becomes slow. It was.

  In addition, since it is not necessary to erase / rewrite the flash memory in units of blocks, it is possible to prevent the problem that the life of the flash memory is shortened.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 host machine, 2 emulator, 3 user system, 11 CPU, 12 debug control circuit, 13 RAM, 14 ROM, 15 bus, 21 address register, 22 program counter, 23 instruction register, 24 instruction decoder, 25 control unit, 26 instruction Replacement part, 27 Data register, 28 ALU, 29 Accumulator, 30 Original instruction temporary storage register.

Claims (5)

A processor that transitions to a break state when an interrupt occurs when a break instruction is executed,
Decoding means for decoding the fetched instruction;
Control means for controlling the processor according to a decoding result by the decoding means;
When an interrupt return instruction is decoded by the decoding means when the processor is in a break state, the fetched return destination instruction is replaced with an original instruction saved in the stack according to control by the control means. A processor including substitution means for causing the decoding means to decode. The replacement means includes holding means for holding the original instruction,
The control means, when the interrupt return instruction is decoded by the decoding means, returns the value of the program counter from the stack, and after returning the value of the program status word from the stack, The processor according to claim 1, wherein the original instruction acquired from the stack is held in the holding unit, and the replacement unit replaces the fetched return destination instruction with the original instruction held in the holding unit. The replacement means includes holding means for holding the original instruction,
The control means, when the interrupt return instruction is decoded by the decoding means, returns the value of the program status word from the stack, and after returning the value of the program counter from the stack, The processor according to claim 1, wherein the original instruction acquired from the stack is held in the holding unit, and the replacement unit replaces the fetched return destination instruction with the original instruction held in the holding unit.   When the interrupt return instruction is decoded by the decoding means, the control means causes the replacement means to hold the original instruction acquired from the stack in the holding means, and the replacement means causes the fetched return destination 2. The processor according to claim 1, wherein after the instruction is replaced with the original instruction held in the holding means, the control means restores the value of the program status word from the stack and restores the value of the program counter from the stack. . A debugging device that debugs a system including a processor that generates an interrupt when a break instruction is executed and enters a break state.
The debugging device includes an original instruction saving unit that saves an original instruction to the stack in response to a program counter and a program status word that the processor saves to the stack when the interrupt occurs.
The processor includes decoding means for decoding the fetched instruction;
Control means for controlling the processor according to a decoding result by the decoding means;
When an interrupt return instruction is decoded by the decoding means while the processor is in a break state, the fetched return destination instruction is replaced with the original instruction saved in the stack according to control by the control means. And a replacement means for causing the decoding means to decode.

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